includes.isa revision 7732
12SN/A// -*- mode:c++ -*- 21762SN/A 32SN/A// Copyright (c) 2010 ARM Limited 42SN/A// All rights reserved 52SN/A// 62SN/A// The license below extends only to copyright in the software and shall 72SN/A// not be construed as granting a license to any other intellectual 82SN/A// property including but not limited to intellectual property relating 92SN/A// to a hardware implementation of the functionality of the software 102SN/A// licensed hereunder. You may use the software subject to the license 112SN/A// terms below provided that you ensure that this notice is replicated 122SN/A// unmodified and in its entirety in all distributions of the software, 132SN/A// modified or unmodified, in source code or in binary form. 142SN/A// 152SN/A// Copyright (c) 2007-2008 The Florida State University 162SN/A// All rights reserved. 172SN/A// 182SN/A// Redistribution and use in source and binary forms, with or without 192SN/A// modification, are permitted provided that the following conditions are 202SN/A// met: redistributions of source code must retain the above copyright 212SN/A// notice, this list of conditions and the following disclaimer; 222SN/A// redistributions in binary form must reproduce the above copyright 232SN/A// notice, this list of conditions and the following disclaimer in the 242SN/A// documentation and/or other materials provided with the distribution; 252SN/A// neither the name of the copyright holders nor the names of its 262SN/A// contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu// this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu// 292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315583Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3556SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37239SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38239SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402SN/A// 412SN/A// Authors: Stephen Hines 425583Snate@binkert.org 435583Snate@binkert.org//////////////////////////////////////////////////////////////////// 445583Snate@binkert.org// 455583Snate@binkert.org// Output include file directives. 462SN/A// 475583Snate@binkert.org 482SN/Aoutput header {{ 492SN/A#include <sstream> 505583Snate@binkert.org#include <iostream> 515583Snate@binkert.org 525583Snate@binkert.org#include "arch/arm/insts/branch.hh" 535583Snate@binkert.org#include "arch/arm/insts/macromem.hh" 545583Snate@binkert.org#include "arch/arm/insts/mem.hh" 555583Snate@binkert.org#include "arch/arm/insts/misc.hh" 565583Snate@binkert.org#include "arch/arm/insts/mult.hh" 575583Snate@binkert.org#include "arch/arm/insts/pred_inst.hh" 585583Snate@binkert.org#include "arch/arm/insts/static_inst.hh" 595583Snate@binkert.org#include "arch/arm/insts/vfp.hh" 605583Snate@binkert.org#include "arch/arm/isa_traits.hh" 615583Snate@binkert.org#include "mem/packet.hh" 625583Snate@binkert.org#include "sim/faults.hh" 635583Snate@binkert.org}}; 642SN/A 655583Snate@binkert.orgoutput decoder {{ 665583Snate@binkert.org#include "arch/arm/faults.hh" 675583Snate@binkert.org#include "arch/arm/intregs.hh" 685583Snate@binkert.org#include "arch/arm/isa_traits.hh" 695583Snate@binkert.org#include "arch/arm/utility.hh" 705583Snate@binkert.org#include "base/cprintf.hh" 715583Snate@binkert.org#include "base/loader/symtab.hh" 725583Snate@binkert.org#include "cpu/thread_context.hh" 735583Snate@binkert.org 745583Snate@binkert.orgusing namespace ArmISA; 752SN/A}}; 765583Snate@binkert.org 772SN/Aoutput exec {{ 78#include "arch/arm/faults.hh" 79#include "arch/arm/isa_traits.hh" 80#include "arch/arm/utility.hh" 81#include "base/condcodes.hh" 82#include "sim/pseudo_inst.hh" 83 84#include <cmath> 85#if defined(linux) 86#include <fenv.h> 87#endif 88 89#include "base/cp_annotate.hh" 90#include "mem/packet.hh" 91#include "mem/packet_access.hh" 92#include "sim/sim_exit.hh" 93 94using namespace ArmISA; 95using std::isnan; 96}}; 97 98