uncond.isa revision 8868:26dbd171754e
15703SN/A// Copyright (c) 2010-2012 ARM Limited 25703SN/A// All rights reserved 39459Ssaidi@eecs.umich.edu// 49459Ssaidi@eecs.umich.edu// The license below extends only to copyright in the software and shall 59459Ssaidi@eecs.umich.edu// not be construed as granting a license to any other intellectual 65703SN/A// property including but not limited to intellectual property relating 79459Ssaidi@eecs.umich.edu// to a hardware implementation of the functionality of the software 89459Ssaidi@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 99459Ssaidi@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 109459Ssaidi@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 119459Ssaidi@eecs.umich.edu// modified or unmodified, in source code or in binary form. 129459Ssaidi@eecs.umich.edu// 139459Ssaidi@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 149459Ssaidi@eecs.umich.edu// modification, are permitted provided that the following conditions are 159459Ssaidi@eecs.umich.edu// met: redistributions of source code must retain the above copyright 169459Ssaidi@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 179459Ssaidi@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 189459Ssaidi@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 199459Ssaidi@eecs.umich.edu// documentation and/or other materials provided with the distribution; 209459Ssaidi@eecs.umich.edu// neither the name of the copyright holders nor the names of its 219459Ssaidi@eecs.umich.edu// contributors may be used to endorse or promote products derived from 229459Ssaidi@eecs.umich.edu// this software without specific prior written permission. 239459Ssaidi@eecs.umich.edu// 249459Ssaidi@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259459Ssaidi@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269459Ssaidi@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279459Ssaidi@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289459Ssaidi@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299459Ssaidi@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309459Ssaidi@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319459Ssaidi@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329459Ssaidi@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339459Ssaidi@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349459Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359459Ssaidi@eecs.umich.edu// 369459Ssaidi@eecs.umich.edu// Authors: Gabe Black 379459Ssaidi@eecs.umich.edu 389459Ssaidi@eecs.umich.edudef format ArmUnconditional() {{ 399459Ssaidi@eecs.umich.edu decode_block = ''' 409459Ssaidi@eecs.umich.edu { 419459Ssaidi@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 429459Ssaidi@eecs.umich.edu const uint32_t op1 = bits(machInst, 27, 20); 439459Ssaidi@eecs.umich.edu if (bits(op1, 7) == 0) { 449459Ssaidi@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 459459Ssaidi@eecs.umich.edu if (op1 == 0x10) { 469459Ssaidi@eecs.umich.edu if (bits((uint32_t)rn, 0) == 1 && op2 == 0) { 479459Ssaidi@eecs.umich.edu return new Setend(machInst, bits(machInst, 9)); 489459Ssaidi@eecs.umich.edu } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) { 499459Ssaidi@eecs.umich.edu const bool enable = bits(machInst, 19, 18) == 0x2; 509459Ssaidi@eecs.umich.edu const uint32_t mods = bits(machInst, 4, 0) | 519459Ssaidi@eecs.umich.edu (bits(machInst, 8, 6) << 5) | 529459Ssaidi@eecs.umich.edu (bits(machInst, 17) << 8) | 539459Ssaidi@eecs.umich.edu ((enable ? 1 : 0) << 9); 549459Ssaidi@eecs.umich.edu return new Cps(machInst, mods); 559459Ssaidi@eecs.umich.edu } 569459Ssaidi@eecs.umich.edu } else if (bits(op1, 6, 5) == 0x1) { 579459Ssaidi@eecs.umich.edu return decodeNeonData(machInst); 589459Ssaidi@eecs.umich.edu } else if (bits(op1, 6, 4) == 0x4) { 599459Ssaidi@eecs.umich.edu if (bits(op1, 0) == 0) { 609459Ssaidi@eecs.umich.edu return decodeNeonMem(machInst); 619459Ssaidi@eecs.umich.edu } else if (bits(op1, 2, 0) == 1) { 629459Ssaidi@eecs.umich.edu // Unallocated memory hint 639459Ssaidi@eecs.umich.edu return new NopInst(machInst); 649459Ssaidi@eecs.umich.edu } else if (bits(op1, 2, 0) == 5) { 659459Ssaidi@eecs.umich.edu const bool add = bits(machInst, 23); 669459Ssaidi@eecs.umich.edu const uint32_t imm12 = bits(machInst, 11, 0); 679459Ssaidi@eecs.umich.edu if (add) { 689459Ssaidi@eecs.umich.edu return new %(pli_iadd)s(machInst, INTREG_ZERO, 699459Ssaidi@eecs.umich.edu rn, add, imm12); 709459Ssaidi@eecs.umich.edu } else { 719459Ssaidi@eecs.umich.edu return new %(pli_isub)s(machInst, INTREG_ZERO, 729459Ssaidi@eecs.umich.edu rn, add, imm12); 739459Ssaidi@eecs.umich.edu } 749459Ssaidi@eecs.umich.edu } 759459Ssaidi@eecs.umich.edu } else if (bits(op1, 6, 4) == 0x5) { 769459Ssaidi@eecs.umich.edu if (bits(op1, 1, 0) == 0x1) { 779459Ssaidi@eecs.umich.edu const bool add = bits(machInst, 23); 789459Ssaidi@eecs.umich.edu const bool pldw = bits(machInst, 22); 799459Ssaidi@eecs.umich.edu const uint32_t imm12 = bits(machInst, 11, 0); 809459Ssaidi@eecs.umich.edu if (pldw) { 819459Ssaidi@eecs.umich.edu if (add) { 829459Ssaidi@eecs.umich.edu return new %(pldw_iadd)s(machInst, INTREG_ZERO, 839459Ssaidi@eecs.umich.edu rn, add, imm12); 849459Ssaidi@eecs.umich.edu } else { 859459Ssaidi@eecs.umich.edu return new %(pldw_isub)s(machInst, INTREG_ZERO, 869459Ssaidi@eecs.umich.edu rn, add, imm12); 879459Ssaidi@eecs.umich.edu } 889459Ssaidi@eecs.umich.edu } else { 899459Ssaidi@eecs.umich.edu if (add) { 909459Ssaidi@eecs.umich.edu return new %(pld_iadd)s(machInst, INTREG_ZERO, 919459Ssaidi@eecs.umich.edu rn, add, imm12); 929312Sandreas.hansson@arm.com } else { 939459Ssaidi@eecs.umich.edu return new %(pld_isub)s(machInst, INTREG_ZERO, 949459Ssaidi@eecs.umich.edu rn, add, imm12); 959312Sandreas.hansson@arm.com } 969312Sandreas.hansson@arm.com } 979312Sandreas.hansson@arm.com } else if (op1 == 0x57) { 989312Sandreas.hansson@arm.com switch (op2) { 999312Sandreas.hansson@arm.com case 0x1: 1009312Sandreas.hansson@arm.com return new Clrex(machInst); 1019459Ssaidi@eecs.umich.edu case 0x4: 1029312Sandreas.hansson@arm.com return new Dsb(machInst); 1039312Sandreas.hansson@arm.com case 0x5: 1049312Sandreas.hansson@arm.com return new Dmb(machInst); 1059312Sandreas.hansson@arm.com case 0x6: 1069312Sandreas.hansson@arm.com return new Isb(machInst); 1079312Sandreas.hansson@arm.com } 1089312Sandreas.hansson@arm.com } 1099312Sandreas.hansson@arm.com } else if (bits(op2, 0) == 0) { 1109459Ssaidi@eecs.umich.edu switch (op1 & 0xf7) { 1119312Sandreas.hansson@arm.com case 0x61: 1129312Sandreas.hansson@arm.com // Unallocated memory hint 1139312Sandreas.hansson@arm.com return new NopInst(machInst); 1149312Sandreas.hansson@arm.com case 0x65: 1159312Sandreas.hansson@arm.com { 1169312Sandreas.hansson@arm.com const uint32_t imm5 = bits(machInst, 11, 7); 1179312Sandreas.hansson@arm.com const uint32_t type = bits(machInst, 6, 5); 1189312Sandreas.hansson@arm.com const bool add = bits(machInst, 23); 1199459Ssaidi@eecs.umich.edu const IntRegIndex rm = 1209312Sandreas.hansson@arm.com (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1219312Sandreas.hansson@arm.com if (add) { 1229459Ssaidi@eecs.umich.edu return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 1239459Ssaidi@eecs.umich.edu add, imm5, type, rm); 1249459Ssaidi@eecs.umich.edu } else { 1259459Ssaidi@eecs.umich.edu return new %(pli_rsub)s(machInst, INTREG_ZERO, rn, 1269459Ssaidi@eecs.umich.edu add, imm5, type, rm); 1279459Ssaidi@eecs.umich.edu } 1289459Ssaidi@eecs.umich.edu } 1299459Ssaidi@eecs.umich.edu case 0x71: 1309459Ssaidi@eecs.umich.edu case 0x75: 1319459Ssaidi@eecs.umich.edu { 1329459Ssaidi@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 1339459Ssaidi@eecs.umich.edu const uint32_t type = bits(machInst, 6, 5); 1349459Ssaidi@eecs.umich.edu const bool add = bits(machInst, 23); 1359459Ssaidi@eecs.umich.edu const bool pldw = bits(machInst, 22); 1369459Ssaidi@eecs.umich.edu const IntRegIndex rm = 1379459Ssaidi@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1389459Ssaidi@eecs.umich.edu if (pldw) { 1399459Ssaidi@eecs.umich.edu if (add) { 1409459Ssaidi@eecs.umich.edu return new %(pldw_radd)s(machInst, INTREG_ZERO, 1419459Ssaidi@eecs.umich.edu rn, add, imm5, 1429459Ssaidi@eecs.umich.edu type, rm); 1439459Ssaidi@eecs.umich.edu } else { 1449459Ssaidi@eecs.umich.edu return new %(pldw_rsub)s(machInst, INTREG_ZERO, 1459459Ssaidi@eecs.umich.edu rn, add, imm5, 1469312Sandreas.hansson@arm.com type, rm); 1479312Sandreas.hansson@arm.com } 1489312Sandreas.hansson@arm.com } else { 1499312Sandreas.hansson@arm.com if (add) { 1509312Sandreas.hansson@arm.com return new %(pld_radd)s(machInst, INTREG_ZERO, 1519312Sandreas.hansson@arm.com rn, add, imm5, 1529312Sandreas.hansson@arm.com type, rm); 1539312Sandreas.hansson@arm.com } else { 1549312Sandreas.hansson@arm.com return new %(pld_rsub)s(machInst, INTREG_ZERO, 1559459Ssaidi@eecs.umich.edu rn, add, imm5, 1569459Ssaidi@eecs.umich.edu type, rm); 1579459Ssaidi@eecs.umich.edu } 1589459Ssaidi@eecs.umich.edu } 1599459Ssaidi@eecs.umich.edu } 1609459Ssaidi@eecs.umich.edu } 1619459Ssaidi@eecs.umich.edu } 1629459Ssaidi@eecs.umich.edu } else { 1639459Ssaidi@eecs.umich.edu switch (bits(machInst, 26, 25)) { 1649459Ssaidi@eecs.umich.edu case 0x0: 1659459Ssaidi@eecs.umich.edu { 1669459Ssaidi@eecs.umich.edu const uint32_t val = ((machInst >> 20) & 0x5); 1679459Ssaidi@eecs.umich.edu if (val == 0x4) { 1689459Ssaidi@eecs.umich.edu const uint32_t mode = bits(machInst, 4, 0); 1699459Ssaidi@eecs.umich.edu if (badMode((OperatingMode)mode)) 1709459Ssaidi@eecs.umich.edu return new Unknown(machInst); 1719459Ssaidi@eecs.umich.edu switch (bits(machInst, 24, 21)) { 1729459Ssaidi@eecs.umich.edu case 0x2: 1739459Ssaidi@eecs.umich.edu return new %(srs)s(machInst, mode, 1749459Ssaidi@eecs.umich.edu SrsOp::DecrementAfter, false); 1759459Ssaidi@eecs.umich.edu case 0x3: 1769459Ssaidi@eecs.umich.edu return new %(srs_w)s(machInst, mode, 1779459Ssaidi@eecs.umich.edu SrsOp::DecrementAfter, true); 1789459Ssaidi@eecs.umich.edu case 0x6: 1799459Ssaidi@eecs.umich.edu return new %(srs_u)s(machInst, mode, 1809459Ssaidi@eecs.umich.edu SrsOp::IncrementAfter, false); 1819459Ssaidi@eecs.umich.edu case 0x7: 1829459Ssaidi@eecs.umich.edu return new %(srs_uw)s(machInst, mode, 1839459Ssaidi@eecs.umich.edu SrsOp::IncrementAfter, true); 1849459Ssaidi@eecs.umich.edu case 0xa: 1859459Ssaidi@eecs.umich.edu return new %(srs_p)s(machInst, mode, 1869459Ssaidi@eecs.umich.edu SrsOp::DecrementBefore, false); 1879312Sandreas.hansson@arm.com case 0xb: 1889459Ssaidi@eecs.umich.edu return new %(srs_pw)s(machInst, mode, 1899459Ssaidi@eecs.umich.edu SrsOp::DecrementBefore, true); 1909459Ssaidi@eecs.umich.edu case 0xe: 1919459Ssaidi@eecs.umich.edu return new %(srs_pu)s(machInst, mode, 1929459Ssaidi@eecs.umich.edu SrsOp::IncrementBefore, false); 1939459Ssaidi@eecs.umich.edu case 0xf: 1949312Sandreas.hansson@arm.com return new %(srs_puw)s(machInst, mode, 1959459Ssaidi@eecs.umich.edu SrsOp::IncrementBefore, true); 1969459Ssaidi@eecs.umich.edu } 1979459Ssaidi@eecs.umich.edu return new Unknown(machInst); 1989459Ssaidi@eecs.umich.edu } else if (val == 0x1) { 1999459Ssaidi@eecs.umich.edu switch (bits(machInst, 24, 21)) { 2009312Sandreas.hansson@arm.com case 0x0: 2019312Sandreas.hansson@arm.com return new %(rfe)s(machInst, rn, 2029312Sandreas.hansson@arm.com RfeOp::DecrementAfter, false); 2039459Ssaidi@eecs.umich.edu case 0x1: 2049459Ssaidi@eecs.umich.edu return new %(rfe_w)s(machInst, rn, 2059459Ssaidi@eecs.umich.edu RfeOp::DecrementAfter, true); 2069459Ssaidi@eecs.umich.edu case 0x4: 2079459Ssaidi@eecs.umich.edu return new %(rfe_u)s(machInst, rn, 2089459Ssaidi@eecs.umich.edu RfeOp::IncrementAfter, false); 2099459Ssaidi@eecs.umich.edu case 0x5: 2109459Ssaidi@eecs.umich.edu return new %(rfe_uw)s(machInst, rn, 2119459Ssaidi@eecs.umich.edu RfeOp::IncrementAfter, true); 2129459Ssaidi@eecs.umich.edu case 0x8: 2139459Ssaidi@eecs.umich.edu return new %(rfe_p)s(machInst, rn, 2149312Sandreas.hansson@arm.com RfeOp::DecrementBefore, false); 2159459Ssaidi@eecs.umich.edu case 0x9: 2169459Ssaidi@eecs.umich.edu return new %(rfe_pw)s(machInst, rn, 2179459Ssaidi@eecs.umich.edu RfeOp::DecrementBefore, true); 2189459Ssaidi@eecs.umich.edu case 0xc: 2199459Ssaidi@eecs.umich.edu return new %(rfe_pu)s(machInst, rn, 2209459Ssaidi@eecs.umich.edu RfeOp::IncrementBefore, false); 2219459Ssaidi@eecs.umich.edu case 0xd: 2229459Ssaidi@eecs.umich.edu return new %(rfe_puw)s(machInst, rn, 2239459Ssaidi@eecs.umich.edu RfeOp::IncrementBefore, true); 2249459Ssaidi@eecs.umich.edu } 2259459Ssaidi@eecs.umich.edu return new Unknown(machInst); 2269459Ssaidi@eecs.umich.edu } 2279459Ssaidi@eecs.umich.edu } 2289459Ssaidi@eecs.umich.edu break; 2299459Ssaidi@eecs.umich.edu case 0x1: 2309459Ssaidi@eecs.umich.edu { 2319459Ssaidi@eecs.umich.edu const uint32_t imm = 2329459Ssaidi@eecs.umich.edu (sext<26>(bits(machInst, 23, 0) << 2)) | 2339459Ssaidi@eecs.umich.edu (bits(machInst, 24) << 1); 2349459Ssaidi@eecs.umich.edu return new BlxImm(machInst, imm, COND_UC); 2359459Ssaidi@eecs.umich.edu } 2369459Ssaidi@eecs.umich.edu case 0x2: 2379459Ssaidi@eecs.umich.edu if (bits(op1, 4, 0) != 0) { 2389459Ssaidi@eecs.umich.edu if (CPNUM == 0xa || CPNUM == 0xb) { 2399459Ssaidi@eecs.umich.edu return decodeExtensionRegLoadStore(machInst); 2409459Ssaidi@eecs.umich.edu } 2419459Ssaidi@eecs.umich.edu if (bits(op1, 0) == 1) { 2429459Ssaidi@eecs.umich.edu if (rn == INTREG_PC) { 2439459Ssaidi@eecs.umich.edu if (bits(op1, 4, 3) != 0x0) { 2449459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2459459Ssaidi@eecs.umich.edu "ldc, ldc2 (literal)", machInst); 2469459Ssaidi@eecs.umich.edu } 2479459Ssaidi@eecs.umich.edu } else { 2489459Ssaidi@eecs.umich.edu if (op1 == 0xC3 || op1 == 0xC7) { 2499459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2509459Ssaidi@eecs.umich.edu "ldc, ldc2 (immediate)", machInst); 2519459Ssaidi@eecs.umich.edu } 2529459Ssaidi@eecs.umich.edu } 2539459Ssaidi@eecs.umich.edu if (op1 == 0xC5) { 2549459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2559459Ssaidi@eecs.umich.edu "mrrc, mrrc2", machInst); 2569459Ssaidi@eecs.umich.edu } 2579459Ssaidi@eecs.umich.edu } else { 2589459Ssaidi@eecs.umich.edu if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) { 2599459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2609459Ssaidi@eecs.umich.edu "stc, stc2", machInst); 2619459Ssaidi@eecs.umich.edu } else if (op1 == 0xC4) { 2629459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2639459Ssaidi@eecs.umich.edu "mcrr, mcrrc", machInst); 2649459Ssaidi@eecs.umich.edu } 2659459Ssaidi@eecs.umich.edu } 2669459Ssaidi@eecs.umich.edu } 2679459Ssaidi@eecs.umich.edu break; 2689459Ssaidi@eecs.umich.edu case 0x3: 2699459Ssaidi@eecs.umich.edu if (bits(op1, 4) == 0) { 2709459Ssaidi@eecs.umich.edu if (CPNUM == 0xa || CPNUM == 0xb) { 2719459Ssaidi@eecs.umich.edu return decodeShortFpTransfer(machInst); 2729459Ssaidi@eecs.umich.edu } else if (CPNUM == 0xe) { 2739459Ssaidi@eecs.umich.edu return decodeMcrMrc14(machInst); 2749459Ssaidi@eecs.umich.edu } else if (CPNUM == 0xf) { 2759459Ssaidi@eecs.umich.edu return decodeMcrMrc15(machInst); 2769459Ssaidi@eecs.umich.edu } 2779459Ssaidi@eecs.umich.edu const bool op = bits(machInst, 4); 2789459Ssaidi@eecs.umich.edu if (op) { 2799459Ssaidi@eecs.umich.edu if (bits(op1, 0)) { 2809459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2819459Ssaidi@eecs.umich.edu "mrc, mrc2", machInst); 2829459Ssaidi@eecs.umich.edu } else { 2839459Ssaidi@eecs.umich.edu return new WarnUnimplemented( 2849459Ssaidi@eecs.umich.edu "mcr, mcr2", machInst); 2859459Ssaidi@eecs.umich.edu } 2869459Ssaidi@eecs.umich.edu } else { 2879459Ssaidi@eecs.umich.edu return new WarnUnimplemented("cdp, cdp2", machInst); 2889459Ssaidi@eecs.umich.edu } 2899459Ssaidi@eecs.umich.edu } 2909459Ssaidi@eecs.umich.edu break; 2919459Ssaidi@eecs.umich.edu } 2929459Ssaidi@eecs.umich.edu } 2939459Ssaidi@eecs.umich.edu return new Unknown(machInst); 2949459Ssaidi@eecs.umich.edu } 2959459Ssaidi@eecs.umich.edu ''' % { 2969459Ssaidi@eecs.umich.edu "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1), 2979459Ssaidi@eecs.umich.edu "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1), 2989459Ssaidi@eecs.umich.edu "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 2999459Ssaidi@eecs.umich.edu "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 3009459Ssaidi@eecs.umich.edu "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 3019459Ssaidi@eecs.umich.edu "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 3029459Ssaidi@eecs.umich.edu "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 3039459Ssaidi@eecs.umich.edu "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1), 3049459Ssaidi@eecs.umich.edu "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 3059459Ssaidi@eecs.umich.edu "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1), 3069459Ssaidi@eecs.umich.edu "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 3079459Ssaidi@eecs.umich.edu "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1), 3089459Ssaidi@eecs.umich.edu "rfe" : "RFE_" + loadImmClassName(True, False, False, 8), 3099459Ssaidi@eecs.umich.edu "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8), 3109459Ssaidi@eecs.umich.edu "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 3119459Ssaidi@eecs.umich.edu "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8), 3129459Ssaidi@eecs.umich.edu "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8), 3139459Ssaidi@eecs.umich.edu "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8), 3149459Ssaidi@eecs.umich.edu "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8), 3159459Ssaidi@eecs.umich.edu "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8), 3169459Ssaidi@eecs.umich.edu "srs" : "SRS_" + storeImmClassName(True, False, False, 8), 3179459Ssaidi@eecs.umich.edu "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8), 3189459Ssaidi@eecs.umich.edu "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8), 3199459Ssaidi@eecs.umich.edu "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8), 3209459Ssaidi@eecs.umich.edu "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8), 3219459Ssaidi@eecs.umich.edu "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8), 3229459Ssaidi@eecs.umich.edu "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8), 3239459Ssaidi@eecs.umich.edu "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8) 3249459Ssaidi@eecs.umich.edu }; 3259459Ssaidi@eecs.umich.edu}}; 3269459Ssaidi@eecs.umich.edu