uncond.isa revision 7602
17860SN/A// Copyright (c) 2010 ARM Limited 27860SN/A// All rights reserved 37860SN/A// 48825Snilay@cs.wisc.edu// The license below extends only to copyright in the software and shall 57935SN/A// not be construed as granting a license to any other intellectual 67935SN/A// property including but not limited to intellectual property relating 77935SN/A// to a hardware implementation of the functionality of the software 87860SN/A// licensed hereunder. You may use the software subject to the license 97860SN/A// terms below provided that you ensure that this notice is replicated 107860SN/A// unmodified and in its entirety in all distributions of the software, 117860SN/A// modified or unmodified, in source code or in binary form. 128825Snilay@cs.wisc.edu// 139265SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without 148825Snilay@cs.wisc.edu// modification, are permitted provided that the following conditions are 158825Snilay@cs.wisc.edu// met: redistributions of source code must retain the above copyright 168825Snilay@cs.wisc.edu// notice, this list of conditions and the following disclaimer; 177860SN/A// redistributions in binary form must reproduce the above copyright 188464SN/A// notice, this list of conditions and the following disclaimer in the 198721SN/A// documentation and/or other materials provided with the distribution; 208825Snilay@cs.wisc.edu// neither the name of the copyright holders nor the names of its 218825Snilay@cs.wisc.edu// contributors may be used to endorse or promote products derived from 227935SN/A// this software without specific prior written permission. 237935SN/A// 247935SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257935SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267935SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277935SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287935SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 298893Ssaidi@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307860SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317860SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327860SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 338825Snilay@cs.wisc.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347860SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357860SN/A// 367860SN/A// Authors: Gabe Black 377860SN/A 388210SN/Adef format ArmUnconditional() {{ 398210SN/A decode_block = ''' 407860SN/A { 417860SN/A const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 427860SN/A const uint32_t op1 = bits(machInst, 27, 20); 437860SN/A if (bits(op1, 7) == 0) { 447860SN/A const uint32_t op2 = bits(machInst, 7, 4); 457860SN/A if (op1 == 0x10) { 467860SN/A if (bits((uint32_t)rn, 0) == 1 && op2 == 0) { 477860SN/A return new Setend(machInst, bits(machInst, 9)); 487860SN/A } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) { 497860SN/A const bool enable = bits(machInst, 19, 18) == 0x2; 507860SN/A const uint32_t mods = bits(machInst, 4, 0) | 517860SN/A (bits(machInst, 8, 6) << 5) | 527860SN/A (bits(machInst, 17) << 8) | 537860SN/A ((enable ? 1 : 0) << 9); 547860SN/A return new Cps(machInst, mods); 557860SN/A } 567860SN/A } else if (bits(op1, 6, 5) == 0x1) { 577860SN/A return decodeNeonData(machInst); 587860SN/A } else if (bits(op1, 6, 4) == 0x4) { 597860SN/A if (bits(op1, 0) == 0) { 607860SN/A return decodeNeonMem(machInst); 617860SN/A } else if (bits(op1, 2, 0) == 1) { 628825Snilay@cs.wisc.edu // Unallocated memory hint 637860SN/A return new NopInst(machInst); 647860SN/A } else if (bits(op1, 2, 0) == 5) { 657860SN/A const bool add = bits(machInst, 23); 667860SN/A const uint32_t imm12 = bits(machInst, 11, 0); 677860SN/A if (add) { 687860SN/A return new %(pli_iadd)s(machInst, INTREG_ZERO, 697860SN/A rn, add, imm12); 707860SN/A } else { 717860SN/A return new %(pli_isub)s(machInst, INTREG_ZERO, 727860SN/A rn, add, imm12); 737860SN/A } 747860SN/A } 757860SN/A } else if (bits(op1, 6, 4) == 0x5) { 767860SN/A if (bits(op1, 1, 0) == 0x1) { 777860SN/A const bool add = bits(machInst, 23); 787860SN/A const bool pldw = bits(machInst, 22); 797860SN/A const uint32_t imm12 = bits(machInst, 11, 0); 808825Snilay@cs.wisc.edu if (pldw) { 817860SN/A if (add) { 827860SN/A return new %(pldw_iadd)s(machInst, INTREG_ZERO, 837860SN/A rn, add, imm12); 847860SN/A } else { 857860SN/A return new %(pldw_isub)s(machInst, INTREG_ZERO, 867860SN/A rn, add, imm12); 877860SN/A } 887860SN/A } else { 897860SN/A if (add) { 907860SN/A return new %(pld_iadd)s(machInst, INTREG_ZERO, 917860SN/A rn, add, imm12); 928825Snilay@cs.wisc.edu } else { 937860SN/A return new %(pld_isub)s(machInst, INTREG_ZERO, 947860SN/A rn, add, imm12); 957860SN/A } 967860SN/A } 977860SN/A } else if (op1 == 0x57) { 987860SN/A switch (op2) { 997860SN/A case 0x1: 1008825Snilay@cs.wisc.edu return new WarnUnimplemented("clrex", machInst); 1017860SN/A case 0x4: 1027860SN/A return new WarnUnimplemented("dsb", machInst); 1037860SN/A case 0x5: 1047860SN/A return new WarnUnimplemented("dmb", machInst); 1057860SN/A case 0x6: 1067860SN/A return new WarnUnimplemented("isb", machInst); 1077860SN/A } 1087860SN/A } 1097860SN/A } else if (bits(op2, 0) == 0) { 1107860SN/A switch (op1 & 0xf7) { 1117860SN/A case 0x61: 1127860SN/A // Unallocated memory hint 1137860SN/A return new NopInst(machInst); 1147860SN/A case 0x65: 1157860SN/A { 1167860SN/A const uint32_t imm5 = bits(machInst, 11, 7); 1178521SN/A const uint32_t type = bits(machInst, 6, 5); 1187860SN/A const bool add = bits(machInst, 23); 1197860SN/A const IntRegIndex rm = 1207860SN/A (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1217860SN/A if (add) { 1227860SN/A return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 1237860SN/A add, imm5, type, rm); 1247860SN/A } else { 1257860SN/A return new %(pli_rsub)s(machInst, INTREG_ZERO, rn, 1267860SN/A add, imm5, type, rm); 1277860SN/A } 1287860SN/A } 1298893Ssaidi@eecs.umich.edu case 0x71: 1307860SN/A case 0x75: 1317860SN/A { 1329265SAli.Saidi@ARM.com const uint32_t imm5 = bits(machInst, 11, 7); 1337860SN/A const uint32_t type = bits(machInst, 6, 5); 1347860SN/A const bool add = bits(machInst, 23); 1359265SAli.Saidi@ARM.com const bool pldw = bits(machInst, 22); 1368150SN/A const IntRegIndex rm = 1377860SN/A (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1387860SN/A if (pldw) { 1397860SN/A if (add) { 1408835SAli.Saidi@ARM.com return new %(pldw_radd)s(machInst, INTREG_ZERO, 1417860SN/A rn, add, imm5, 1427860SN/A type, rm); 1439265SAli.Saidi@ARM.com } else { 1447860SN/A return new %(pldw_rsub)s(machInst, INTREG_ZERO, 1457860SN/A rn, add, imm5, 1468835SAli.Saidi@ARM.com type, rm); 1477860SN/A } 1487860SN/A } else { 1497860SN/A if (add) { 1507860SN/A return new %(pld_radd)s(machInst, INTREG_ZERO, 1517860SN/A rn, add, imm5, 1528893Ssaidi@eecs.umich.edu type, rm); 1537860SN/A } else { 1547860SN/A return new %(pld_rsub)s(machInst, INTREG_ZERO, 1557860SN/A rn, add, imm5, 1568825Snilay@cs.wisc.edu type, rm); 1577860SN/A } 1588825Snilay@cs.wisc.edu } 1598825Snilay@cs.wisc.edu } 1608825Snilay@cs.wisc.edu } 1618825Snilay@cs.wisc.edu } 1629265SAli.Saidi@ARM.com } else { 1639265SAli.Saidi@ARM.com switch (bits(machInst, 26, 25)) { 1648825Snilay@cs.wisc.edu case 0x0: 1658893Ssaidi@eecs.umich.edu { 1667860SN/A const uint32_t val = ((machInst >> 20) & 0x5); 1677860SN/A if (val == 0x4) { 1687860SN/A const uint32_t mode = bits(machInst, 4, 0); 1697860SN/A if (badMode((OperatingMode)mode)) 1707860SN/A return new Unknown(machInst); 1717860SN/A switch (bits(machInst, 24, 21)) { 1727860SN/A case 0x2: 1737860SN/A return new %(srs)s(machInst, mode, 1747860SN/A SrsOp::DecrementAfter, false); 1757860SN/A case 0x3: 1767860SN/A return new %(srs_w)s(machInst, mode, 1777860SN/A SrsOp::DecrementAfter, true); 1787860SN/A case 0x6: 1797860SN/A return new %(srs_u)s(machInst, mode, 1807860SN/A SrsOp::IncrementAfter, false); 1817860SN/A case 0x7: 1827860SN/A return new %(srs_uw)s(machInst, mode, 1837860SN/A SrsOp::IncrementAfter, true); 1847860SN/A case 0xa: 1857860SN/A return new %(srs_p)s(machInst, mode, 1867860SN/A SrsOp::DecrementBefore, false); 1877860SN/A case 0xb: 1887860SN/A return new %(srs_pw)s(machInst, mode, 1897860SN/A SrsOp::DecrementBefore, true); 1907860SN/A case 0xe: 1917860SN/A return new %(srs_pu)s(machInst, mode, 1927860SN/A SrsOp::IncrementBefore, false); 1937860SN/A case 0xf: 1947860SN/A return new %(srs_puw)s(machInst, mode, 1957860SN/A SrsOp::IncrementBefore, true); 1967860SN/A } 1977860SN/A return new Unknown(machInst); 1987860SN/A } else if (val == 0x1) { 1997860SN/A switch (bits(machInst, 24, 21)) { 2007860SN/A case 0x0: 2017860SN/A return new %(rfe)s(machInst, rn, 2027860SN/A RfeOp::DecrementAfter, false); 2037860SN/A case 0x1: 2047860SN/A return new %(rfe_w)s(machInst, rn, 2057860SN/A RfeOp::DecrementAfter, true); 2067860SN/A case 0x4: 2077860SN/A return new %(rfe_u)s(machInst, rn, 2087860SN/A RfeOp::IncrementAfter, false); 2097860SN/A case 0x5: 2107860SN/A return new %(rfe_uw)s(machInst, rn, 2117860SN/A RfeOp::IncrementAfter, true); 2127860SN/A case 0x8: 2137860SN/A return new %(rfe_p)s(machInst, rn, 2147860SN/A RfeOp::DecrementBefore, false); 2157860SN/A case 0x9: 2167860SN/A return new %(rfe_pw)s(machInst, rn, 2177860SN/A RfeOp::DecrementBefore, true); 2187860SN/A case 0xc: 2197860SN/A return new %(rfe_pu)s(machInst, rn, 2207860SN/A RfeOp::IncrementBefore, false); 2217860SN/A case 0xd: 2227860SN/A return new %(rfe_puw)s(machInst, rn, 2237860SN/A RfeOp::IncrementBefore, true); 2247860SN/A } 2257860SN/A return new Unknown(machInst); 2267860SN/A } 2277860SN/A } 2287860SN/A break; 2297860SN/A case 0x1: 2307860SN/A { 2317860SN/A const uint32_t imm = 2327860SN/A (sext<26>(bits(machInst, 23, 0) << 2)) | 2337860SN/A (bits(machInst, 24) << 1); 2347860SN/A return new BlxImm(machInst, imm, COND_UC); 2357860SN/A } 2367860SN/A case 0x2: 2377860SN/A if (bits(op1, 4, 0) != 0) { 2387860SN/A if (CPNUM == 0xa || CPNUM == 0xb) { 2397860SN/A return decodeExtensionRegLoadStore(machInst); 2407860SN/A } 2417860SN/A if (bits(op1, 0) == 1) { 2427860SN/A if (rn == INTREG_PC) { 2437860SN/A if (bits(op1, 4, 3) != 0x0) { 2447860SN/A return new WarnUnimplemented( 2457860SN/A "ldc, ldc2 (literal)", machInst); 2467860SN/A } 2477860SN/A } else { 2487860SN/A if (op1 == 0xC3 || op1 == 0xC7) { 2497860SN/A return new WarnUnimplemented( 2507860SN/A "ldc, ldc2 (immediate)", machInst); 2517860SN/A } 2527860SN/A } 2537860SN/A if (op1 == 0xC5) { 2547860SN/A return new WarnUnimplemented( 2557860SN/A "mrrc, mrrc2", machInst); 2567860SN/A } 2577860SN/A } else { 2587860SN/A if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) { 2597860SN/A return new WarnUnimplemented( 2607860SN/A "stc, stc2", machInst); 2617860SN/A } else if (op1 == 0xC4) { 2627860SN/A return new WarnUnimplemented( 2637860SN/A "mcrr, mcrrc", machInst); 2647860SN/A } 2657860SN/A } 2667860SN/A } 2677860SN/A break; 2687860SN/A case 0x3: 2697860SN/A if (bits(op1, 4) == 0) { 2707860SN/A if (CPNUM == 0xa || CPNUM == 0xb) { 2717860SN/A return decodeShortFpTransfer(machInst); 2727860SN/A } else if (CPNUM == 0xf) { 2737860SN/A return decodeMcrMrc15(machInst); 2747860SN/A } 2757860SN/A const bool op = bits(machInst, 4); 2767860SN/A if (op) { 2777860SN/A if (bits(op1, 0)) { 2787860SN/A return new WarnUnimplemented( 2797860SN/A "mrc, mrc2", machInst); 2807860SN/A } else { 2817860SN/A return new WarnUnimplemented( 2827860SN/A "mcr, mcr2", machInst); 2837860SN/A } 2847860SN/A } else { 2857860SN/A return new WarnUnimplemented("cdp, cdp2", machInst); 2867860SN/A } 2877860SN/A } 2887860SN/A break; 2897860SN/A } 2907860SN/A } 2917860SN/A return new Unknown(machInst); 2927860SN/A } 2937860SN/A ''' % { 2947860SN/A "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1), 2957860SN/A "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1), 2967860SN/A "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 2977860SN/A "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 2987860SN/A "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 2997860SN/A "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 3007860SN/A "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 3017860SN/A "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1), 3027860SN/A "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 3037860SN/A "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1), 3047860SN/A "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 3057860SN/A "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1), 3067860SN/A "rfe" : "RFE_" + loadImmClassName(True, False, False, 8), 3077860SN/A "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8), 3087860SN/A "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 3097860SN/A "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8), 3107860SN/A "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8), 3117860SN/A "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8), 3127860SN/A "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8), 3137860SN/A "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8), 3147860SN/A "srs" : "SRS_" + storeImmClassName(True, False, False, 8), 3157860SN/A "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8), 3167860SN/A "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8), 3177860SN/A "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8), 3187860SN/A "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8), 3197860SN/A "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8), 3207860SN/A "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8), 3217860SN/A "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8) 3227860SN/A }; 3237860SN/A}}; 3247860SN/A