uncond.isa revision 7314 
1// Copyright (c) 2010 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39    decode_block = '''
40    {
41        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42        const uint32_t op1 = bits(machInst, 27, 20);
43        if (bits(op1, 7) == 0) {
44            const uint32_t op2 = bits(machInst, 7, 4);
45            if (op1 == 0x10) {
46                if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47                    return new Setend(machInst, bits(machInst, 9));
48                } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49                    return new WarnUnimplemented("cps", machInst);
50                }
51            } else if (bits(op1, 6, 5) == 0x1) {
52                return new WarnUnimplemented(
53                        "Advanced SIMD data-processing", machInst);
54            } else if (bits(op1, 6, 4) == 0x4) {
55                if (bits(op1, 0) == 0) {
56                    return new WarnUnimplemented(
57                            "Advanced SIMD element or structure load/store",
58                            machInst);
59                } else if (bits(op1, 2, 0) == 1) {
60                    // Unallocated memory hint
61                    return new NopInst(machInst);
62                } else if (bits(op1, 2, 0) == 5) {
63                    const bool add = bits(machInst, 23);
64                    const uint32_t imm12 = bits(machInst, 11, 0);
65                    if (add) {
66                        return new %(pli_iadd)s(machInst, INTREG_ZERO,
67                                                rn, add, imm12);
68                    } else {
69                        return new %(pli_isub)s(machInst, INTREG_ZERO,
70                                                rn, add, imm12);
71                    }
72                }
73            } else if (bits(op1, 6, 4) == 0x5) {
74                if (bits(op1, 1, 0) == 0x1) {
75                    const bool add = bits(machInst, 23);
76                    const bool pldw = bits(machInst, 22);
77                    const uint32_t imm12 = bits(machInst, 11, 0);
78                    if (pldw) {
79                        if (add) {
80                            return new %(pldw_iadd)s(machInst, INTREG_ZERO,
81                                                     rn, add, imm12);
82                        } else {
83                            return new %(pldw_isub)s(machInst, INTREG_ZERO,
84                                                     rn, add, imm12);
85                        }
86                    } else {
87                        if (add) {
88                            return new %(pld_iadd)s(machInst, INTREG_ZERO,
89                                                    rn, add, imm12);
90                        } else {
91                            return new %(pld_isub)s(machInst, INTREG_ZERO,
92                                                    rn, add, imm12);
93                        }
94                    }
95                } else if (op1 == 0x57) {
96                    switch (op2) {
97                      case 0x1:
98                        return new WarnUnimplemented("clrex", machInst);
99                      case 0x4:
100                        return new WarnUnimplemented("dsb", machInst);
101                      case 0x5:
102                        return new WarnUnimplemented("dmb", machInst);
103                      case 0x6:
104                        return new WarnUnimplemented("isb", machInst);
105                    }
106                }
107            } else if (bits(op2, 0) == 0) {
108                switch (op1 & 0xf7) {
109                  case 0x61:
110                    // Unallocated memory hint
111                    return new NopInst(machInst);
112                  case 0x65:
113                    {
114                        const uint32_t imm5 = bits(machInst, 11, 7);
115                        const uint32_t type = bits(machInst, 6, 5);
116                        const bool add = bits(machInst, 23);
117                        const IntRegIndex rm =
118                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
119                        if (add) {
120                            return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
121                                                    add, imm5, type, rm);
122                        } else {
123                            return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
124                                                    add, imm5, type, rm);
125                        }
126                    }
127                  case 0x71:
128                  case 0x75:
129                    {
130                        const uint32_t imm5 = bits(machInst, 11, 7);
131                        const uint32_t type = bits(machInst, 6, 5);
132                        const bool add = bits(machInst, 23);
133                        const bool pldw = bits(machInst, 22);
134                        const IntRegIndex rm =
135                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
136                        if (pldw) {
137                            if (add) {
138                                return new %(pldw_radd)s(machInst, INTREG_ZERO,
139                                                         rn, add, imm5,
140                                                         type, rm);
141                            } else {
142                                return new %(pldw_rsub)s(machInst, INTREG_ZERO,
143                                                         rn, add, imm5,
144                                                         type, rm);
145                            }
146                        } else {
147                            if (add) {
148                                return new %(pld_radd)s(machInst, INTREG_ZERO,
149                                                        rn, add, imm5,
150                                                        type, rm);
151                            } else {
152                                return new %(pld_rsub)s(machInst, INTREG_ZERO,
153                                                        rn, add, imm5,
154                                                        type, rm);
155                            }
156                        }
157                    }
158                }
159            }
160        } else {
161            switch (bits(machInst, 26, 25)) {
162              case 0x0:
163                {
164                    const uint32_t val = ((machInst >> 20) & 0x5);
165                    if (val == 0x4) {
166                        const uint32_t mode = bits(machInst, 4, 0);
167                        switch (bits(machInst, 24, 21)) {
168                          case 0x2:
169                            return new %(srs)s(machInst, mode,
170                                    SrsOp::DecrementAfter, false);
171                          case 0x3:
172                            return new %(srs_w)s(machInst, mode,
173                                    SrsOp::DecrementAfter, true);
174                          case 0x6:
175                            return new %(srs_u)s(machInst, mode,
176                                    SrsOp::IncrementAfter, false);
177                          case 0x7:
178                            return new %(srs_uw)s(machInst, mode,
179                                    SrsOp::IncrementAfter, true);
180                          case 0xa:
181                            return new %(srs_p)s(machInst, mode,
182                                    SrsOp::DecrementBefore, false);
183                          case 0xb:
184                            return new %(srs_pw)s(machInst, mode,
185                                    SrsOp::DecrementBefore, true);
186                          case 0xe:
187                            return new %(srs_pu)s(machInst, mode,
188                                    SrsOp::IncrementBefore, false);
189                          case 0xf:
190                            return new %(srs_puw)s(machInst, mode,
191                                    SrsOp::IncrementBefore, true);
192                        }
193                        return new Unknown(machInst);
194                    } else if (val == 0x1) {
195                        switch (bits(machInst, 24, 21)) {
196                          case 0x0:
197                            return new %(rfe)s(machInst, rn,
198                                    RfeOp::DecrementAfter, false);
199                          case 0x1:
200                            return new %(rfe_w)s(machInst, rn,
201                                    RfeOp::DecrementAfter, true);
202                          case 0x4:
203                            return new %(rfe_u)s(machInst, rn,
204                                    RfeOp::IncrementAfter, false);
205                          case 0x5:
206                            return new %(rfe_uw)s(machInst, rn,
207                                    RfeOp::IncrementAfter, true);
208                          case 0x8:
209                            return new %(rfe_p)s(machInst, rn,
210                                    RfeOp::DecrementBefore, false);
211                          case 0x9:
212                            return new %(rfe_pw)s(machInst, rn,
213                                    RfeOp::DecrementBefore, true);
214                          case 0xc:
215                            return new %(rfe_pu)s(machInst, rn,
216                                    RfeOp::IncrementBefore, false);
217                          case 0xd:
218                            return new %(rfe_puw)s(machInst, rn,
219                                    RfeOp::IncrementBefore, true);
220                        }
221                        return new Unknown(machInst);
222                    }
223                }
224                break;
225              case 0x1:
226                {
227                    const uint32_t imm =
228                        (sext<26>(bits(machInst, 23, 0) << 2)) |
229                        (bits(machInst, 24) << 1);
230                    return new BlxImm(machInst, imm);
231                }
232              case 0x2:
233                if (bits(op1, 0) == 1) {
234                    if (rn == INTREG_PC) {
235                        if (bits(op1, 4, 3) != 0x0) {
236                            return new WarnUnimplemented(
237                                    "ldc, ldc2 (literal)", machInst);
238                        }
239                    } else {
240                        if (op1 == 0xC3 || op1 == 0xC7) {
241                            return new WarnUnimplemented(
242                                    "ldc, ldc2 (immediate)", machInst);
243                        }
244                    }
245                    if (op1 == 0xC5) {
246                        return new WarnUnimplemented("mrrc, mrrc2", machInst);
247                    }
248                } else {
249                    if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
250                        return new WarnUnimplemented("stc, stc2", machInst);
251                    } else if (op1 == 0xC4) {
252                        return new WarnUnimplemented("mcrr, mcrrc", machInst);
253                    }
254                }
255                break;
256              case 0x3:
257                {
258                    const bool op = bits(machInst, 4);
259                    if (op) {
260                        if (bits(op1, 0)) {
261                            return new WarnUnimplemented(
262                                    "mrc, mrc2", machInst);
263                        } else {
264                            return new WarnUnimplemented(
265                                    "mcr, mcr2", machInst);
266                        }
267                    } else {
268                        return new WarnUnimplemented("cdp, cdp2", machInst);
269                    }
270                }
271                break;
272            }
273        }
274        return new Unknown(machInst);
275    }
276    ''' % {
277        "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
278        "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
279        "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
280        "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
281        "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
282        "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
283        "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
284        "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
285        "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
286        "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
287        "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
288        "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
289        "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
290        "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
291        "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
292        "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
293        "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
294        "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
295        "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
296        "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
297        "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
298        "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
299        "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
300        "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
301        "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
302        "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
303        "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
304        "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
305    };
306}};
307