uncond.isa revision 7293
17191Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited
27191Sgblack@eecs.umich.edu// All rights reserved
37191Sgblack@eecs.umich.edu//
47191Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall
57191Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual
67191Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating
77191Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software
87191Sgblack@eecs.umich.edu// licensed hereunder.  You may use the software subject to the license
97191Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated
107191Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software,
117191Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form.
127191Sgblack@eecs.umich.edu//
137191Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without
147191Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are
157191Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright
167191Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer;
177191Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright
187191Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the
197191Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution;
207191Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its
217191Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from
227191Sgblack@eecs.umich.edu// this software without specific prior written permission.
237191Sgblack@eecs.umich.edu//
247191Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
257191Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
267191Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
277191Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
287191Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
297191Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
307191Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
317191Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
327191Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
337191Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
347191Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
357191Sgblack@eecs.umich.edu//
367191Sgblack@eecs.umich.edu// Authors: Gabe Black
377191Sgblack@eecs.umich.edu
387191Sgblack@eecs.umich.edudef format ArmUnconditional() {{
397191Sgblack@eecs.umich.edu    decode_block = '''
407191Sgblack@eecs.umich.edu    {
417191Sgblack@eecs.umich.edu        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
427191Sgblack@eecs.umich.edu        const uint32_t op1 = bits(machInst, 27, 20);
437191Sgblack@eecs.umich.edu        if (bits(op1, 7) == 0) {
447191Sgblack@eecs.umich.edu            const uint32_t op2 = bits(machInst, 7, 4);
457191Sgblack@eecs.umich.edu            if (op1 == 0x10) {
467191Sgblack@eecs.umich.edu                if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
477191Sgblack@eecs.umich.edu                    return new WarnUnimplemented("setend", machInst);
487191Sgblack@eecs.umich.edu                } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
497191Sgblack@eecs.umich.edu                    return new WarnUnimplemented("cps", machInst);
507191Sgblack@eecs.umich.edu                }
517191Sgblack@eecs.umich.edu            } else if (bits(op1, 6, 5) == 0x1) {
527191Sgblack@eecs.umich.edu                return new WarnUnimplemented(
537191Sgblack@eecs.umich.edu                        "Advanced SIMD data-processing", machInst);
547191Sgblack@eecs.umich.edu            } else if (bits(op1, 6, 4) == 0x4) {
557191Sgblack@eecs.umich.edu                if (bits(op1, 0) == 0) {
567191Sgblack@eecs.umich.edu                    return new WarnUnimplemented(
577191Sgblack@eecs.umich.edu                            "Advanced SIMD element or structure load/store",
587191Sgblack@eecs.umich.edu                            machInst);
597191Sgblack@eecs.umich.edu                } else if (bits(op1, 2, 0) == 1) {
607191Sgblack@eecs.umich.edu                    // Unallocated memory hint
617248Sgblack@eecs.umich.edu                    return new NopInst(machInst);
627191Sgblack@eecs.umich.edu                } else if (bits(op1, 2, 0) == 5) {
637192Sgblack@eecs.umich.edu                    const bool add = bits(machInst, 23);
647192Sgblack@eecs.umich.edu                    const uint32_t imm12 = bits(machInst, 11, 0);
657192Sgblack@eecs.umich.edu                    if (add) {
667192Sgblack@eecs.umich.edu                        return new %(pli_iadd)s(machInst, INTREG_ZERO,
677192Sgblack@eecs.umich.edu                                                rn, add, imm12);
687192Sgblack@eecs.umich.edu                    } else {
697192Sgblack@eecs.umich.edu                        return new %(pli_isub)s(machInst, INTREG_ZERO,
707192Sgblack@eecs.umich.edu                                                rn, add, imm12);
717192Sgblack@eecs.umich.edu                    }
727191Sgblack@eecs.umich.edu                }
737191Sgblack@eecs.umich.edu            } else if (bits(op1, 6, 4) == 0x5) {
747191Sgblack@eecs.umich.edu                if (bits(op1, 1, 0) == 0x1) {
757192Sgblack@eecs.umich.edu                    const bool add = bits(machInst, 23);
767192Sgblack@eecs.umich.edu                    const bool pldw = bits(machInst, 22);
777192Sgblack@eecs.umich.edu                    const uint32_t imm12 = bits(machInst, 11, 0);
787192Sgblack@eecs.umich.edu                    if (pldw) {
797192Sgblack@eecs.umich.edu                        if (add) {
807192Sgblack@eecs.umich.edu                            return new %(pldw_iadd)s(machInst, INTREG_ZERO,
817192Sgblack@eecs.umich.edu                                                     rn, add, imm12);
827192Sgblack@eecs.umich.edu                        } else {
837192Sgblack@eecs.umich.edu                            return new %(pldw_isub)s(machInst, INTREG_ZERO,
847192Sgblack@eecs.umich.edu                                                     rn, add, imm12);
857192Sgblack@eecs.umich.edu                        }
867192Sgblack@eecs.umich.edu                    } else {
877192Sgblack@eecs.umich.edu                        if (add) {
887192Sgblack@eecs.umich.edu                            return new %(pld_iadd)s(machInst, INTREG_ZERO,
897192Sgblack@eecs.umich.edu                                                    rn, add, imm12);
907192Sgblack@eecs.umich.edu                        } else {
917192Sgblack@eecs.umich.edu                            return new %(pld_isub)s(machInst, INTREG_ZERO,
927192Sgblack@eecs.umich.edu                                                    rn, add, imm12);
937192Sgblack@eecs.umich.edu                        }
947192Sgblack@eecs.umich.edu                    }
957191Sgblack@eecs.umich.edu                } else if (op1 == 0x57) {
967191Sgblack@eecs.umich.edu                    switch (op2) {
977191Sgblack@eecs.umich.edu                      case 0x1:
987191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("clrex", machInst);
997191Sgblack@eecs.umich.edu                      case 0x4:
1007191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("dsb", machInst);
1017191Sgblack@eecs.umich.edu                      case 0x5:
1027191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("dmb", machInst);
1037191Sgblack@eecs.umich.edu                      case 0x6:
1047191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("isb", machInst);
1057191Sgblack@eecs.umich.edu                    }
1067191Sgblack@eecs.umich.edu                }
1077191Sgblack@eecs.umich.edu            } else if (bits(op2, 0) == 0) {
1087191Sgblack@eecs.umich.edu                switch (op1 & 0xf7) {
1097191Sgblack@eecs.umich.edu                  case 0x61:
1107191Sgblack@eecs.umich.edu                    // Unallocated memory hint
1117248Sgblack@eecs.umich.edu                    return new NopInst(machInst);
1127191Sgblack@eecs.umich.edu                  case 0x65:
1137192Sgblack@eecs.umich.edu                    {
1147192Sgblack@eecs.umich.edu                        const uint32_t imm5 = bits(machInst, 11, 7);
1157192Sgblack@eecs.umich.edu                        const uint32_t type = bits(machInst, 6, 5);
1167192Sgblack@eecs.umich.edu                        const bool add = bits(machInst, 23);
1177192Sgblack@eecs.umich.edu                        const IntRegIndex rm =
1187192Sgblack@eecs.umich.edu                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
1197192Sgblack@eecs.umich.edu                        if (add) {
1207192Sgblack@eecs.umich.edu                            return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
1217192Sgblack@eecs.umich.edu                                                    add, imm5, type, rm);
1227192Sgblack@eecs.umich.edu                        } else {
1237192Sgblack@eecs.umich.edu                            return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
1247192Sgblack@eecs.umich.edu                                                    add, imm5, type, rm);
1257192Sgblack@eecs.umich.edu                        }
1267192Sgblack@eecs.umich.edu                    }
1277191Sgblack@eecs.umich.edu                  case 0x71:
1287192Sgblack@eecs.umich.edu                  case 0x75:
1297192Sgblack@eecs.umich.edu                    {
1307192Sgblack@eecs.umich.edu                        const uint32_t imm5 = bits(machInst, 11, 7);
1317192Sgblack@eecs.umich.edu                        const uint32_t type = bits(machInst, 6, 5);
1327192Sgblack@eecs.umich.edu                        const bool add = bits(machInst, 23);
1337192Sgblack@eecs.umich.edu                        const bool pldw = bits(machInst, 22);
1347192Sgblack@eecs.umich.edu                        const IntRegIndex rm =
1357192Sgblack@eecs.umich.edu                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
1367192Sgblack@eecs.umich.edu                        if (pldw) {
1377192Sgblack@eecs.umich.edu                            if (add) {
1387192Sgblack@eecs.umich.edu                                return new %(pldw_radd)s(machInst, INTREG_ZERO,
1397192Sgblack@eecs.umich.edu                                                         rn, add, imm5,
1407192Sgblack@eecs.umich.edu                                                         type, rm);
1417192Sgblack@eecs.umich.edu                            } else {
1427192Sgblack@eecs.umich.edu                                return new %(pldw_rsub)s(machInst, INTREG_ZERO,
1437192Sgblack@eecs.umich.edu                                                         rn, add, imm5,
1447192Sgblack@eecs.umich.edu                                                         type, rm);
1457192Sgblack@eecs.umich.edu                            }
1467192Sgblack@eecs.umich.edu                        } else {
1477192Sgblack@eecs.umich.edu                            if (add) {
1487192Sgblack@eecs.umich.edu                                return new %(pld_radd)s(machInst, INTREG_ZERO,
1497192Sgblack@eecs.umich.edu                                                        rn, add, imm5,
1507192Sgblack@eecs.umich.edu                                                        type, rm);
1517192Sgblack@eecs.umich.edu                            } else {
1527192Sgblack@eecs.umich.edu                                return new %(pld_rsub)s(machInst, INTREG_ZERO,
1537192Sgblack@eecs.umich.edu                                                        rn, add, imm5,
1547192Sgblack@eecs.umich.edu                                                        type, rm);
1557192Sgblack@eecs.umich.edu                            }
1567192Sgblack@eecs.umich.edu                        }
1577192Sgblack@eecs.umich.edu                    }
1587191Sgblack@eecs.umich.edu                }
1597191Sgblack@eecs.umich.edu            }
1607191Sgblack@eecs.umich.edu        } else {
1617191Sgblack@eecs.umich.edu            switch (bits(machInst, 26, 25)) {
1627191Sgblack@eecs.umich.edu              case 0x0:
1637191Sgblack@eecs.umich.edu                {
1647191Sgblack@eecs.umich.edu                    const uint32_t val = ((machInst >> 20) & 0x5);
1657191Sgblack@eecs.umich.edu                    if (val == 0x4) {
1667191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("srs", machInst);
1677191Sgblack@eecs.umich.edu                    } else if (val == 0x1) {
1687293Sgblack@eecs.umich.edu                        switch (bits(machInst, 24, 21)) {
1697293Sgblack@eecs.umich.edu                          case 0x0:
1707293Sgblack@eecs.umich.edu                            return new %(rfe)s(machInst, rn,
1717293Sgblack@eecs.umich.edu                                    RfeOp::DecrementAfter, false);
1727293Sgblack@eecs.umich.edu                          case 0x1:
1737293Sgblack@eecs.umich.edu                            return new %(rfe_w)s(machInst, rn,
1747293Sgblack@eecs.umich.edu                                    RfeOp::DecrementAfter, true);
1757293Sgblack@eecs.umich.edu                          case 0x4:
1767293Sgblack@eecs.umich.edu                            return new %(rfe_u)s(machInst, rn,
1777293Sgblack@eecs.umich.edu                                    RfeOp::IncrementAfter, false);
1787293Sgblack@eecs.umich.edu                          case 0x5:
1797293Sgblack@eecs.umich.edu                            return new %(rfe_uw)s(machInst, rn,
1807293Sgblack@eecs.umich.edu                                    RfeOp::IncrementAfter, true);
1817293Sgblack@eecs.umich.edu                          case 0x8:
1827293Sgblack@eecs.umich.edu                            return new %(rfe_p)s(machInst, rn,
1837293Sgblack@eecs.umich.edu                                    RfeOp::DecrementBefore, false);
1847293Sgblack@eecs.umich.edu                          case 0x9:
1857293Sgblack@eecs.umich.edu                            return new %(rfe_pw)s(machInst, rn,
1867293Sgblack@eecs.umich.edu                                    RfeOp::DecrementBefore, true);
1877293Sgblack@eecs.umich.edu                          case 0xc:
1887293Sgblack@eecs.umich.edu                            return new %(rfe_pu)s(machInst, rn,
1897293Sgblack@eecs.umich.edu                                    RfeOp::IncrementBefore, false);
1907293Sgblack@eecs.umich.edu                          case 0xd:
1917293Sgblack@eecs.umich.edu                            return new %(rfe_puw)s(machInst, rn,
1927293Sgblack@eecs.umich.edu                                    RfeOp::IncrementBefore, true);
1937293Sgblack@eecs.umich.edu                        }
1947293Sgblack@eecs.umich.edu                        return new Unknown(machInst);
1957191Sgblack@eecs.umich.edu                    }
1967191Sgblack@eecs.umich.edu                }
1977191Sgblack@eecs.umich.edu                break;
1987191Sgblack@eecs.umich.edu              case 0x1:
1997191Sgblack@eecs.umich.edu                {
2007191Sgblack@eecs.umich.edu                    const uint32_t imm =
2017191Sgblack@eecs.umich.edu                        (sext<26>(bits(machInst, 23, 0) << 2)) |
2027191Sgblack@eecs.umich.edu                        (bits(machInst, 24) << 1);
2037191Sgblack@eecs.umich.edu                    return new BlxImm(machInst, imm);
2047191Sgblack@eecs.umich.edu                }
2057191Sgblack@eecs.umich.edu              case 0x2:
2067191Sgblack@eecs.umich.edu                if (bits(op1, 0) == 1) {
2077191Sgblack@eecs.umich.edu                    if (rn == INTREG_PC) {
2087191Sgblack@eecs.umich.edu                        if (bits(op1, 4, 3) != 0x0) {
2097191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2107191Sgblack@eecs.umich.edu                                    "ldc, ldc2 (literal)", machInst);
2117191Sgblack@eecs.umich.edu                        }
2127191Sgblack@eecs.umich.edu                    } else {
2137191Sgblack@eecs.umich.edu                        if (op1 == 0xC3 || op1 == 0xC7) {
2147191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2157191Sgblack@eecs.umich.edu                                    "ldc, ldc2 (immediate)", machInst);
2167191Sgblack@eecs.umich.edu                        }
2177191Sgblack@eecs.umich.edu                    }
2187191Sgblack@eecs.umich.edu                    if (op1 == 0xC5) {
2197191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("mrrc, mrrc2", machInst);
2207191Sgblack@eecs.umich.edu                    }
2217191Sgblack@eecs.umich.edu                } else {
2227191Sgblack@eecs.umich.edu                    if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
2237191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("stc, stc2", machInst);
2247191Sgblack@eecs.umich.edu                    } else if (op1 == 0xC4) {
2257191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("mcrr, mcrrc", machInst);
2267191Sgblack@eecs.umich.edu                    }
2277191Sgblack@eecs.umich.edu                }
2287191Sgblack@eecs.umich.edu                break;
2297191Sgblack@eecs.umich.edu              case 0x3:
2307191Sgblack@eecs.umich.edu                {
2317191Sgblack@eecs.umich.edu                    const bool op = bits(machInst, 4);
2327191Sgblack@eecs.umich.edu                    if (op) {
2337191Sgblack@eecs.umich.edu                        if (bits(op1, 0)) {
2347191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2357191Sgblack@eecs.umich.edu                                    "mrc, mrc2", machInst);
2367191Sgblack@eecs.umich.edu                        } else {
2377191Sgblack@eecs.umich.edu                            return new WarnUnimplemented(
2387191Sgblack@eecs.umich.edu                                    "mcr, mcr2", machInst);
2397191Sgblack@eecs.umich.edu                        }
2407191Sgblack@eecs.umich.edu                    } else {
2417191Sgblack@eecs.umich.edu                        return new WarnUnimplemented("cdp, cdp2", machInst);
2427191Sgblack@eecs.umich.edu                    }
2437191Sgblack@eecs.umich.edu                }
2447191Sgblack@eecs.umich.edu                break;
2457191Sgblack@eecs.umich.edu            }
2467191Sgblack@eecs.umich.edu        }
2477191Sgblack@eecs.umich.edu        return new Unknown(machInst);
2487191Sgblack@eecs.umich.edu    }
2497192Sgblack@eecs.umich.edu    ''' % {
2507192Sgblack@eecs.umich.edu        "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
2517192Sgblack@eecs.umich.edu        "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
2527192Sgblack@eecs.umich.edu        "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
2537192Sgblack@eecs.umich.edu        "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
2547192Sgblack@eecs.umich.edu        "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
2557192Sgblack@eecs.umich.edu        "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
2567192Sgblack@eecs.umich.edu        "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
2577192Sgblack@eecs.umich.edu        "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
2587192Sgblack@eecs.umich.edu        "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
2597192Sgblack@eecs.umich.edu        "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
2607192Sgblack@eecs.umich.edu        "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
2617293Sgblack@eecs.umich.edu        "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
2627293Sgblack@eecs.umich.edu        "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
2637293Sgblack@eecs.umich.edu        "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
2647293Sgblack@eecs.umich.edu        "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
2657293Sgblack@eecs.umich.edu        "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
2667293Sgblack@eecs.umich.edu        "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
2677293Sgblack@eecs.umich.edu        "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
2687293Sgblack@eecs.umich.edu        "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
2697293Sgblack@eecs.umich.edu        "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8)
2707192Sgblack@eecs.umich.edu    };
2717191Sgblack@eecs.umich.edu}};
272