uncond.isa revision 12788 
1// Copyright (c) 2010-2012 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38def format ArmUnconditional() {{
39    decode_block = '''
40    {
41        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42        const uint32_t op1 = bits(machInst, 27, 20);
43        if (bits(op1, 7) == 0) {
44            const uint32_t op2 = bits(machInst, 7, 4);
45            if (op1 == 0x10) {
46                if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47                    return new Setend(machInst, bits(machInst, 9));
48                } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49                    const bool enable = bits(machInst, 19, 18) == 0x2;
50                    const uint32_t mods = bits(machInst, 4, 0) |
51                                          (bits(machInst, 8, 6) << 5) |
52                                          (bits(machInst, 17) << 8) |
53                                          ((enable ? 1 : 0) << 9);
54                    return new Cps(machInst, mods);
55                }
56            } else if (bits(op1, 6, 5) == 0x1) {
57                return decodeNeonData(machInst);
58            } else if (bits(op1, 6, 4) == 0x4) {
59                if (bits(op1, 0) == 0) {
60                    return decodeNeonMem(machInst);
61                } else if (bits(op1, 2, 0) == 1) {
62                    // Unallocated memory hint
63                    return new NopInst(machInst);
64                } else if (bits(op1, 2, 0) == 5) {
65                    const bool add = bits(machInst, 23);
66                    const uint32_t imm12 = bits(machInst, 11, 0);
67                    if (add) {
68                        return new %(pli_iadd)s(machInst, INTREG_ZERO,
69                                                rn, add, imm12);
70                    } else {
71                        return new %(pli_isub)s(machInst, INTREG_ZERO,
72                                                rn, add, imm12);
73                    }
74                }
75            } else if (bits(op1, 6, 4) == 0x5) {
76                if (bits(op1, 1, 0) == 0x1) {
77                    const bool add = bits(machInst, 23);
78                    const bool pldw = bits(machInst, 22);
79                    const uint32_t imm12 = bits(machInst, 11, 0);
80                    if (pldw) {
81                        if (add) {
82                            return new %(pldw_iadd)s(machInst, INTREG_ZERO,
83                                                     rn, add, imm12);
84                        } else {
85                            return new %(pldw_isub)s(machInst, INTREG_ZERO,
86                                                     rn, add, imm12);
87                        }
88                    } else {
89                        if (add) {
90                            return new %(pld_iadd)s(machInst, INTREG_ZERO,
91                                                    rn, add, imm12);
92                        } else {
93                            return new %(pld_isub)s(machInst, INTREG_ZERO,
94                                                    rn, add, imm12);
95                        }
96                    }
97                } else if (op1 == 0x57) {
98                    switch (op2) {
99                      case 0x1:
100                        return new Clrex(machInst);
101                      case 0x4:
102                        return new Dsb(machInst, 0);
103                      case 0x5:
104                        return new Dmb(machInst, 0);
105                      case 0x6:
106                        return new Isb(machInst, 0);
107                    }
108                }
109            } else if (bits(op2, 0) == 0) {
110                switch (op1 & 0xf7) {
111                  case 0x61:
112                    // Unallocated memory hint
113                    return new NopInst(machInst);
114                  case 0x65:
115                    {
116                        const uint32_t imm5 = bits(machInst, 11, 7);
117                        const uint32_t type = bits(machInst, 6, 5);
118                        const bool add = bits(machInst, 23);
119                        const IntRegIndex rm =
120                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
121                        if (add) {
122                            return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
123                                                    add, imm5, type, rm);
124                        } else {
125                            return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
126                                                    add, imm5, type, rm);
127                        }
128                    }
129                  case 0x71:
130                  case 0x75:
131                    {
132                        const uint32_t imm5 = bits(machInst, 11, 7);
133                        const uint32_t type = bits(machInst, 6, 5);
134                        const bool add = bits(machInst, 23);
135                        const bool pldw = bits(machInst, 22);
136                        const IntRegIndex rm =
137                            (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
138                        if (pldw) {
139                            if (add) {
140                                return new %(pldw_radd)s(machInst, INTREG_ZERO,
141                                                         rn, add, imm5,
142                                                         type, rm);
143                            } else {
144                                return new %(pldw_rsub)s(machInst, INTREG_ZERO,
145                                                         rn, add, imm5,
146                                                         type, rm);
147                            }
148                        } else {
149                            if (add) {
150                                return new %(pld_radd)s(machInst, INTREG_ZERO,
151                                                        rn, add, imm5,
152                                                        type, rm);
153                            } else {
154                                return new %(pld_rsub)s(machInst, INTREG_ZERO,
155                                                        rn, add, imm5,
156                                                        type, rm);
157                            }
158                        }
159                    }
160                }
161            }
162        } else {
163            switch (bits(machInst, 26, 25)) {
164              case 0x0:
165                {
166                    const uint32_t val = ((machInst >> 20) & 0x5);
167                    if (val == 0x4) {
168                        const uint32_t mode = bits(machInst, 4, 0);
169                        // We check at decode stage if the mode exists even
170                        // if the checking is re-done by Srs::execute.
171                        // This is done because we will otherwise panic if
172                        // trying to read the banked stack pointer of an
173                        // unrecognized mode.
174                        if (unknownMode32((OperatingMode)mode))
175                            return new Unknown(machInst);
176                        switch (bits(machInst, 24, 21)) {
177                          case 0x2:
178                            return new %(srs)s(machInst, mode,
179                                    SrsOp::DecrementAfter, false);
180                          case 0x3:
181                            return new %(srs_w)s(machInst, mode,
182                                    SrsOp::DecrementAfter, true);
183                          case 0x6:
184                            return new %(srs_u)s(machInst, mode,
185                                    SrsOp::IncrementAfter, false);
186                          case 0x7:
187                            return new %(srs_uw)s(machInst, mode,
188                                    SrsOp::IncrementAfter, true);
189                          case 0xa:
190                            return new %(srs_p)s(machInst, mode,
191                                    SrsOp::DecrementBefore, false);
192                          case 0xb:
193                            return new %(srs_pw)s(machInst, mode,
194                                    SrsOp::DecrementBefore, true);
195                          case 0xe:
196                            return new %(srs_pu)s(machInst, mode,
197                                    SrsOp::IncrementBefore, false);
198                          case 0xf:
199                            return new %(srs_puw)s(machInst, mode,
200                                    SrsOp::IncrementBefore, true);
201                        }
202                        return new Unknown(machInst);
203                    } else if (val == 0x1) {
204                        switch (bits(machInst, 24, 21)) {
205                          case 0x0:
206                            return new %(rfe)s(machInst, rn,
207                                    RfeOp::DecrementAfter, false);
208                          case 0x1:
209                            return new %(rfe_w)s(machInst, rn,
210                                    RfeOp::DecrementAfter, true);
211                          case 0x4:
212                            return new %(rfe_u)s(machInst, rn,
213                                    RfeOp::IncrementAfter, false);
214                          case 0x5:
215                            return new %(rfe_uw)s(machInst, rn,
216                                    RfeOp::IncrementAfter, true);
217                          case 0x8:
218                            return new %(rfe_p)s(machInst, rn,
219                                    RfeOp::DecrementBefore, false);
220                          case 0x9:
221                            return new %(rfe_pw)s(machInst, rn,
222                                    RfeOp::DecrementBefore, true);
223                          case 0xc:
224                            return new %(rfe_pu)s(machInst, rn,
225                                    RfeOp::IncrementBefore, false);
226                          case 0xd:
227                            return new %(rfe_puw)s(machInst, rn,
228                                    RfeOp::IncrementBefore, true);
229                        }
230                        return new Unknown(machInst);
231                    }
232                }
233                break;
234              case 0x1:
235                {
236                    const uint32_t imm =
237                        (sext<26>(bits(machInst, 23, 0) << 2)) |
238                        (bits(machInst, 24) << 1);
239                    return new BlxImm(machInst, imm, COND_UC);
240                }
241              case 0x2:
242                if (bits(op1, 4, 0) != 0) {
243                    if (CPNUM == 0xa || CPNUM == 0xb) {
244                        return decodeExtensionRegLoadStore(machInst);
245                    }
246                    if (bits(op1, 0) == 1) {
247                        if (rn == INTREG_PC) {
248                            if (bits(op1, 4, 3) != 0x0) {
249                                return new WarnUnimplemented(
250                                        "ldc, ldc2 (literal)", machInst);
251                            }
252                        } else {
253                            if (op1 == 0xC3 || op1 == 0xC7) {
254                                return new WarnUnimplemented(
255                                        "ldc, ldc2 (immediate)", machInst);
256                            }
257                        }
258                    } else {
259                        if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
260                            return new WarnUnimplemented(
261                                    "stc, stc2", machInst);
262                        }
263                    }
264                }
265                break;
266              case 0x3:
267                if (bits(op1, 4) == 0) {
268                    if (CPNUM == 0xa || CPNUM == 0xb) {
269                        return decodeShortFpTransfer(machInst);
270                    } else if (CPNUM == 0xe) {
271                        return decodeMcrMrc14(machInst);
272                    } else if (CPNUM == 0xf) {
273                        return decodeMcrMrc15(machInst);
274                    }
275                    const bool op = bits(machInst, 4);
276                    if (op) {
277                        if (bits(op1, 0)) {
278                            return new WarnUnimplemented(
279                                    "mrc, mrc2", machInst);
280                        } else {
281                            return new WarnUnimplemented(
282                                    "mcr, mcr2", machInst);
283                        }
284                    } else {
285                        return new WarnUnimplemented("cdp, cdp2", machInst);
286                    }
287                }
288                break;
289            }
290        }
291        return new Unknown(machInst);
292    }
293    ''' % {
294        "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
295        "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
296        "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
297        "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
298        "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
299        "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
300        "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
301        "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
302        "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
303        "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
304        "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
305        "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
306        "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
307        "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
308        "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
309        "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
310        "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
311        "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
312        "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
313        "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
314        "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
315        "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
316        "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
317        "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
318        "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
319        "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
320        "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
321        "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)
322    };
323}};
324