misc.isa revision 10506:aa23216161fa
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2013 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39// Giacomo Gabrielli 40 41def format ArmERet() {{ 42 decode_block = "return new Eret(machInst);" 43}}; 44 45def format Svc() {{ 46 decode_block = "return new Svc(machInst, bits(machInst, 23, 0));" 47}}; 48 49def format ArmSmcHyp() {{ 50 decode_block = ''' 51 { 52 if (bits(machInst, 21)) 53 { 54 return new Smc(machInst); 55 } else { 56 uint32_t imm16 = (bits(machInst, 19, 8) << 4) | 57 (bits(machInst, 3, 0) << 0); 58 return new Hvc(machInst, imm16); 59 } 60 } 61 ''' 62}}; 63 64def format ArmMsrMrs() {{ 65 decode_block = ''' 66 { 67 const uint8_t byteMask = bits(machInst, 19, 16); 68 const uint8_t sysM = byteMask | (bits(machInst, 8) << 4); 69 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 70 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 71 const uint32_t opcode = bits(machInst, 24, 21); 72 const bool useImm = bits(machInst, 25); 73 const bool r = bits(machInst, 22); 74 const bool isBanked = bits(machInst, 9); 75 76 const uint32_t unrotated = bits(machInst, 7, 0); 77 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 78 const uint32_t imm = rotate_imm(unrotated, rotation); 79 80 switch (opcode) { 81 case 0x8: 82 if (isBanked) { 83 return new MrsBankedReg(machInst, rd, sysM, r!=0); 84 } else { 85 return new MrsCpsr(machInst, rd); 86 } 87 case 0x9: 88 if (useImm) { 89 return new MsrCpsrImm(machInst, imm, byteMask); 90 } else { 91 if (isBanked) { 92 return new MsrBankedReg(machInst, rn, sysM, r!=0); 93 } else { 94 return new MsrCpsrReg(machInst, rn, byteMask); 95 } 96 } 97 case 0xa: 98 if (isBanked) { 99 return new MrsBankedReg(machInst, rd, sysM, r!=0); 100 } else { 101 return new MrsSpsr(machInst, rd); 102 } 103 case 0xb: 104 if (useImm) { 105 return new MsrSpsrImm(machInst, imm, byteMask); 106 } else { 107 if (isBanked) { 108 return new MsrBankedReg(machInst, rn, sysM, r!=0); 109 } else { 110 return new MsrSpsrReg(machInst, rn, byteMask); 111 } 112 } 113 default: 114 return new Unknown(machInst); 115 } 116 } 117 ''' 118}}; 119 120let {{ 121 header_output = ''' 122 StaticInstPtr 123 decodeMcrMrc14(ExtMachInst machInst); 124 ''' 125 decoder_output = ''' 126 StaticInstPtr 127 decodeMcrMrc14(ExtMachInst machInst) 128 { 129 const uint32_t opc1 = bits(machInst, 23, 21); 130 const uint32_t crn = bits(machInst, 19, 16); 131 const uint32_t opc2 = bits(machInst, 7, 5); 132 const uint32_t crm = bits(machInst, 3, 0); 133 const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2); 134 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 135 136 const bool isRead = bits(machInst, 20); 137 138 switch (miscReg) { 139 case MISCREG_NOP: 140 return new NopInst(machInst); 141 case MISCREG_CP14_UNIMPL: 142 return new FailUnimplemented(isRead ? "mrc unknown" : "mcr unknown", 143 machInst, 144 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", 145 crn, opc1, crm, opc2, isRead ? "read" : "write")); 146 default: 147 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2); 148 if (isRead) { 149 return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss); 150 } else { 151 return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss); 152 } 153 } 154 } 155 ''' 156}}; 157 158def format McrMrc14() {{ 159 decode_block = ''' 160 return decodeMcrMrc14(machInst); 161 ''' 162}}; 163 164let {{ 165 header_output = ''' 166 StaticInstPtr decodeMcrMrc14(ExtMachInst machInst); 167 StaticInstPtr decodeMcrMrc15(ExtMachInst machInst); 168 ''' 169 decoder_output = ''' 170 StaticInstPtr 171 decodeMcrMrc15(ExtMachInst machInst) 172 { 173 const uint32_t opc1 = bits(machInst, 23, 21); 174 const uint32_t crn = bits(machInst, 19, 16); 175 const uint32_t opc2 = bits(machInst, 7, 5); 176 const uint32_t crm = bits(machInst, 3, 0); 177 const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2); 178 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 179 const bool isRead = bits(machInst, 20); 180 uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2); 181 182 switch (miscReg) { 183 case MISCREG_NOP: 184 return new NopInst(machInst); 185 case MISCREG_CP15_UNIMPL: 186 return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown", 187 machInst, 188 csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", 189 crn, opc1, crm, opc2, isRead ? "read" : "write")); 190 case MISCREG_DCCMVAC: 191 return new FlushPipeInst( 192 isRead ? "mrc dccmvac" : "mcr dccmvac", machInst); 193 case MISCREG_CP15ISB: 194 return new Isb(machInst, iss); 195 case MISCREG_CP15DSB: 196 return new Dsb(machInst, iss); 197 case MISCREG_CP15DMB: 198 return new Dmb(machInst, iss); 199 default: 200 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 201 std::string full_mnem = csprintf("%s %s", 202 isRead ? "mrc" : "mcr", miscRegName[miscReg]); 203 warn("\\tinstruction '%s' unimplemented\\n", full_mnem); 204 205 // Remove the warn flag and set the implemented flag. This 206 // prevents the instruction warning a second time, it also 207 // means the instruction is actually generated. Actually 208 // creating the instruction to access an register that isn't 209 // implemented sounds a bit silly, but its required to get 210 // the correct behaviour for hyp traps and undef exceptions. 211 miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true; 212 miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false; 213 } 214 215 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 216 if (isRead) 217 return new Mrc15(machInst, rt, miscReg, iss); 218 return new Mcr15(machInst, miscReg, rt, iss); 219 } else { 220 return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst, 221 csprintf("%s %s", isRead ? "mrc" : "mcr", 222 miscRegName[miscReg])); 223 } 224 } 225 } 226 ''' 227}}; 228 229def format McrMrc15() {{ 230 decode_block = ''' 231 return decodeMcrMrc15(machInst); 232 ''' 233}}; 234 235let {{ 236 header_output = ''' 237 StaticInstPtr 238 decodeMcrrMrrc15(ExtMachInst machInst); 239 ''' 240 decoder_output = ''' 241 StaticInstPtr 242 decodeMcrrMrrc15(ExtMachInst machInst) 243 { 244 const uint32_t crm = bits(machInst, 3, 0); 245 const uint32_t opc1 = bits(machInst, 7, 4); 246 const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1); 247 const IntRegIndex rt = (IntRegIndex) (uint32_t) bits(machInst, 15, 12); 248 const IntRegIndex rt2 = (IntRegIndex) (uint32_t) bits(machInst, 19, 16); 249 250 const bool isRead = bits(machInst, 20); 251 252 switch (miscReg) { 253 case MISCREG_CP15_UNIMPL: 254 return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst, 255 csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown", 256 crm, opc1, isRead ? "read" : "write")); 257 default: 258 if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 259 std::string full_mnem = csprintf("%s %s", 260 isRead ? "mrrc" : "mcrr", miscRegName[miscReg]); 261 warn("\\tinstruction '%s' unimplemented\\n", full_mnem); 262 263 // Remove the warn flag and set the implemented flag. This 264 // prevents the instruction warning a second time, it also 265 // means the instruction is actually generated. Actually 266 // creating the instruction to access an register that isn't 267 // implemented sounds a bit silly, but its required to get 268 // the correct behaviour for hyp traps and undef exceptions. 269 miscRegInfo[miscReg][MISCREG_IMPLEMENTED] = true; 270 miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL] = false; 271 } 272 273 if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 274 uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1); 275 276 if (isRead) { 277 StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss); 278 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 279 si->setFlag(StaticInst::IsUnverifiable); 280 return si; 281 } 282 return new Mcrr15(machInst, rt2, rt, miscReg, iss); 283 } else { 284 return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst, 285 csprintf("%s %s", 286 isRead ? "mrrc" : "mcrr", miscRegName[miscReg])); 287 } 288 } 289 } 290 ''' 291}}; 292 293def format Mcrr15() {{ 294 decode_block = ''' 295 return decodeMcrrMrrc15(machInst); 296 ''' 297}}; 298 299def format Mrrc15() {{ 300 decode_block = ''' 301 return decodeMcrrMrrc15(machInst); 302 ''' 303}}; 304