mem.isa revision 7417:a573ee3adc96
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Gabe Black 42 43def format AddrMode2(imm) {{ 44 if eval(imm): 45 imm = True 46 else: 47 imm = False 48 49 def buildPUBWLCase(p, u, b, w, l): 50 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) 51 52 header_output = decoder_output = exec_output = "" 53 decode_block = "switch(PUBWL) {\n" 54 55 # Loop over all the values of p, u, b, w and l and build instructions and 56 # a decode block for them. 57 for p in (0, 1): 58 for u in (0, 1): 59 for b in (0, 1): 60 for w in (0, 1): 61 post = (p == 0) 62 user = (p == 0 and w == 1) 63 writeback = (p == 0 or w == 1) 64 add = (u == 1) 65 if b == 0: 66 size = 4 67 else: 68 size = 1 69 if add: 70 addStr = "true" 71 else: 72 addStr = "false" 73 if imm: 74 newDecode = "return new %s(machInst, RD, RN," + \ 75 "%s, machInst.immed11_0);" 76 loadClass = loadImmClassName(post, add, writeback, 77 size, False, user) 78 storeClass = storeImmClassName(post, add, writeback, 79 size, False, user) 80 loadDecode = newDecode % (loadClass, addStr) 81 storeDecode = newDecode % (storeClass, addStr) 82 else: 83 newDecode = "return new %s(machInst, RD, RN, %s," + \ 84 "machInst.shiftSize," + \ 85 "machInst.shift, RM);" 86 loadClass = loadRegClassName(post, add, writeback, 87 size, False, user) 88 storeClass = storeRegClassName(post, add, writeback, 89 size, False, user) 90 loadDecode = newDecode % (loadClass, addStr) 91 storeDecode = newDecode % (storeClass, addStr) 92 decode = ''' 93 case %#x: 94 {%s} 95 break; 96 ''' 97 decode_block += decode % \ 98 (buildPUBWLCase(p,u,b,w,1), loadDecode) 99 decode_block += decode % \ 100 (buildPUBWLCase(p,u,b,w,0), storeDecode) 101 decode_block += ''' 102 default: 103 return new Unknown(machInst); 104 break; 105 }''' 106}}; 107 108def format AddrMode3() {{ 109 decode = ''' 110 { 111 const uint32_t op1 = bits(machInst, 24, 20); 112 const uint32_t op2 = bits(machInst, 6, 5); 113 const uint32_t puiw = bits(machInst, 24, 21); 114 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0; 115 switch (op2) { 116 case 0x1: 117 if (op1 & 0x1) { 118 %(ldrh)s 119 } else { 120 %(strh)s 121 } 122 case 0x2: 123 if (op1 & 0x1) { 124 %(ldrsb)s 125 } else if ((RT %% 2) == 0) { 126 %(ldrd)s 127 } else { 128 return new Unknown(machInst); 129 } 130 case 0x3: 131 if (op1 & 0x1) { 132 %(ldrsh)s 133 } else { 134 %(strd)s 135 } 136 default: 137 return new Unknown(machInst); 138 } 139 } 140 ''' 141 142 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False): 143 post = (p == 0) 144 user = (p == 0 and w == 1) 145 writeback = (p == 0 or w == 1) 146 add = (u == 1) 147 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0) 148 decode = ''' 149 case %#x: 150 return new '''% caseVal 151 if add: 152 addStr = "true" 153 else: 154 addStr = "false" 155 if d: 156 dests = "RT & ~1, RT | 1" 157 else: 158 dests = "RT" 159 if i: 160 if load: 161 if d: 162 className = loadDoubleImmClassName(post, add, writeback) 163 else: 164 className = loadImmClassName(post, add, writeback, \ 165 size=size, sign=sign, \ 166 user=user) 167 else: 168 if d: 169 className = storeDoubleImmClassName(post, add, writeback) 170 else: 171 className = storeImmClassName(post, add, writeback, \ 172 size=size, sign=sign, \ 173 user=user) 174 decode += ("%s(machInst, %s, RN, %s, imm);\n" % \ 175 (className, dests, addStr)) 176 else: 177 if load: 178 if d: 179 className = loadDoubleRegClassName(post, add, writeback) 180 else: 181 className = loadRegClassName(post, add, writeback, \ 182 size=size, sign=sign, \ 183 user=user) 184 else: 185 if d: 186 className = storeDoubleRegClassName(post, add, writeback) 187 else: 188 className = storeRegClassName(post, add, writeback, \ 189 size=size, sign=sign, \ 190 user=user) 191 decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \ 192 (className, dests, addStr)) 193 return decode 194 195 def decodePuiw(load, d, size=4, sign=False): 196 global decodePuiwCase 197 decode = "switch (puiw) {\n" 198 for p in (0, 1): 199 for u in (0, 1): 200 for i in (0, 1): 201 for w in (0, 1): 202 decode += decodePuiwCase(load, d, p, u, i, w, 203 size, sign) 204 decode += ''' 205 default: 206 return new Unknown(machInst); 207 } 208 ''' 209 return decode 210 211 subs = { 212 "ldrh" : decodePuiw(True, False, size=2), 213 "strh" : decodePuiw(False, False, size=2), 214 "ldrsb" : decodePuiw(True, False, size=1, sign=True), 215 "ldrd" : decodePuiw(True, True), 216 "ldrsh" : decodePuiw(True, False, size=2, sign=True), 217 "strd" : decodePuiw(False, True) 218 } 219 decode_block = decode % subs 220}}; 221 222def format ArmSyncMem() {{ 223 decode_block = ''' 224 { 225 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 226 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 227 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 228 switch (PUBWL) { 229 case 0x10: 230 return new Swp(machInst, rt, rt2, rn); 231 case 0x14: 232 return new Swpb(machInst, rt, rt2, rn); 233 case 0x18: 234 return new %(strex)s(machInst, rt, rt2, rn, true, 0); 235 case 0x19: 236 return new %(ldrex)s(machInst, rt, rn, true, 0); 237 case 0x1a: 238 return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); 239 case 0x1b: 240 return new %(ldrexd)s(machInst, rt, rt + 1, rn, true, 0); 241 case 0x1c: 242 return new %(strexb)s(machInst, rt, rt2, rn, true, 0); 243 case 0x1d: 244 return new %(ldrexb)s(machInst, rt, rn, true, 0); 245 case 0x1e: 246 return new %(strexh)s(machInst, rt, rt2, rn, true, 0); 247 case 0x1f: 248 return new %(ldrexh)s(machInst, rt, rn, true, 0); 249 default: 250 return new Unknown(machInst); 251 } 252 } 253 ''' % { 254 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 255 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 256 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 257 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 258 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 259 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 260 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), 261 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False) 262 } 263}}; 264 265def format Thumb32SrsRfe() {{ 266 decode_block = ''' 267 { 268 const bool wb = (bits(machInst, 21) == 1); 269 const bool add = (bits(machInst, 24, 23) == 0x3); 270 if (bits(machInst, 20) == 1) { 271 // post == add 272 const IntRegIndex rn = 273 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 274 if (!add && !wb) { 275 return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb); 276 } else if (add && !wb) { 277 return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb); 278 } else if (!add && wb) { 279 return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb); 280 } else { 281 return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb); 282 } 283 } else { 284 const uint32_t mode = bits(machInst, 4, 0); 285 if (!add && !wb) { 286 return new %(srs)s(machInst, mode, 287 SrsOp::DecrementBefore, wb); 288 } else if (add && !wb) { 289 return new %(srs_u)s(machInst, mode, 290 SrsOp::IncrementAfter, wb); 291 } else if (!add && wb) { 292 return new %(srs_w)s(machInst, mode, 293 SrsOp::DecrementBefore, wb); 294 } else { 295 return new %(srs_uw)s(machInst, mode, 296 SrsOp::IncrementAfter, wb); 297 } 298 } 299 } 300 ''' % { 301 "rfe" : "RFE_" + loadImmClassName(False, False, False, 8), 302 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 303 "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8), 304 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8), 305 "srs" : "SRS_" + storeImmClassName(False, False, False, 8), 306 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8), 307 "srs_w" : "SRS_" + storeImmClassName(False, False, True, 8), 308 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8) 309 } 310}}; 311 312def format Thumb32LdrStrDExTbh() {{ 313 decode_block = ''' 314 { 315 const uint32_t op1 = bits(machInst, 24, 23); 316 const uint32_t op2 = bits(machInst, 21, 20); 317 const uint32_t op3 = bits(machInst, 7, 4); 318 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 319 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 320 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 321 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 322 const uint32_t imm8 = bits(machInst, 7, 0); 323 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) { 324 if (op1 == 0) { 325 const uint32_t imm = bits(machInst, 7, 0) << 2; 326 if (op2 == 0) { 327 return new %(strex)s(machInst, rt2, rt, rn, true, imm); 328 } else { 329 return new %(ldrex)s(machInst, rt, rn, true, imm); 330 } 331 } else { 332 if (op2 == 0) { 333 switch (op3) { 334 case 0x4: 335 return new %(strexb)s(machInst, rd, rt, rn, true, 0); 336 case 0x5: 337 return new %(strexh)s(machInst, rd, rt, rn, true, 0); 338 case 0x7: 339 return new %(strexd)s(machInst, rd, rt, 340 rt2, rn, true, 0); 341 default: 342 return new Unknown(machInst); 343 } 344 } else { 345 switch (op3) { 346 case 0x0: 347 return new Tbb(machInst, rn, rd); 348 case 0x1: 349 return new Tbh(machInst, rn, rd); 350 case 0x4: 351 return new %(ldrexb)s(machInst, rt, rn, true, 0); 352 case 0x5: 353 return new %(ldrexh)s(machInst, rt, rn, true, 0); 354 case 0x7: 355 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0); 356 default: 357 return new Unknown(machInst); 358 } 359 } 360 } 361 } else { 362 const uint32_t puw = (bits(machInst, 24, 23) << 1) | 363 bits(machInst, 21); 364 const uint32_t dimm = imm8 << 2; 365 if (bits(op2, 0) == 0) { 366 switch (puw) { 367 case 0x1: 368 return new %(strd_w)s(machInst, rt, rt2, rn, false, dimm); 369 case 0x3: 370 return new %(strd_uw)s(machInst, rt, rt2, rn, true, dimm); 371 case 0x4: 372 return new %(strd_p)s(machInst, rt, rt2, rn, false, dimm); 373 case 0x5: 374 return new %(strd_pw)s(machInst, rt, rt2, rn, false, dimm); 375 case 0x6: 376 return new %(strd_pu)s(machInst, rt, rt2, rn, true, dimm); 377 case 0x7: 378 return new %(strd_puw)s(machInst, rt, rt2, rn, true, dimm); 379 default: 380 return new Unknown(machInst); 381 } 382 } else { 383 switch (puw) { 384 case 0x1: 385 return new %(ldrd_w)s(machInst, rt, rt2, rn, false, dimm); 386 case 0x3: 387 return new %(ldrd_uw)s(machInst, rt, rt2, rn, true, dimm); 388 case 0x4: 389 return new %(ldrd_p)s(machInst, rt, rt2, rn, false, dimm); 390 case 0x5: 391 return new %(ldrd_pw)s(machInst, rt, rt2, rn, false, dimm); 392 case 0x6: 393 return new %(ldrd_pu)s(machInst, rt, rt2, rn, true, dimm); 394 case 0x7: 395 return new %(ldrd_puw)s(machInst, rt, rt2, rn, true, dimm); 396 default: 397 return new Unknown(machInst); 398 } 399 } 400 } 401 } 402 ''' % { 403 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 404 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 405 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 406 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 407 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 408 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 409 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), 410 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False), 411 "ldrd_w" : loadDoubleImmClassName(True, False, True), 412 "ldrd_uw" : loadDoubleImmClassName(True, True, True), 413 "ldrd_p" : loadDoubleImmClassName(False, False, False), 414 "ldrd_pw" : loadDoubleImmClassName(False, False, True), 415 "ldrd_pu" : loadDoubleImmClassName(False, True, False), 416 "ldrd_puw" : loadDoubleImmClassName(False, True, True), 417 "strd_w" : storeDoubleImmClassName(True, False, True), 418 "strd_uw" : storeDoubleImmClassName(True, True, True), 419 "strd_p" : storeDoubleImmClassName(False, False, False), 420 "strd_pw" : storeDoubleImmClassName(False, False, True), 421 "strd_pu" : storeDoubleImmClassName(False, True, False), 422 "strd_puw" : storeDoubleImmClassName(False, True, True) 423 } 424}}; 425 426def format Thumb32LoadWord() {{ 427 decode = ''' 428 { 429 uint32_t op1 = bits(machInst, 24, 23); 430 if (bits(op1, 1) == 0) { 431 uint32_t op2 = bits(machInst, 11, 6); 432 if (HTRN == 0xF) { 433 if (UP) { 434 return new %(literal_u)s(machInst, RT, INTREG_PC, 435 true, IMMED_11_0); 436 } else { 437 return new %(literal)s(machInst, RT, INTREG_PC, 438 false, IMMED_11_0); 439 } 440 } else if (op1 == 0x1) { 441 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0); 442 } else if (op2 == 0) { 443 return new %(register)s(machInst, RT, RN, UP, 444 bits(machInst, 5, 4), LSL, RM); 445 } else if ((op2 & 0x3c) == 0x38) { 446 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0); 447 } else if ((op2 & 0x3c) == 0x30 || //P 448 (op2 & 0x24) == 0x24) { //W 449 uint32_t puw = bits(machInst, 10, 8); 450 uint32_t imm = IMMED_7_0; 451 switch (puw) { 452 case 0: 453 case 2: 454 // If we're here, either P or W must have been set. 455 panic("Neither P or W set, but that " 456 "shouldn't be possible.\\n"); 457 case 1: 458 return new %(imm_w)s(machInst, RT, RN, false, imm); 459 case 3: 460 return new %(imm_uw)s(machInst, RT, RN, true, imm); 461 case 4: 462 return new %(imm_p)s(machInst, RT, RN, false, imm); 463 case 5: 464 return new %(imm_pw)s(machInst, RT, RN, false, imm); 465 case 6: 466 return new %(imm_pu)s(machInst, RT, RN, true, imm); 467 case 7: 468 return new %(imm_puw)s(machInst, RT, RN, true, imm); 469 } 470 } 471 } else { 472 return new Unknown(machInst); 473 } 474 } 475 ''' 476 classNames = { 477 "literal_u" : loadImmClassName(False, True, False), 478 "literal" : loadImmClassName(False, False, False), 479 "register" : loadRegClassName(False, True, False), 480 "ldrt" : loadImmClassName(False, True, False, user=True), 481 "imm_w" : loadImmClassName(True, False, True), 482 "imm_uw" : loadImmClassName(True, True, True), 483 "imm_p" : loadImmClassName(False, False, False), 484 "imm_pw" : loadImmClassName(False, False, True), 485 "imm_pu" : loadImmClassName(False, True, False), 486 "imm_puw" : loadImmClassName(False, True, True) 487 } 488 decode_block = decode % classNames 489}}; 490 491def format Thumb32StoreSingle() {{ 492 def buildPuwDecode(size): 493 puwDecode = ''' 494 { 495 uint32_t puw = bits(machInst, 10, 8); 496 uint32_t imm = IMMED_7_0; 497 switch (puw) { 498 case 0: 499 case 2: 500 // If we're here, either P or W must have been set. 501 panic("Neither P or W set, but that " 502 "shouldn't be possible.\\n"); 503 case 1: 504 return new %(imm_w)s(machInst, RT, RN, false, imm); 505 case 3: 506 return new %(imm_uw)s(machInst, RT, RN, true, imm); 507 case 4: 508 return new %(imm_p)s(machInst, RT, RN, false, imm); 509 case 5: 510 return new %(imm_pw)s(machInst, RT, RN, false, imm); 511 case 6: 512 return new %(imm_pu)s(machInst, RT, RN, true, imm); 513 case 7: 514 return new %(imm_puw)s(machInst, RT, RN, true, imm); 515 } 516 } 517 ''' 518 return puwDecode % { 519 "imm_w" : storeImmClassName(True, False, True, size=size), 520 "imm_uw" : storeImmClassName(True, True, True, size=size), 521 "imm_p" : storeImmClassName(False, False, False, size=size), 522 "imm_pw" : storeImmClassName(False, False, True, size=size), 523 "imm_pu" : storeImmClassName(False, True, False, size=size), 524 "imm_puw" : storeImmClassName(False, True, True, size=size) 525 } 526 decode = ''' 527 { 528 uint32_t op1 = bits(machInst, 23, 21); 529 uint32_t op2 = bits(machInst, 11, 6); 530 bool op2Puw = ((op2 & 0x24) == 0x24 || 531 (op2 & 0x3c) == 0x30); 532 if (RN == 0xf) { 533 return new Unknown(machInst); 534 } 535 if (op1 == 4) { 536 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); 537 } else if (op1 == 0 && op2Puw) { 538 %(strb_puw)s; 539 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) { 540 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0); 541 } else if (op1 == 0 && op2 == 0) { 542 return new %(strb_reg)s(machInst, RT, RN, true, 543 bits(machInst, 5, 4), LSL, RM); 544 } else if (op1 == 5) { 545 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0); 546 } else if (op1 == 1 && op2Puw) { 547 %(strh_puw)s; 548 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) { 549 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0); 550 } else if (op1 == 1 && op2 == 0) { 551 return new %(strh_reg)s(machInst, RT, RN, true, 552 bits(machInst, 5, 4), LSL, RM); 553 } else if (op1 == 6) { 554 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0); 555 } else if (op1 == 2 && op2Puw) { 556 %(str_puw)s; 557 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) { 558 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0); 559 } else if (op1 == 2 && op2 == 0) { 560 return new %(str_reg)s(machInst, RT, RN, true, 561 bits(machInst, 5, 4), LSL, RM); 562 } else { 563 return new Unknown(machInst); 564 } 565 } 566 ''' 567 classNames = { 568 "strb_imm" : storeImmClassName(False, True, False, size=1), 569 "strb_puw" : buildPuwDecode(1), 570 "strbt" : storeImmClassName(False, True, False, user=True, size=1), 571 "strb_reg" : storeRegClassName(False, True, False, size=1), 572 "strh_imm" : storeImmClassName(False, True, False, size=2), 573 "strh_puw" : buildPuwDecode(2), 574 "strht" : storeImmClassName(False, True, False, user=True, size=2), 575 "strh_reg" : storeRegClassName(False, True, False, size=2), 576 "str_imm" : storeImmClassName(False, True, False), 577 "str_puw" : buildPuwDecode(4), 578 "strt" : storeImmClassName(False, True, False, user=True), 579 "str_reg" : storeRegClassName(False, True, False) 580 } 581 decode_block = decode % classNames 582}}; 583 584def format LoadByteMemoryHints() {{ 585 decode = ''' 586 { 587 const uint32_t op1 = bits(machInst, 24, 23); 588 const uint32_t op2 = bits(machInst, 11, 6); 589 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 590 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 591 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 592 const uint32_t imm12 = bits(machInst, 11, 0); 593 const uint32_t imm8 = bits(machInst, 7, 0); 594 bool pldw = bits(machInst, 21); 595 const uint32_t imm2 = bits(machInst, 5, 4); 596 if (rn == 0xf) { 597 if (rt == 0xf) { 598 const bool add = bits(machInst, 23); 599 if (bits(op1, 1) == 1) { 600 if (add) { 601 return new %(pli_iulit)s(machInst, INTREG_ZERO, 602 INTREG_PC, true, imm12); 603 } else { 604 return new %(pli_ilit)s(machInst, INTREG_ZERO, 605 INTREG_PC, false, imm12); 606 } 607 } else { 608 if (add) { 609 return new %(pld_iulit)s(machInst, INTREG_ZERO, 610 INTREG_PC, true, imm12); 611 } else { 612 return new %(pld_ilit)s(machInst, INTREG_ZERO, 613 INTREG_PC, false, imm12); 614 } 615 } 616 } else { 617 if (bits(op1, 1) == 1) { 618 if (bits(machInst, 23)) { 619 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC, 620 true, imm12); 621 } else { 622 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC, 623 false, imm12); 624 } 625 } else { 626 if (bits(machInst, 23)) { 627 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC, 628 true, imm12); 629 } else { 630 return new %(ldrb_lit)s(machInst, rt, INTREG_PC, 631 false, imm12); 632 } 633 } 634 } 635 } else if (rt == 0xf) { 636 switch (op1) { 637 case 0x0: 638 if (op2 == 0x0) { 639 if (pldw) { 640 return new %(pldw_radd)s(machInst, INTREG_ZERO, 641 rn, true, imm2, LSL, rm); 642 } else { 643 return new %(pld_radd)s(machInst, INTREG_ZERO, 644 rn, true, imm2, LSL, rm); 645 } 646 } else if (bits(op2, 5, 2) == 0xc) { 647 if (pldw) { 648 return new %(pldw_isub)s(machInst, INTREG_ZERO, 649 rn, false, imm8); 650 } else { 651 return new %(pld_isub)s(machInst, INTREG_ZERO, 652 rn, false, imm8); 653 } 654 } 655 break; 656 case 0x1: 657 if (pldw) { 658 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 659 rn, true, imm12); 660 } else { 661 return new %(pld_iadd)s(machInst, INTREG_ZERO, 662 rn, true, imm12); 663 } 664 case 0x2: 665 if (op2 == 0x0) { 666 return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 667 true, imm2, LSL, rm); 668 } else if (bits(op2, 5, 2) == 0xc) { 669 return new %(pli_ilit)s(machInst, INTREG_ZERO, 670 INTREG_PC, false, imm8); 671 } 672 break; 673 case 0x3: 674 return new %(pli_iulit)s(machInst, INTREG_ZERO, 675 INTREG_PC, true, imm12); 676 } 677 return new Unknown(machInst); 678 } else { 679 switch (op1) { 680 case 0x0: 681 if (op2 == 0) { 682 return new %(ldrb_radd)s(machInst, rt, rn, true, 683 imm2, LSL, rm); 684 } else if (bits(op2, 5, 2) == 0xe) { 685 return new %(ldrbt)s(machInst, rt, rn, true, imm8); 686 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 687 const uint32_t puw = bits(machInst, 10, 8); 688 switch (puw) { 689 case 0x1: 690 return new %(ldrb_iw)s(machInst, rt, 691 rn, false, imm8); 692 case 0x3: 693 return new %(ldrb_iuw)s(machInst, rt, 694 rn, true, imm8); 695 case 0x4: 696 return new %(ldrb_ip)s(machInst, rt, 697 rn, false, imm8); 698 case 0x5: 699 return new %(ldrb_ipw)s(machInst, rt, 700 rn, false, imm8); 701 case 0x7: 702 return new %(ldrb_ipuw)s(machInst, rt, 703 rn, true, imm8); 704 } 705 } 706 break; 707 case 0x1: 708 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12); 709 case 0x2: 710 if (op2 == 0) { 711 return new %(ldrsb_radd)s(machInst, rt, rn, true, 712 imm2, LSL, rm); 713 } else if (bits(op2, 5, 2) == 0xe) { 714 return new %(ldrsbt)s(machInst, rt, rn, true, imm8); 715 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 716 const uint32_t puw = bits(machInst, 10, 8); 717 switch (puw) { 718 case 0x1: 719 return new %(ldrsb_iw)s(machInst, rt, 720 rn, false, imm8); 721 case 0x3: 722 return new %(ldrsb_iuw)s(machInst, rt, 723 rn, true, imm8); 724 case 0x4: 725 return new %(ldrsb_ip)s(machInst, rt, 726 rn, false, imm8); 727 case 0x5: 728 return new %(ldrsb_ipw)s(machInst, rt, 729 rn, false, imm8); 730 case 0x7: 731 return new %(ldrsb_ipuw)s(machInst, rt, 732 rn, true, imm8); 733 } 734 } 735 break; 736 case 0x3: 737 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12); 738 } 739 return new Unknown(machInst); 740 } 741 } 742 ''' 743 substDict = { 744 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True), 745 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True), 746 "ldrb_lit_u" : loadImmClassName(False, True, False, 1), 747 "ldrb_lit" : loadImmClassName(False, False, False, 1), 748 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True), 749 "ldrb_radd" : loadRegClassName(False, True, False, 1), 750 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True), 751 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True), 752 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True), 753 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True), 754 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True), 755 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True), 756 "ldrb_iw" : loadImmClassName(True, False, True, 1), 757 "ldrb_iuw" : loadImmClassName(True, True, True, 1), 758 "ldrb_ip" : loadImmClassName(False, False, False, 1), 759 "ldrb_ipw" : loadImmClassName(False, False, True, 1), 760 "ldrb_ipuw" : loadImmClassName(False, True, True, 1), 761 "ldrb_iadd" : loadImmClassName(False, True, False, 1), 762 "ldrbt" : loadImmClassName(False, True, False, 1, user=True), 763 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True), 764 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 765 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 766 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 767 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 768 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 769 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 770 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1), 771 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1), 772 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 773 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1), 774 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 775 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 776 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1) 777 } 778 decode_block = decode % substDict 779}}; 780 781def format LoadHalfwordMemoryHints() {{ 782 decode = ''' 783 { 784 const uint32_t op1 = bits(machInst, 24, 23); 785 const uint32_t op2 = bits(machInst, 11, 6); 786 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 787 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 788 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 789 const uint32_t imm12 = bits(machInst, 11, 0); 790 const uint32_t imm8 = bits(machInst, 7, 0); 791 bool pldw = bits(machInst, 21); 792 const uint32_t imm2 = bits(machInst, 5, 4); 793 if (rn == 0xf) { 794 if (rt == 0xf) { 795 if (bits(op1, 1) == 1) { 796 // Unallocated memory hint 797 return new NopInst(machInst); 798 } else { 799 return new Unknown(machInst); 800 } 801 } else { 802 if (bits(op1, 1) == 1) { 803 if (bits(machInst, 23)) { 804 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC, 805 true, imm12); 806 } else { 807 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC, 808 false, imm12); 809 } 810 } else { 811 if (bits(machInst, 23)) { 812 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC, 813 true, imm12); 814 } else { 815 return new %(ldrh_lit)s(machInst, rt, INTREG_PC, 816 false, imm12); 817 } 818 } 819 } 820 } else if (rt == 0xf) { 821 switch (op1) { 822 case 0x0: 823 if (op2 == 0x0) { 824 if (pldw) { 825 return new %(pldw_radd)s(machInst, INTREG_ZERO, 826 rn, true, imm2, LSL, rm); 827 } else { 828 return new %(pld_radd)s(machInst, INTREG_ZERO, 829 rn, true, imm2, LSL, rm); 830 } 831 } else if (bits(op2, 5, 2) == 0xc) { 832 if (pldw) { 833 return new %(pldw_isub)s(machInst, INTREG_ZERO, 834 rn, false, imm8); 835 } else { 836 return new %(pld_isub)s(machInst, INTREG_ZERO, 837 rn, false, imm8); 838 } 839 } 840 break; 841 case 0x1: 842 if (pldw) { 843 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 844 rn, true, imm12); 845 } else { 846 return new %(pld_iadd)s(machInst, INTREG_ZERO, 847 rn, true, imm12); 848 } 849 case 0x2: 850 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) { 851 // Unallocated memory hint 852 return new NopInst(machInst); 853 } 854 break; 855 case 0x3: 856 return new NopInst(machInst); 857 } 858 return new Unknown(machInst); 859 } else { 860 switch (op1) { 861 case 0x0: 862 if (op2 == 0) { 863 return new %(ldrh_radd)s(machInst, rt, rn, true, 864 imm2, LSL, rm); 865 } else if (bits(op2, 5, 2) == 0xe) { 866 return new %(ldrht)s(machInst, rt, rn, true, imm8); 867 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 868 const uint32_t puw = bits(machInst, 10, 8); 869 switch (puw) { 870 case 0x1: 871 return new %(ldrh_iw)s(machInst, rt, 872 rn, false, imm8); 873 case 0x3: 874 return new %(ldrh_iuw)s(machInst, rt, 875 rn, true, imm8); 876 case 0x4: 877 return new %(ldrh_ip)s(machInst, rt, 878 rn, false, imm8); 879 case 0x5: 880 return new %(ldrh_ipw)s(machInst, rt, 881 rn, false, imm8); 882 case 0x7: 883 return new %(ldrh_ipuw)s(machInst, rt, 884 rn, true, imm8); 885 } 886 } 887 break; 888 case 0x1: 889 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12); 890 case 0x2: 891 if (op2 == 0) { 892 return new %(ldrsh_radd)s(machInst, rt, rn, true, 893 imm2, LSL, rm); 894 } else if (bits(op2, 5, 2) == 0xe) { 895 return new %(ldrsht)s(machInst, rt, rn, true, imm8); 896 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 897 const uint32_t puw = bits(machInst, 10, 8); 898 switch (puw) { 899 case 0x1: 900 return new %(ldrsh_iw)s(machInst, rt, 901 rn, false, imm8); 902 case 0x3: 903 return new %(ldrsh_iuw)s(machInst, rt, 904 rn, true, imm8); 905 case 0x4: 906 return new %(ldrsh_ip)s(machInst, rt, 907 rn, false, imm8); 908 case 0x5: 909 return new %(ldrsh_ipw)s(machInst, rt, 910 rn, false, imm8); 911 case 0x7: 912 return new %(ldrsh_ipuw)s(machInst, rt, 913 rn, true, imm8); 914 } 915 } 916 break; 917 case 0x3: 918 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12); 919 } 920 return new Unknown(machInst); 921 } 922 } 923 ''' 924 substDict = { 925 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True), 926 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True), 927 "ldrh_lit_u" : loadImmClassName(False, True, False, 2), 928 "ldrh_lit" : loadImmClassName(False, False, False, 2), 929 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True), 930 "ldrh_radd" : loadRegClassName(False, True, False, 2), 931 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True), 932 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True), 933 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True), 934 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True), 935 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True), 936 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True), 937 "ldrh_iw" : loadImmClassName(True, False, True, 2), 938 "ldrh_iuw" : loadImmClassName(True, True, True, 2), 939 "ldrh_ip" : loadImmClassName(False, False, False, 2), 940 "ldrh_ipw" : loadImmClassName(False, False, True, 2), 941 "ldrh_ipuw" : loadImmClassName(False, True, True, 2), 942 "ldrh_iadd" : loadImmClassName(False, True, False, 2), 943 "ldrht" : loadImmClassName(False, True, False, 2, user=True), 944 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True), 945 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 946 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 947 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 948 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 949 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 950 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1) 951 } 952 decode_block = decode % substDict 953}}; 954 955def format Thumb16MemReg() {{ 956 decode = ''' 957 { 958 const uint32_t opb = bits(machInst, 11, 9); 959 const uint32_t rt = bits(machInst, 2, 0); 960 const uint32_t rn = bits(machInst, 5, 3); 961 const uint32_t rm = bits(machInst, 8, 6); 962 switch (opb) { 963 case 0x0: 964 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm); 965 case 0x1: 966 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm); 967 case 0x2: 968 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm); 969 case 0x3: 970 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm); 971 case 0x4: 972 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm); 973 case 0x5: 974 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm); 975 case 0x6: 976 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm); 977 case 0x7: 978 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm); 979 } 980 } 981 ''' 982 classNames = { 983 "str" : storeRegClassName(False, True, False), 984 "strh" : storeRegClassName(False, True, False, size=2), 985 "strb" : storeRegClassName(False, True, False, size=1), 986 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1), 987 "ldr" : loadRegClassName(False, True, False), 988 "ldrh" : loadRegClassName(False, True, False, size=2), 989 "ldrb" : loadRegClassName(False, True, False, size=1), 990 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), 991 } 992 decode_block = decode % classNames 993}}; 994 995def format Thumb16MemImm() {{ 996 decode = ''' 997 { 998 const uint32_t opa = bits(machInst, 15, 12); 999 const uint32_t opb = bits(machInst, 11, 9); 1000 const uint32_t lrt = bits(machInst, 2, 0); 1001 const uint32_t lrn = bits(machInst, 5, 3); 1002 const uint32_t hrt = bits(machInst, 10, 8); 1003 const uint32_t imm5 = bits(machInst, 10, 6); 1004 const uint32_t imm8 = bits(machInst, 7, 0); 1005 const bool load = bits(opb, 2); 1006 switch (opa) { 1007 case 0x6: 1008 if (load) { 1009 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2); 1010 } else { 1011 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2); 1012 } 1013 case 0x7: 1014 if (load) { 1015 return new %(ldrb)s(machInst, lrt, lrn, true, imm5); 1016 } else { 1017 return new %(strb)s(machInst, lrt, lrn, true, imm5); 1018 } 1019 case 0x8: 1020 if (load) { 1021 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1); 1022 } else { 1023 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1); 1024 } 1025 case 0x9: 1026 if (load) { 1027 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1028 } else { 1029 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1030 } 1031 default: 1032 return new Unknown(machInst); 1033 } 1034 } 1035 ''' 1036 classNames = { 1037 "ldr" : loadImmClassName(False, True, False), 1038 "str" : storeImmClassName(False, True, False), 1039 "ldrh" : loadImmClassName(False, True, False, size=2), 1040 "strh" : storeImmClassName(False, True, False, size=2), 1041 "ldrb" : loadImmClassName(False, True, False, size=1), 1042 "strb" : storeImmClassName(False, True, False, size=1), 1043 } 1044 decode_block = decode % classNames 1045}}; 1046 1047def format Thumb16MemLit() {{ 1048 decode_block = ''' 1049 { 1050 const uint32_t rt = bits(machInst, 10, 8); 1051 const uint32_t imm8 = bits(machInst, 7, 0); 1052 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2); 1053 } 1054 ''' % loadImmClassName(False, True, False) 1055}}; 1056 1057