mem.isa revision 7314:f254f66afb11
17191Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27191Sgblack@eecs.umich.edu 37191Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47191Sgblack@eecs.umich.edu// All rights reserved 57191Sgblack@eecs.umich.edu// 67191Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77191Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87191Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97191Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107191Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117191Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127191Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137191Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147191Sgblack@eecs.umich.edu// 157191Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167191Sgblack@eecs.umich.edu// All rights reserved. 177191Sgblack@eecs.umich.edu// 187191Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197191Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207191Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217191Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227191Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237191Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247191Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257191Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267191Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277191Sgblack@eecs.umich.edu// this software without specific prior written permission. 287191Sgblack@eecs.umich.edu// 297191Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307191Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317191Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327191Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337191Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347191Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357191Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367191Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377191Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387191Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397191Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407191Sgblack@eecs.umich.edu// 417191Sgblack@eecs.umich.edu// Authors: Gabe Black 427191Sgblack@eecs.umich.edu 437191Sgblack@eecs.umich.edudef format AddrMode2(imm) {{ 447191Sgblack@eecs.umich.edu if eval(imm): 457191Sgblack@eecs.umich.edu imm = True 467191Sgblack@eecs.umich.edu else: 477308Sgblack@eecs.umich.edu imm = False 487191Sgblack@eecs.umich.edu 497316Sgblack@eecs.umich.edu def buildPUBWLCase(p, u, b, w, l): 507316Sgblack@eecs.umich.edu return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) 517316Sgblack@eecs.umich.edu 527316Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 537316Sgblack@eecs.umich.edu decode_block = "switch(PUBWL) {\n" 547316Sgblack@eecs.umich.edu 557191Sgblack@eecs.umich.edu # Loop over all the values of p, u, b, w and l and build instructions and 567191Sgblack@eecs.umich.edu # a decode block for them. 577435Sgblack@eecs.umich.edu for p in (0, 1): 587191Sgblack@eecs.umich.edu for u in (0, 1): 597191Sgblack@eecs.umich.edu for b in (0, 1): 607435Sgblack@eecs.umich.edu for w in (0, 1): 617191Sgblack@eecs.umich.edu post = (p == 0) 627191Sgblack@eecs.umich.edu user = (p == 0 and w == 1) 637248Sgblack@eecs.umich.edu writeback = (p == 0 or w == 1) 647191Sgblack@eecs.umich.edu add = (u == 1) 657192Sgblack@eecs.umich.edu if b == 0: 667192Sgblack@eecs.umich.edu size = 4 677192Sgblack@eecs.umich.edu else: 687192Sgblack@eecs.umich.edu size = 1 697192Sgblack@eecs.umich.edu if add: 707192Sgblack@eecs.umich.edu addStr = "true" 717192Sgblack@eecs.umich.edu else: 727192Sgblack@eecs.umich.edu addStr = "false" 737192Sgblack@eecs.umich.edu if imm: 747191Sgblack@eecs.umich.edu newDecode = "return new %s(machInst, RD, RN," + \ 757191Sgblack@eecs.umich.edu "%s, machInst.immed11_0);" 767191Sgblack@eecs.umich.edu loadClass = loadImmClassName(post, add, writeback, 777192Sgblack@eecs.umich.edu size, False, user) 787192Sgblack@eecs.umich.edu storeClass = storeImmClassName(post, add, writeback, 797192Sgblack@eecs.umich.edu size, False, user) 807192Sgblack@eecs.umich.edu loadDecode = newDecode % (loadClass, addStr) 817192Sgblack@eecs.umich.edu storeDecode = newDecode % (storeClass, addStr) 827192Sgblack@eecs.umich.edu else: 837192Sgblack@eecs.umich.edu newDecode = "return new %s(machInst, RD, RN, %s," + \ 847192Sgblack@eecs.umich.edu "machInst.shiftSize," + \ 857192Sgblack@eecs.umich.edu "machInst.shift, RM);" 867192Sgblack@eecs.umich.edu loadClass = loadRegClassName(post, add, writeback, 877192Sgblack@eecs.umich.edu size, False, user) 887192Sgblack@eecs.umich.edu storeClass = storeRegClassName(post, add, writeback, 897192Sgblack@eecs.umich.edu size, False, user) 907192Sgblack@eecs.umich.edu loadDecode = newDecode % (loadClass, addStr) 917192Sgblack@eecs.umich.edu storeDecode = newDecode % (storeClass, addStr) 927192Sgblack@eecs.umich.edu decode = ''' 937192Sgblack@eecs.umich.edu case %#x: 947192Sgblack@eecs.umich.edu {%s} 957192Sgblack@eecs.umich.edu break; 967192Sgblack@eecs.umich.edu ''' 977191Sgblack@eecs.umich.edu decode_block += decode % \ 987191Sgblack@eecs.umich.edu (buildPUBWLCase(p,u,b,w,1), loadDecode) 997191Sgblack@eecs.umich.edu decode_block += decode % \ 1007191Sgblack@eecs.umich.edu (buildPUBWLCase(p,u,b,w,0), storeDecode) 1017191Sgblack@eecs.umich.edu decode_block += ''' 1027191Sgblack@eecs.umich.edu default: 1037191Sgblack@eecs.umich.edu return new Unknown(machInst); 1047191Sgblack@eecs.umich.edu break; 1057191Sgblack@eecs.umich.edu }''' 1067191Sgblack@eecs.umich.edu}}; 1077191Sgblack@eecs.umich.edu 1087191Sgblack@eecs.umich.edudef format AddrMode3() {{ 1097191Sgblack@eecs.umich.edu decode = ''' 1107191Sgblack@eecs.umich.edu { 1117191Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 24, 20); 1127191Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 6, 5); 1137248Sgblack@eecs.umich.edu const uint32_t puiw = bits(machInst, 24, 21); 1147191Sgblack@eecs.umich.edu const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0; 1157192Sgblack@eecs.umich.edu switch (op2) { 1167192Sgblack@eecs.umich.edu case 0x1: 1177192Sgblack@eecs.umich.edu if (op1 & 0x1) { 1187192Sgblack@eecs.umich.edu %(ldrh)s 1197192Sgblack@eecs.umich.edu } else { 1207192Sgblack@eecs.umich.edu %(strh)s 1217192Sgblack@eecs.umich.edu } 1227192Sgblack@eecs.umich.edu case 0x2: 1237192Sgblack@eecs.umich.edu if (op1 & 0x1) { 1247192Sgblack@eecs.umich.edu %(ldrsb)s 1257192Sgblack@eecs.umich.edu } else { 1267192Sgblack@eecs.umich.edu %(ldrd)s 1277192Sgblack@eecs.umich.edu } 1287192Sgblack@eecs.umich.edu case 0x3: 1297191Sgblack@eecs.umich.edu if (op1 & 0x1) { 1307192Sgblack@eecs.umich.edu %(ldrsh)s 1317192Sgblack@eecs.umich.edu } else { 1327192Sgblack@eecs.umich.edu %(strd)s 1337192Sgblack@eecs.umich.edu } 1347192Sgblack@eecs.umich.edu default: 1357192Sgblack@eecs.umich.edu return new Unknown(machInst); 1367192Sgblack@eecs.umich.edu } 1377192Sgblack@eecs.umich.edu } 1387192Sgblack@eecs.umich.edu ''' 1397192Sgblack@eecs.umich.edu 1407192Sgblack@eecs.umich.edu def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False): 1417192Sgblack@eecs.umich.edu post = (p == 0) 1427192Sgblack@eecs.umich.edu user = (p == 0 and w == 1) 1437192Sgblack@eecs.umich.edu writeback = (p == 0 or w == 1) 1447192Sgblack@eecs.umich.edu add = (u == 1) 1457192Sgblack@eecs.umich.edu caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0) 1467192Sgblack@eecs.umich.edu decode = ''' 1477192Sgblack@eecs.umich.edu case %#x: 1487192Sgblack@eecs.umich.edu return new '''% caseVal 1497192Sgblack@eecs.umich.edu if add: 1507192Sgblack@eecs.umich.edu addStr = "true" 1517192Sgblack@eecs.umich.edu else: 1527192Sgblack@eecs.umich.edu addStr = "false" 1537192Sgblack@eecs.umich.edu if d: 1547192Sgblack@eecs.umich.edu dests = "RT & ~1, RT | 1" 1557192Sgblack@eecs.umich.edu else: 1567192Sgblack@eecs.umich.edu dests = "RT" 1577192Sgblack@eecs.umich.edu if i: 1587192Sgblack@eecs.umich.edu if load: 1597192Sgblack@eecs.umich.edu if d: 1607191Sgblack@eecs.umich.edu className = loadDoubleImmClassName(post, add, writeback) 1617191Sgblack@eecs.umich.edu else: 1627191Sgblack@eecs.umich.edu className = loadImmClassName(post, add, writeback, \ 1637191Sgblack@eecs.umich.edu size=size, sign=sign, \ 1647191Sgblack@eecs.umich.edu user=user) 1657191Sgblack@eecs.umich.edu else: 1667191Sgblack@eecs.umich.edu if d: 1677191Sgblack@eecs.umich.edu className = storeDoubleImmClassName(post, add, writeback) 1687314Sgblack@eecs.umich.edu else: 1697314Sgblack@eecs.umich.edu className = storeImmClassName(post, add, writeback, \ 1707314Sgblack@eecs.umich.edu size=size, sign=sign, \ 1717314Sgblack@eecs.umich.edu user=user) 1727314Sgblack@eecs.umich.edu decode += ("%s(machInst, %s, RN, %s, imm);\n" % \ 1737314Sgblack@eecs.umich.edu (className, dests, addStr)) 1747314Sgblack@eecs.umich.edu else: 1757314Sgblack@eecs.umich.edu if load: 1767314Sgblack@eecs.umich.edu if d: 1777314Sgblack@eecs.umich.edu className = loadDoubleRegClassName(post, add, writeback) 1787314Sgblack@eecs.umich.edu else: 1797314Sgblack@eecs.umich.edu className = loadRegClassName(post, add, writeback, \ 1807314Sgblack@eecs.umich.edu size=size, sign=sign, \ 1817314Sgblack@eecs.umich.edu user=user) 1827314Sgblack@eecs.umich.edu else: 1837314Sgblack@eecs.umich.edu if d: 1847314Sgblack@eecs.umich.edu className = storeDoubleRegClassName(post, add, writeback) 1857314Sgblack@eecs.umich.edu else: 1867314Sgblack@eecs.umich.edu className = storeRegClassName(post, add, writeback, \ 1877314Sgblack@eecs.umich.edu size=size, sign=sign, \ 1887314Sgblack@eecs.umich.edu user=user) 1897314Sgblack@eecs.umich.edu decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \ 1907314Sgblack@eecs.umich.edu (className, dests, addStr)) 1917314Sgblack@eecs.umich.edu return decode 1927314Sgblack@eecs.umich.edu 1937314Sgblack@eecs.umich.edu def decodePuiw(load, d, size=4, sign=False): 1947314Sgblack@eecs.umich.edu global decodePuiwCase 1957314Sgblack@eecs.umich.edu decode = "switch (puiw) {\n" 1967191Sgblack@eecs.umich.edu for p in (0, 1): 1977293Sgblack@eecs.umich.edu for u in (0, 1): 1987293Sgblack@eecs.umich.edu for i in (0, 1): 1997293Sgblack@eecs.umich.edu for w in (0, 1): 2007293Sgblack@eecs.umich.edu decode += decodePuiwCase(load, d, p, u, i, w, 2017293Sgblack@eecs.umich.edu size, sign) 2027293Sgblack@eecs.umich.edu decode += ''' 2037293Sgblack@eecs.umich.edu default: 2047293Sgblack@eecs.umich.edu return new Unknown(machInst); 2057293Sgblack@eecs.umich.edu } 2067293Sgblack@eecs.umich.edu ''' 2077293Sgblack@eecs.umich.edu return decode 2087293Sgblack@eecs.umich.edu 2097293Sgblack@eecs.umich.edu subs = { 2107293Sgblack@eecs.umich.edu "ldrh" : decodePuiw(True, False, size=2), 2117293Sgblack@eecs.umich.edu "strh" : decodePuiw(False, False, size=2), 2127293Sgblack@eecs.umich.edu "ldrsb" : decodePuiw(True, False, size=1, sign=True), 2137293Sgblack@eecs.umich.edu "ldrd" : decodePuiw(True, True), 2147293Sgblack@eecs.umich.edu "ldrsh" : decodePuiw(True, False, size=2, sign=True), 2157293Sgblack@eecs.umich.edu "strd" : decodePuiw(False, True) 2167293Sgblack@eecs.umich.edu } 2177293Sgblack@eecs.umich.edu decode_block = decode % subs 2187293Sgblack@eecs.umich.edu}}; 2197293Sgblack@eecs.umich.edu 2207293Sgblack@eecs.umich.edudef format ArmSyncMem() {{ 2217293Sgblack@eecs.umich.edu decode_block = ''' 2227293Sgblack@eecs.umich.edu { 2237293Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2247191Sgblack@eecs.umich.edu const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2257191Sgblack@eecs.umich.edu const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2267191Sgblack@eecs.umich.edu switch (PUBWL) { 2277191Sgblack@eecs.umich.edu case 0x10: 2287191Sgblack@eecs.umich.edu return new Swp(machInst, rt, rt2, rn); 2297191Sgblack@eecs.umich.edu case 0x14: 2307191Sgblack@eecs.umich.edu return new Swpb(machInst, rt, rt2, rn); 2317191Sgblack@eecs.umich.edu case 0x18: 2327191Sgblack@eecs.umich.edu return new %(strex)s(machInst, rt, rt2, rn, true, 0); 2337191Sgblack@eecs.umich.edu case 0x19: 2347191Sgblack@eecs.umich.edu return new %(ldrex)s(machInst, rt, rn, true, 0); 2357421Sgblack@eecs.umich.edu case 0x1a: 2367421Sgblack@eecs.umich.edu return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); 2377421Sgblack@eecs.umich.edu case 0x1b: 2387421Sgblack@eecs.umich.edu return new %(ldrexd)s(machInst, rt, rt + 1, rn, true, 0); 2397421Sgblack@eecs.umich.edu case 0x1c: 2407421Sgblack@eecs.umich.edu return new %(strexb)s(machInst, rt, rt2, rn, true, 0); 2417421Sgblack@eecs.umich.edu case 0x1d: 2427421Sgblack@eecs.umich.edu return new %(ldrexb)s(machInst, rt, rn, true, 0); 2437421Sgblack@eecs.umich.edu case 0x1e: 2447421Sgblack@eecs.umich.edu return new %(strexh)s(machInst, rt, rt2, rn, true, 0); 2457421Sgblack@eecs.umich.edu case 0x1f: 2467421Sgblack@eecs.umich.edu return new %(ldrexh)s(machInst, rt, rn, true, 0); 2477421Sgblack@eecs.umich.edu default: 2487421Sgblack@eecs.umich.edu return new Unknown(machInst); 2497421Sgblack@eecs.umich.edu } 2507421Sgblack@eecs.umich.edu } 2517421Sgblack@eecs.umich.edu ''' % { 2527191Sgblack@eecs.umich.edu "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 2537421Sgblack@eecs.umich.edu "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 2547191Sgblack@eecs.umich.edu "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 2557191Sgblack@eecs.umich.edu "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 2567421Sgblack@eecs.umich.edu "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 2577191Sgblack@eecs.umich.edu "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 2587421Sgblack@eecs.umich.edu "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), 2597421Sgblack@eecs.umich.edu "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False) 2607421Sgblack@eecs.umich.edu } 2617421Sgblack@eecs.umich.edu}}; 2627191Sgblack@eecs.umich.edu 2637191Sgblack@eecs.umich.edudef format Thumb32SrsRfe() {{ 2647191Sgblack@eecs.umich.edu decode_block = ''' 2657191Sgblack@eecs.umich.edu { 2667191Sgblack@eecs.umich.edu const bool wb = (bits(machInst, 21) == 1); 2677421Sgblack@eecs.umich.edu const bool add = (bits(machInst, 24, 23) == 0x3); 2687357Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 2697357Sgblack@eecs.umich.edu // post == add 2707359Sgblack@eecs.umich.edu const IntRegIndex rn = 2717359Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2727357Sgblack@eecs.umich.edu if (!add && !wb) { 2737191Sgblack@eecs.umich.edu return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb); 2747191Sgblack@eecs.umich.edu } else if (add && !wb) { 2757191Sgblack@eecs.umich.edu return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb); 2767191Sgblack@eecs.umich.edu } else if (!add && wb) { 2777191Sgblack@eecs.umich.edu return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb); 2787191Sgblack@eecs.umich.edu } else { 2797191Sgblack@eecs.umich.edu return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb); 2807191Sgblack@eecs.umich.edu } 2817191Sgblack@eecs.umich.edu } else { 2827191Sgblack@eecs.umich.edu const uint32_t mode = bits(machInst, 4, 0); 2837191Sgblack@eecs.umich.edu if (!add && !wb) { 2847191Sgblack@eecs.umich.edu return new %(srs)s(machInst, mode, 2857191Sgblack@eecs.umich.edu SrsOp::DecrementBefore, wb); 2867191Sgblack@eecs.umich.edu } else if (add && !wb) { 2877191Sgblack@eecs.umich.edu return new %(srs_u)s(machInst, mode, 2887191Sgblack@eecs.umich.edu SrsOp::IncrementAfter, wb); 2897191Sgblack@eecs.umich.edu } else if (!add && wb) { 2907191Sgblack@eecs.umich.edu return new %(srs_w)s(machInst, mode, 2917192Sgblack@eecs.umich.edu SrsOp::DecrementBefore, wb); 2927192Sgblack@eecs.umich.edu } else { 2937192Sgblack@eecs.umich.edu return new %(srs_uw)s(machInst, mode, 2947192Sgblack@eecs.umich.edu SrsOp::IncrementAfter, wb); 2957192Sgblack@eecs.umich.edu } 2967192Sgblack@eecs.umich.edu } 2977192Sgblack@eecs.umich.edu } 2987192Sgblack@eecs.umich.edu ''' % { 2997192Sgblack@eecs.umich.edu "rfe" : "RFE_" + loadImmClassName(False, False, False, 8), 3007192Sgblack@eecs.umich.edu "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 3017192Sgblack@eecs.umich.edu "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8), 3027192Sgblack@eecs.umich.edu "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8), 3037293Sgblack@eecs.umich.edu "srs" : "SRS_" + storeImmClassName(False, False, False, 8), 3047293Sgblack@eecs.umich.edu "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8), 3057293Sgblack@eecs.umich.edu "srs_w" : "SRS_" + storeImmClassName(False, False, True, 8), 3067293Sgblack@eecs.umich.edu "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8) 3077293Sgblack@eecs.umich.edu } 3087293Sgblack@eecs.umich.edu}}; 3097293Sgblack@eecs.umich.edu 3107293Sgblack@eecs.umich.edudef format Thumb32LdrStrDExTbh() {{ 3117314Sgblack@eecs.umich.edu decode_block = ''' 3127314Sgblack@eecs.umich.edu { 3137314Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 24, 23); 3147314Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 21, 20); 3157314Sgblack@eecs.umich.edu const uint32_t op3 = bits(machInst, 7, 4); 3167314Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3177314Sgblack@eecs.umich.edu const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3187314Sgblack@eecs.umich.edu const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 3197314Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3207192Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 3217191Sgblack@eecs.umich.edu if (bits(op1, 1) == 0 && bits(op2, 1) == 0) { 322 if (op1 == 0) { 323 const uint32_t imm = bits(machInst, 7, 0) << 2; 324 if (op2 == 0) { 325 return new %(strex)s(machInst, rt2, rt, rn, true, imm); 326 } else { 327 return new %(ldrex)s(machInst, rt, rn, true, imm); 328 } 329 } else { 330 if (op2 == 0) { 331 switch (op3) { 332 case 0x4: 333 return new %(strexb)s(machInst, rd, rt, rn, true, 0); 334 case 0x5: 335 return new %(strexh)s(machInst, rd, rt, rn, true, 0); 336 case 0x7: 337 return new %(strexd)s(machInst, rd, rt, 338 rt2, rn, true, 0); 339 default: 340 return new Unknown(machInst); 341 } 342 } else { 343 switch (op3) { 344 case 0x0: 345 return new Tbb(machInst, rn, rd); 346 case 0x1: 347 return new Tbh(machInst, rn, rd); 348 case 0x4: 349 return new %(ldrexb)s(machInst, rt, rn, true, 0); 350 case 0x5: 351 return new %(ldrexh)s(machInst, rt, rn, true, 0); 352 case 0x7: 353 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0); 354 default: 355 return new Unknown(machInst); 356 } 357 } 358 } 359 } else { 360 const uint32_t puw = (bits(machInst, 24, 23) << 1) | 361 bits(machInst, 21); 362 const uint32_t dimm = imm8 << 2; 363 if (bits(op2, 0) == 0) { 364 switch (puw) { 365 case 0x1: 366 return new %(strd_w)s(machInst, rt, rt2, rn, false, dimm); 367 case 0x3: 368 return new %(strd_uw)s(machInst, rt, rt2, rn, true, dimm); 369 case 0x4: 370 return new %(strd_p)s(machInst, rt, rt2, rn, false, dimm); 371 case 0x5: 372 return new %(strd_pw)s(machInst, rt, rt2, rn, false, dimm); 373 case 0x6: 374 return new %(strd_pu)s(machInst, rt, rt2, rn, true, dimm); 375 case 0x7: 376 return new %(strd_puw)s(machInst, rt, rt2, rn, true, dimm); 377 default: 378 return new Unknown(machInst); 379 } 380 } else { 381 switch (puw) { 382 case 0x1: 383 return new %(ldrd_w)s(machInst, rt, rt2, rn, false, dimm); 384 case 0x3: 385 return new %(ldrd_uw)s(machInst, rt, rt2, rn, true, dimm); 386 case 0x4: 387 return new %(ldrd_p)s(machInst, rt, rt2, rn, false, dimm); 388 case 0x5: 389 return new %(ldrd_pw)s(machInst, rt, rt2, rn, false, dimm); 390 case 0x6: 391 return new %(ldrd_pu)s(machInst, rt, rt2, rn, true, dimm); 392 case 0x7: 393 return new %(ldrd_puw)s(machInst, rt, rt2, rn, true, dimm); 394 default: 395 return new Unknown(machInst); 396 } 397 } 398 } 399 } 400 ''' % { 401 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 402 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 403 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 404 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 405 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 406 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 407 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), 408 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False), 409 "ldrd_w" : loadDoubleImmClassName(True, False, True), 410 "ldrd_uw" : loadDoubleImmClassName(True, True, True), 411 "ldrd_p" : loadDoubleImmClassName(False, False, False), 412 "ldrd_pw" : loadDoubleImmClassName(False, False, True), 413 "ldrd_pu" : loadDoubleImmClassName(False, True, False), 414 "ldrd_puw" : loadDoubleImmClassName(False, True, True), 415 "strd_w" : storeDoubleImmClassName(True, False, True), 416 "strd_uw" : storeDoubleImmClassName(True, True, True), 417 "strd_p" : storeDoubleImmClassName(False, False, False), 418 "strd_pw" : storeDoubleImmClassName(False, False, True), 419 "strd_pu" : storeDoubleImmClassName(False, True, False), 420 "strd_puw" : storeDoubleImmClassName(False, True, True) 421 } 422}}; 423 424def format Thumb32LoadWord() {{ 425 decode = ''' 426 { 427 uint32_t op1 = bits(machInst, 24, 23); 428 if (bits(op1, 1) == 0) { 429 uint32_t op2 = bits(machInst, 11, 6); 430 if (HTRN == 0xF) { 431 if (UP) { 432 return new %(literal_u)s(machInst, RT, INTREG_PC, 433 true, IMMED_11_0); 434 } else { 435 return new %(literal)s(machInst, RT, INTREG_PC, 436 false, IMMED_11_0); 437 } 438 } else if (op1 == 0x1) { 439 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0); 440 } else if (op2 == 0) { 441 return new %(register)s(machInst, RT, RN, UP, 442 bits(machInst, 5, 4), LSL, RM); 443 } else if ((op2 & 0x3c) == 0x38) { 444 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0); 445 } else if ((op2 & 0x3c) == 0x30 || //P 446 (op2 & 0x24) == 0x24) { //W 447 uint32_t puw = bits(machInst, 10, 8); 448 uint32_t imm = IMMED_7_0; 449 switch (puw) { 450 case 0: 451 case 2: 452 // If we're here, either P or W must have been set. 453 panic("Neither P or W set, but that " 454 "shouldn't be possible.\\n"); 455 case 1: 456 return new %(imm_w)s(machInst, RT, RN, false, imm); 457 case 3: 458 return new %(imm_uw)s(machInst, RT, RN, true, imm); 459 case 4: 460 return new %(imm_p)s(machInst, RT, RN, false, imm); 461 case 5: 462 return new %(imm_pw)s(machInst, RT, RN, false, imm); 463 case 6: 464 return new %(imm_pu)s(machInst, RT, RN, true, imm); 465 case 7: 466 return new %(imm_puw)s(machInst, RT, RN, true, imm); 467 } 468 } 469 } else { 470 return new Unknown(machInst); 471 } 472 } 473 ''' 474 classNames = { 475 "literal_u" : loadImmClassName(False, True, False), 476 "literal" : loadImmClassName(False, False, False), 477 "register" : loadRegClassName(False, True, False), 478 "ldrt" : loadImmClassName(False, True, False, user=True), 479 "imm_w" : loadImmClassName(True, False, True), 480 "imm_uw" : loadImmClassName(True, True, True), 481 "imm_p" : loadImmClassName(False, False, False), 482 "imm_pw" : loadImmClassName(False, False, True), 483 "imm_pu" : loadImmClassName(False, True, False), 484 "imm_puw" : loadImmClassName(False, True, True) 485 } 486 decode_block = decode % classNames 487}}; 488 489def format Thumb32StoreSingle() {{ 490 def buildPuwDecode(size): 491 puwDecode = ''' 492 { 493 uint32_t puw = bits(machInst, 10, 8); 494 uint32_t imm = IMMED_7_0; 495 switch (puw) { 496 case 0: 497 case 2: 498 // If we're here, either P or W must have been set. 499 panic("Neither P or W set, but that " 500 "shouldn't be possible.\\n"); 501 case 1: 502 return new %(imm_w)s(machInst, RT, RN, false, imm); 503 case 3: 504 return new %(imm_uw)s(machInst, RT, RN, true, imm); 505 case 4: 506 return new %(imm_p)s(machInst, RT, RN, false, imm); 507 case 5: 508 return new %(imm_pw)s(machInst, RT, RN, false, imm); 509 case 6: 510 return new %(imm_pu)s(machInst, RT, RN, true, imm); 511 case 7: 512 return new %(imm_puw)s(machInst, RT, RN, true, imm); 513 } 514 } 515 ''' 516 return puwDecode % { 517 "imm_w" : storeImmClassName(True, False, True, size=size), 518 "imm_uw" : storeImmClassName(True, True, True, size=size), 519 "imm_p" : storeImmClassName(False, False, False, size=size), 520 "imm_pw" : storeImmClassName(False, False, True, size=size), 521 "imm_pu" : storeImmClassName(False, True, False, size=size), 522 "imm_puw" : storeImmClassName(False, True, True, size=size) 523 } 524 decode = ''' 525 { 526 uint32_t op1 = bits(machInst, 23, 21); 527 uint32_t op2 = bits(machInst, 11, 6); 528 bool op2Puw = ((op2 & 0x24) == 0x24 || 529 (op2 & 0x3c) == 0x30); 530 if (RN == 0xf) { 531 return new Unknown(machInst); 532 } 533 if (op1 == 4) { 534 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); 535 } else if (op1 == 0 && op2Puw) { 536 %(strb_puw)s; 537 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) { 538 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0); 539 } else if (op1 == 0 && op2 == 0) { 540 return new %(strb_reg)s(machInst, RT, RN, true, 541 bits(machInst, 5, 4), LSL, RM); 542 } else if (op1 == 5) { 543 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0); 544 } else if (op1 == 1 && op2Puw) { 545 %(strh_puw)s; 546 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) { 547 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0); 548 } else if (op1 == 1 && op2 == 0) { 549 return new %(strh_reg)s(machInst, RT, RN, true, 550 bits(machInst, 5, 4), LSL, RM); 551 } else if (op1 == 6) { 552 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0); 553 } else if (op1 == 2 && op2Puw) { 554 %(str_puw)s; 555 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) { 556 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0); 557 } else if (op1 == 2 && op2 == 0) { 558 return new %(str_reg)s(machInst, RT, RN, true, 559 bits(machInst, 5, 4), LSL, RM); 560 } else { 561 return new Unknown(machInst); 562 } 563 } 564 ''' 565 classNames = { 566 "strb_imm" : storeImmClassName(False, True, False, size=1), 567 "strb_puw" : buildPuwDecode(1), 568 "strbt" : storeImmClassName(False, True, False, user=True, size=1), 569 "strb_reg" : storeRegClassName(False, True, False, size=1), 570 "strh_imm" : storeImmClassName(False, True, False, size=2), 571 "strh_puw" : buildPuwDecode(2), 572 "strht" : storeImmClassName(False, True, False, user=True, size=2), 573 "strh_reg" : storeRegClassName(False, True, False, size=2), 574 "str_imm" : storeImmClassName(False, True, False), 575 "str_puw" : buildPuwDecode(4), 576 "strt" : storeImmClassName(False, True, False, user=True), 577 "str_reg" : storeRegClassName(False, True, False) 578 } 579 decode_block = decode % classNames 580}}; 581 582def format LoadByteMemoryHints() {{ 583 decode = ''' 584 { 585 const uint32_t op1 = bits(machInst, 24, 23); 586 const uint32_t op2 = bits(machInst, 11, 6); 587 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 588 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 589 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 590 const uint32_t imm12 = bits(machInst, 11, 0); 591 const uint32_t imm8 = bits(machInst, 7, 0); 592 bool pldw = bits(machInst, 21); 593 const uint32_t imm2 = bits(machInst, 5, 4); 594 if (rn == 0xf) { 595 if (rt == 0xf) { 596 const bool add = bits(machInst, 23); 597 if (bits(op1, 1) == 1) { 598 if (add) { 599 return new %(pli_iulit)s(machInst, INTREG_ZERO, 600 INTREG_PC, true, imm12); 601 } else { 602 return new %(pli_ilit)s(machInst, INTREG_ZERO, 603 INTREG_PC, false, imm12); 604 } 605 } else { 606 if (add) { 607 return new %(pld_iulit)s(machInst, INTREG_ZERO, 608 INTREG_PC, true, imm12); 609 } else { 610 return new %(pld_ilit)s(machInst, INTREG_ZERO, 611 INTREG_PC, false, imm12); 612 } 613 } 614 } else { 615 if (bits(op1, 1) == 1) { 616 if (bits(machInst, 23)) { 617 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC, 618 true, imm12); 619 } else { 620 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC, 621 false, imm12); 622 } 623 } else { 624 if (bits(machInst, 23)) { 625 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC, 626 true, imm12); 627 } else { 628 return new %(ldrb_lit)s(machInst, rt, INTREG_PC, 629 false, imm12); 630 } 631 } 632 } 633 } else if (rt == 0xf) { 634 switch (op1) { 635 case 0x0: 636 if (op2 == 0x0) { 637 if (pldw) { 638 return new %(pldw_radd)s(machInst, INTREG_ZERO, 639 rn, true, imm2, LSL, rm); 640 } else { 641 return new %(pld_radd)s(machInst, INTREG_ZERO, 642 rn, true, imm2, LSL, rm); 643 } 644 } else if (bits(op2, 5, 2) == 0xc) { 645 if (pldw) { 646 return new %(pldw_isub)s(machInst, INTREG_ZERO, 647 rn, false, imm8); 648 } else { 649 return new %(pld_isub)s(machInst, INTREG_ZERO, 650 rn, false, imm8); 651 } 652 } 653 break; 654 case 0x1: 655 if (pldw) { 656 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 657 rn, true, imm12); 658 } else { 659 return new %(pld_iadd)s(machInst, INTREG_ZERO, 660 rn, true, imm12); 661 } 662 case 0x2: 663 if (op2 == 0x0) { 664 return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 665 true, imm2, LSL, rm); 666 } else if (bits(op2, 5, 2) == 0xc) { 667 return new %(pli_ilit)s(machInst, INTREG_ZERO, 668 INTREG_PC, false, imm8); 669 } 670 break; 671 case 0x3: 672 return new %(pli_iulit)s(machInst, INTREG_ZERO, 673 INTREG_PC, true, imm12); 674 } 675 return new Unknown(machInst); 676 } else { 677 switch (op1) { 678 case 0x0: 679 if (op2 == 0) { 680 return new %(ldrb_radd)s(machInst, rt, rn, true, 681 imm2, LSL, rm); 682 } else if (bits(op2, 5, 2) == 0xe) { 683 return new %(ldrbt)s(machInst, rt, rn, true, imm8); 684 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 685 const uint32_t puw = bits(machInst, 10, 8); 686 switch (puw) { 687 case 0x1: 688 return new %(ldrb_iw)s(machInst, rt, 689 rn, false, imm8); 690 case 0x3: 691 return new %(ldrb_iuw)s(machInst, rt, 692 rn, true, imm8); 693 case 0x4: 694 return new %(ldrb_ip)s(machInst, rt, 695 rn, false, imm8); 696 case 0x5: 697 return new %(ldrb_ipw)s(machInst, rt, 698 rn, false, imm8); 699 case 0x7: 700 return new %(ldrb_ipuw)s(machInst, rt, 701 rn, true, imm8); 702 } 703 } 704 break; 705 case 0x1: 706 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12); 707 case 0x2: 708 if (op2 == 0) { 709 return new %(ldrsb_radd)s(machInst, rt, rn, true, 710 imm2, LSL, rm); 711 } else if (bits(op2, 5, 2) == 0xe) { 712 return new %(ldrsbt)s(machInst, rt, rn, true, imm8); 713 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 714 const uint32_t puw = bits(machInst, 10, 8); 715 switch (puw) { 716 case 0x1: 717 return new %(ldrsb_iw)s(machInst, rt, 718 rn, false, imm8); 719 case 0x3: 720 return new %(ldrsb_iuw)s(machInst, rt, 721 rn, true, imm8); 722 case 0x4: 723 return new %(ldrsb_ip)s(machInst, rt, 724 rn, false, imm8); 725 case 0x5: 726 return new %(ldrsb_ipw)s(machInst, rt, 727 rn, false, imm8); 728 case 0x7: 729 return new %(ldrsb_ipuw)s(machInst, rt, 730 rn, true, imm8); 731 } 732 } 733 break; 734 case 0x3: 735 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12); 736 } 737 return new Unknown(machInst); 738 } 739 } 740 ''' 741 substDict = { 742 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True), 743 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True), 744 "ldrb_lit_u" : loadImmClassName(False, True, False, 1), 745 "ldrb_lit" : loadImmClassName(False, False, False, 1), 746 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True), 747 "ldrb_radd" : loadRegClassName(False, True, False, 1), 748 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True), 749 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True), 750 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True), 751 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True), 752 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True), 753 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True), 754 "ldrb_iw" : loadImmClassName(True, False, True, 1), 755 "ldrb_iuw" : loadImmClassName(True, True, True, 1), 756 "ldrb_ip" : loadImmClassName(False, False, False, 1), 757 "ldrb_ipw" : loadImmClassName(False, False, True, 1), 758 "ldrb_ipuw" : loadImmClassName(False, True, True, 1), 759 "ldrb_iadd" : loadImmClassName(False, True, False, 1), 760 "ldrbt" : loadImmClassName(False, True, False, 1, user=True), 761 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True), 762 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 763 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 764 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 765 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 766 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 767 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 768 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1), 769 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1), 770 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 771 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1), 772 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 773 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 774 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1) 775 } 776 decode_block = decode % substDict 777}}; 778 779def format LoadHalfwordMemoryHints() {{ 780 decode = ''' 781 { 782 const uint32_t op1 = bits(machInst, 24, 23); 783 const uint32_t op2 = bits(machInst, 11, 6); 784 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 785 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 786 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 787 const uint32_t imm12 = bits(machInst, 11, 0); 788 const uint32_t imm8 = bits(machInst, 7, 0); 789 bool pldw = bits(machInst, 21); 790 const uint32_t imm2 = bits(machInst, 5, 4); 791 if (rn == 0xf) { 792 if (rt == 0xf) { 793 if (bits(op1, 1) == 1) { 794 // Unallocated memory hint 795 return new NopInst(machInst); 796 } else { 797 return new Unknown(machInst); 798 } 799 } else { 800 if (bits(op1, 1) == 1) { 801 if (bits(machInst, 23)) { 802 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC, 803 true, imm12); 804 } else { 805 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC, 806 false, imm12); 807 } 808 } else { 809 if (bits(machInst, 23)) { 810 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC, 811 true, imm12); 812 } else { 813 return new %(ldrh_lit)s(machInst, rt, INTREG_PC, 814 false, imm12); 815 } 816 } 817 } 818 } else if (rt == 0xf) { 819 switch (op1) { 820 case 0x0: 821 if (op2 == 0x0) { 822 if (pldw) { 823 return new %(pldw_radd)s(machInst, INTREG_ZERO, 824 rn, true, imm2, LSL, rm); 825 } else { 826 return new %(pld_radd)s(machInst, INTREG_ZERO, 827 rn, true, imm2, LSL, rm); 828 } 829 } else if (bits(op2, 5, 2) == 0xc) { 830 if (pldw) { 831 return new %(pldw_isub)s(machInst, INTREG_ZERO, 832 rn, false, imm8); 833 } else { 834 return new %(pld_isub)s(machInst, INTREG_ZERO, 835 rn, false, imm8); 836 } 837 } 838 break; 839 case 0x1: 840 if (pldw) { 841 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 842 rn, true, imm12); 843 } else { 844 return new %(pld_iadd)s(machInst, INTREG_ZERO, 845 rn, true, imm12); 846 } 847 case 0x2: 848 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) { 849 // Unallocated memory hint 850 return new NopInst(machInst); 851 } 852 break; 853 case 0x3: 854 return new NopInst(machInst); 855 } 856 return new Unknown(machInst); 857 } else { 858 switch (op1) { 859 case 0x0: 860 if (op2 == 0) { 861 return new %(ldrh_radd)s(machInst, rt, rn, true, 862 imm2, LSL, rm); 863 } else if (bits(op2, 5, 2) == 0xe) { 864 return new %(ldrht)s(machInst, rt, rn, true, imm8); 865 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 866 const uint32_t puw = bits(machInst, 10, 8); 867 switch (puw) { 868 case 0x1: 869 return new %(ldrh_iw)s(machInst, rt, 870 rn, false, imm8); 871 case 0x3: 872 return new %(ldrh_iuw)s(machInst, rt, 873 rn, true, imm8); 874 case 0x4: 875 return new %(ldrh_ip)s(machInst, rt, 876 rn, false, imm8); 877 case 0x5: 878 return new %(ldrh_ipw)s(machInst, rt, 879 rn, false, imm8); 880 case 0x7: 881 return new %(ldrh_ipuw)s(machInst, rt, 882 rn, true, imm8); 883 } 884 } 885 break; 886 case 0x1: 887 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12); 888 case 0x2: 889 if (op2 == 0) { 890 return new %(ldrsh_radd)s(machInst, rt, rn, true, 891 imm2, LSL, rm); 892 } else if (bits(op2, 5, 2) == 0xe) { 893 return new %(ldrsht)s(machInst, rt, rn, true, imm8); 894 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 895 const uint32_t puw = bits(machInst, 10, 8); 896 switch (puw) { 897 case 0x1: 898 return new %(ldrsh_iw)s(machInst, rt, 899 rn, false, imm8); 900 case 0x3: 901 return new %(ldrsh_iuw)s(machInst, rt, 902 rn, true, imm8); 903 case 0x4: 904 return new %(ldrsh_ip)s(machInst, rt, 905 rn, false, imm8); 906 case 0x5: 907 return new %(ldrsh_ipw)s(machInst, rt, 908 rn, false, imm8); 909 case 0x7: 910 return new %(ldrsh_ipuw)s(machInst, rt, 911 rn, true, imm8); 912 } 913 } 914 break; 915 case 0x3: 916 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12); 917 } 918 return new Unknown(machInst); 919 } 920 } 921 ''' 922 substDict = { 923 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True), 924 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True), 925 "ldrh_lit_u" : loadImmClassName(False, True, False, 2), 926 "ldrh_lit" : loadImmClassName(False, False, False, 2), 927 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True), 928 "ldrh_radd" : loadRegClassName(False, True, False, 2), 929 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True), 930 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True), 931 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True), 932 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True), 933 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True), 934 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True), 935 "ldrh_iw" : loadImmClassName(True, False, True, 2), 936 "ldrh_iuw" : loadImmClassName(True, True, True, 2), 937 "ldrh_ip" : loadImmClassName(False, False, False, 2), 938 "ldrh_ipw" : loadImmClassName(False, False, True, 2), 939 "ldrh_ipuw" : loadImmClassName(False, True, True, 2), 940 "ldrh_iadd" : loadImmClassName(False, True, False, 2), 941 "ldrht" : loadImmClassName(False, True, False, 2, user=True), 942 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True), 943 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 944 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 945 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 946 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 947 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 948 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1) 949 } 950 decode_block = decode % substDict 951}}; 952 953def format Thumb16MemReg() {{ 954 decode = ''' 955 { 956 const uint32_t opb = bits(machInst, 11, 9); 957 const uint32_t rt = bits(machInst, 2, 0); 958 const uint32_t rn = bits(machInst, 5, 3); 959 const uint32_t rm = bits(machInst, 8, 6); 960 switch (opb) { 961 case 0x0: 962 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm); 963 case 0x1: 964 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm); 965 case 0x2: 966 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm); 967 case 0x3: 968 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm); 969 case 0x4: 970 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm); 971 case 0x5: 972 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm); 973 case 0x6: 974 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm); 975 case 0x7: 976 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm); 977 } 978 } 979 ''' 980 classNames = { 981 "str" : storeRegClassName(False, True, False), 982 "strh" : storeRegClassName(False, True, False, size=2), 983 "strb" : storeRegClassName(False, True, False, size=1), 984 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1), 985 "ldr" : loadRegClassName(False, True, False), 986 "ldrh" : loadRegClassName(False, True, False, size=2), 987 "ldrb" : loadRegClassName(False, True, False, size=1), 988 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), 989 } 990 decode_block = decode % classNames 991}}; 992 993def format Thumb16MemImm() {{ 994 decode = ''' 995 { 996 const uint32_t opa = bits(machInst, 15, 12); 997 const uint32_t opb = bits(machInst, 11, 9); 998 const uint32_t lrt = bits(machInst, 2, 0); 999 const uint32_t lrn = bits(machInst, 5, 3); 1000 const uint32_t hrt = bits(machInst, 10, 8); 1001 const uint32_t imm5 = bits(machInst, 10, 6); 1002 const uint32_t imm8 = bits(machInst, 7, 0); 1003 const bool load = bits(opb, 2); 1004 switch (opa) { 1005 case 0x6: 1006 if (load) { 1007 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2); 1008 } else { 1009 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2); 1010 } 1011 case 0x7: 1012 if (load) { 1013 return new %(ldrb)s(machInst, lrt, lrn, true, imm5); 1014 } else { 1015 return new %(strb)s(machInst, lrt, lrn, true, imm5); 1016 } 1017 case 0x8: 1018 if (load) { 1019 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1); 1020 } else { 1021 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1); 1022 } 1023 case 0x9: 1024 if (load) { 1025 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1026 } else { 1027 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1028 } 1029 default: 1030 return new Unknown(machInst); 1031 } 1032 } 1033 ''' 1034 classNames = { 1035 "ldr" : loadImmClassName(False, True, False), 1036 "str" : storeImmClassName(False, True, False), 1037 "ldrh" : loadImmClassName(False, True, False, size=2), 1038 "strh" : storeImmClassName(False, True, False, size=2), 1039 "ldrb" : loadImmClassName(False, True, False, size=1), 1040 "strb" : storeImmClassName(False, True, False, size=1), 1041 } 1042 decode_block = decode % classNames 1043}}; 1044 1045def format Thumb16MemLit() {{ 1046 decode_block = ''' 1047 { 1048 const uint32_t rt = bits(machInst, 10, 8); 1049 const uint32_t imm8 = bits(machInst, 7, 0); 1050 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2); 1051 } 1052 ''' % loadImmClassName(False, True, False) 1053}}; 1054 1055