mem.isa revision 7304:ce1844ce6412
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Gabe Black 42 43def format AddrMode2(imm) {{ 44 if eval(imm): 45 imm = True 46 else: 47 imm = False 48 49 def buildPUBWLCase(p, u, b, w, l): 50 return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) 51 52 header_output = decoder_output = exec_output = "" 53 decode_block = "switch(PUBWL) {\n" 54 55 # Loop over all the values of p, u, b, w and l and build instructions and 56 # a decode block for them. 57 for p in (0, 1): 58 for u in (0, 1): 59 for b in (0, 1): 60 for w in (0, 1): 61 post = (p == 0) 62 user = (p == 0 and w == 1) 63 writeback = (p == 0 or w == 1) 64 add = (u == 1) 65 if b == 0: 66 size = 4 67 else: 68 size = 1 69 if add: 70 addStr = "true" 71 else: 72 addStr = "false" 73 if imm: 74 newDecode = "return new %s(machInst, RD, RN," + \ 75 "%s, machInst.immed11_0);" 76 loadClass = loadImmClassName(post, add, writeback, 77 size, False, user) 78 storeClass = storeImmClassName(post, add, writeback, 79 size, False, user) 80 loadDecode = newDecode % (loadClass, addStr) 81 storeDecode = newDecode % (storeClass, addStr) 82 else: 83 newDecode = "return new %s(machInst, RD, RN, %s," + \ 84 "machInst.shiftSize," + \ 85 "machInst.shift, RM);" 86 loadClass = loadRegClassName(post, add, writeback, 87 size, False, user) 88 storeClass = storeRegClassName(post, add, writeback, 89 size, False, user) 90 loadDecode = newDecode % (loadClass, addStr) 91 storeDecode = newDecode % (storeClass, addStr) 92 decode = ''' 93 case %#x: 94 {%s} 95 break; 96 ''' 97 decode_block += decode % \ 98 (buildPUBWLCase(p,u,b,w,1), loadDecode) 99 decode_block += decode % \ 100 (buildPUBWLCase(p,u,b,w,0), storeDecode) 101 decode_block += ''' 102 default: 103 return new Unknown(machInst); 104 break; 105 }''' 106}}; 107 108def format AddrMode3() {{ 109 decode = ''' 110 { 111 const uint32_t op1 = bits(machInst, 24, 20); 112 const uint32_t op2 = bits(machInst, 6, 5); 113 const uint32_t puiw = bits(machInst, 24, 21); 114 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0; 115 switch (op2) { 116 case 0x1: 117 if (op1 & 0x1) { 118 %(ldrh)s 119 } else { 120 %(strh)s 121 } 122 case 0x2: 123 if (op1 & 0x1) { 124 %(ldrsb)s 125 } else { 126 %(ldrd)s 127 } 128 case 0x3: 129 if (op1 & 0x1) { 130 %(ldrsh)s 131 } else { 132 %(strd)s 133 } 134 default: 135 return new Unknown(machInst); 136 } 137 } 138 ''' 139 140 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False): 141 post = (p == 0) 142 user = (p == 0 and w == 1) 143 writeback = (p == 0 or w == 1) 144 add = (u == 1) 145 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0) 146 decode = ''' 147 case %#x: 148 return new '''% caseVal 149 if add: 150 addStr = "true" 151 else: 152 addStr = "false" 153 if d: 154 dests = "RT & ~1, RT | 1" 155 else: 156 dests = "RT" 157 if i: 158 if load: 159 if d: 160 className = loadDoubleImmClassName(post, add, writeback) 161 else: 162 className = loadImmClassName(post, add, writeback, \ 163 size=size, sign=sign, \ 164 user=user) 165 else: 166 if d: 167 className = storeDoubleImmClassName(post, add, writeback) 168 else: 169 className = storeImmClassName(post, add, writeback, \ 170 size=size, sign=sign, \ 171 user=user) 172 decode += ("%s(machInst, %s, RN, %s, imm);\n" % \ 173 (className, dests, addStr)) 174 else: 175 if load: 176 if d: 177 className = loadDoubleRegClassName(post, add, writeback) 178 else: 179 className = loadRegClassName(post, add, writeback, \ 180 size=size, sign=sign, \ 181 user=user) 182 else: 183 if d: 184 className = storeDoubleRegClassName(post, add, writeback) 185 else: 186 className = storeRegClassName(post, add, writeback, \ 187 size=size, sign=sign, \ 188 user=user) 189 decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \ 190 (className, dests, addStr)) 191 return decode 192 193 def decodePuiw(load, d, size=4, sign=False): 194 global decodePuiwCase 195 decode = "switch (puiw) {\n" 196 for p in (0, 1): 197 for u in (0, 1): 198 for i in (0, 1): 199 for w in (0, 1): 200 decode += decodePuiwCase(load, d, p, u, i, w, 201 size, sign) 202 decode += ''' 203 default: 204 return new Unknown(machInst); 205 } 206 ''' 207 return decode 208 209 subs = { 210 "ldrh" : decodePuiw(True, False, size=2), 211 "strh" : decodePuiw(False, False, size=2), 212 "ldrsb" : decodePuiw(True, False, size=1, sign=True), 213 "ldrd" : decodePuiw(True, True), 214 "ldrsh" : decodePuiw(True, False, size=2, sign=True), 215 "strd" : decodePuiw(False, True) 216 } 217 decode_block = decode % subs 218}}; 219 220def format ArmSyncMem() {{ 221 decode_block = ''' 222 { 223 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 224 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 225 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 226 switch (PUBWL) { 227 case 0x10: 228 return new Swp(machInst, rt, rt2, rn); 229 case 0x14: 230 return new Swpb(machInst, rt, rt2, rn); 231 case 0x18: 232 return new %(strex)s(machInst, rt, rt2, rn, true, 0); 233 case 0x19: 234 return new %(ldrex)s(machInst, rt, rn, true, 0); 235 case 0x1a: 236 return new %(strexd)s(machInst, rt, rt2, rt2 + 1, rn, true, 0); 237 case 0x1b: 238 return new WarnUnimplemented("ldrexd", machInst); 239 case 0x1c: 240 return new %(strexb)s(machInst, rt, rt2, rn, true, 0); 241 case 0x1d: 242 return new %(ldrexb)s(machInst, rt, rn, true, 0); 243 case 0x1e: 244 return new %(strexh)s(machInst, rt, rt2, rn, true, 0); 245 case 0x1f: 246 return new %(ldrexh)s(machInst, rt, rn, true, 0); 247 default: 248 return new Unknown(machInst); 249 } 250 } 251 ''' % { 252 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 253 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 254 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 255 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 256 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 257 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), 258 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False) 259 } 260}}; 261 262def format Thumb32SrsRfe() {{ 263 decode_block = ''' 264 { 265 if (bits(machInst, 20) == 1) { 266 const bool add = (bits(machInst, 24, 23) == 0x3); 267 // post == add 268 const bool wb = (bits(machInst, 21) == 1); 269 const IntRegIndex rn = 270 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 271 if (!add && !wb) { 272 return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb); 273 } else if (add && !wb) { 274 return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb); 275 } else if (!add && wb) { 276 return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb); 277 } else { 278 return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb); 279 } 280 } else { 281 return new WarnUnimplemented("srs", machInst); 282 } 283 } 284 ''' % { 285 "rfe" : "RFE_" + loadImmClassName(False, False, False, 8), 286 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 287 "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8), 288 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8) 289 } 290}}; 291 292def format Thumb32LdrStrDExTbh() {{ 293 decode_block = ''' 294 { 295 const uint32_t op1 = bits(machInst, 24, 23); 296 const uint32_t op2 = bits(machInst, 21, 20); 297 const uint32_t op3 = bits(machInst, 7, 4); 298 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 299 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 300 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 301 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 302 const uint32_t imm8 = bits(machInst, 7, 0); 303 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) { 304 if (op1 == 0) { 305 const uint32_t imm = bits(machInst, 7, 0) << 2; 306 if (op2 == 0) { 307 return new %(strex)s(machInst, rt2, rt, rn, true, imm); 308 } else { 309 return new %(ldrex)s(machInst, rt, rn, true, imm); 310 } 311 } else { 312 if (op2 == 0) { 313 switch (op3) { 314 case 0x4: 315 return new %(strexb)s(machInst, rd, rt, rn, true, 0); 316 case 0x5: 317 return new %(strexh)s(machInst, rd, rt, rn, true, 0); 318 case 0x7: 319 return new %(strexd)s(machInst, rd, rt, 320 rt2, rn, true, 0); 321 default: 322 return new Unknown(machInst); 323 } 324 } else { 325 switch (op3) { 326 case 0x0: 327 return new WarnUnimplemented("tbb", machInst); 328 case 0x1: 329 return new WarnUnimplemented("tbh", machInst); 330 case 0x4: 331 return new %(ldrexb)s(machInst, rt, rn, true, 0); 332 case 0x5: 333 return new %(ldrexh)s(machInst, rt, rn, true, 0); 334 case 0x7: 335 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0); 336 default: 337 return new Unknown(machInst); 338 } 339 } 340 } 341 } else { 342 const uint32_t puw = (bits(machInst, 24, 23) << 1) | 343 bits(machInst, 21); 344 const uint32_t dimm = imm8 << 2; 345 if (bits(op2, 0) == 0) { 346 switch (puw) { 347 case 0x1: 348 return new %(strd_w)s(machInst, rt, rt2, rn, false, dimm); 349 case 0x3: 350 return new %(strd_uw)s(machInst, rt, rt2, rn, true, dimm); 351 case 0x4: 352 return new %(strd_p)s(machInst, rt, rt2, rn, false, dimm); 353 case 0x5: 354 return new %(strd_pw)s(machInst, rt, rt2, rn, false, dimm); 355 case 0x6: 356 return new %(strd_pu)s(machInst, rt, rt2, rn, true, dimm); 357 case 0x7: 358 return new %(strd_puw)s(machInst, rt, rt2, rn, true, dimm); 359 default: 360 return new Unknown(machInst); 361 } 362 } else { 363 switch (puw) { 364 case 0x1: 365 return new %(ldrd_w)s(machInst, rt, rt2, rn, false, dimm); 366 case 0x3: 367 return new %(ldrd_uw)s(machInst, rt, rt2, rn, true, dimm); 368 case 0x4: 369 return new %(ldrd_p)s(machInst, rt, rt2, rn, false, dimm); 370 case 0x5: 371 return new %(ldrd_pw)s(machInst, rt, rt2, rn, false, dimm); 372 case 0x6: 373 return new %(ldrd_pu)s(machInst, rt, rt2, rn, true, dimm); 374 case 0x7: 375 return new %(ldrd_puw)s(machInst, rt, rt2, rn, true, dimm); 376 default: 377 return new Unknown(machInst); 378 } 379 } 380 } 381 } 382 ''' % { 383 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 384 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 385 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 386 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 387 "strex" : "STREX_" + storeImmClassName(False, True, False, size=4), 388 "strexb" : "STREXB_" + storeImmClassName(False, True, False, size=1), 389 "strexh" : "STREXH_" + storeImmClassName(False, True, False, size=2), 390 "strexd" : "STREXD_" + storeDoubleImmClassName(False, True, False), 391 "ldrd_w" : loadDoubleImmClassName(True, False, True), 392 "ldrd_uw" : loadDoubleImmClassName(True, True, True), 393 "ldrd_p" : loadDoubleImmClassName(False, False, False), 394 "ldrd_pw" : loadDoubleImmClassName(False, False, True), 395 "ldrd_pu" : loadDoubleImmClassName(False, True, False), 396 "ldrd_puw" : loadDoubleImmClassName(False, True, True), 397 "strd_w" : storeDoubleImmClassName(True, False, True), 398 "strd_uw" : storeDoubleImmClassName(True, True, True), 399 "strd_p" : storeDoubleImmClassName(False, False, False), 400 "strd_pw" : storeDoubleImmClassName(False, False, True), 401 "strd_pu" : storeDoubleImmClassName(False, True, False), 402 "strd_puw" : storeDoubleImmClassName(False, True, True) 403 } 404}}; 405 406def format Thumb32LoadWord() {{ 407 decode = ''' 408 { 409 uint32_t op1 = bits(machInst, 24, 23); 410 if (bits(op1, 1) == 0) { 411 uint32_t op2 = bits(machInst, 11, 6); 412 if (HTRN == 0xF) { 413 if (UP) { 414 return new %(literal_u)s(machInst, RT, INTREG_PC, 415 true, IMMED_11_0); 416 } else { 417 return new %(literal)s(machInst, RT, INTREG_PC, 418 false, IMMED_11_0); 419 } 420 } else if (op1 == 0x1) { 421 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0); 422 } else if (op2 == 0) { 423 return new %(register)s(machInst, RT, RN, UP, 424 bits(machInst, 5, 4), LSL, RM); 425 } else if ((op2 & 0x3c) == 0x38) { 426 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0); 427 } else if ((op2 & 0x3c) == 0x30 || //P 428 (op2 & 0x24) == 0x24) { //W 429 uint32_t puw = bits(machInst, 10, 8); 430 uint32_t imm = IMMED_7_0; 431 switch (puw) { 432 case 0: 433 case 2: 434 // If we're here, either P or W must have been set. 435 panic("Neither P or W set, but that " 436 "shouldn't be possible.\\n"); 437 case 1: 438 return new %(imm_w)s(machInst, RT, RN, false, imm); 439 case 3: 440 return new %(imm_uw)s(machInst, RT, RN, true, imm); 441 case 4: 442 return new %(imm_p)s(machInst, RT, RN, false, imm); 443 case 5: 444 return new %(imm_pw)s(machInst, RT, RN, false, imm); 445 case 6: 446 return new %(imm_pu)s(machInst, RT, RN, true, imm); 447 case 7: 448 return new %(imm_puw)s(machInst, RT, RN, true, imm); 449 } 450 } 451 } else { 452 return new Unknown(machInst); 453 } 454 } 455 ''' 456 classNames = { 457 "literal_u" : loadImmClassName(False, True, False), 458 "literal" : loadImmClassName(False, False, False), 459 "register" : loadRegClassName(False, True, False), 460 "ldrt" : loadImmClassName(False, True, False, user=True), 461 "imm_w" : loadImmClassName(True, False, True), 462 "imm_uw" : loadImmClassName(True, True, True), 463 "imm_p" : loadImmClassName(False, False, False), 464 "imm_pw" : loadImmClassName(False, False, True), 465 "imm_pu" : loadImmClassName(False, True, False), 466 "imm_puw" : loadImmClassName(False, True, True) 467 } 468 decode_block = decode % classNames 469}}; 470 471def format Thumb32StoreSingle() {{ 472 def buildPuwDecode(size): 473 puwDecode = ''' 474 { 475 uint32_t puw = bits(machInst, 10, 8); 476 uint32_t imm = IMMED_7_0; 477 switch (puw) { 478 case 0: 479 case 2: 480 // If we're here, either P or W must have been set. 481 panic("Neither P or W set, but that " 482 "shouldn't be possible.\\n"); 483 case 1: 484 return new %(imm_w)s(machInst, RT, RN, false, imm); 485 case 3: 486 return new %(imm_uw)s(machInst, RT, RN, true, imm); 487 case 4: 488 return new %(imm_p)s(machInst, RT, RN, false, imm); 489 case 5: 490 return new %(imm_pw)s(machInst, RT, RN, false, imm); 491 case 6: 492 return new %(imm_pu)s(machInst, RT, RN, true, imm); 493 case 7: 494 return new %(imm_puw)s(machInst, RT, RN, true, imm); 495 } 496 } 497 ''' 498 return puwDecode % { 499 "imm_w" : storeImmClassName(True, False, True, size=size), 500 "imm_uw" : storeImmClassName(True, True, True, size=size), 501 "imm_p" : storeImmClassName(False, False, False, size=size), 502 "imm_pw" : storeImmClassName(False, False, True, size=size), 503 "imm_pu" : storeImmClassName(False, True, False, size=size), 504 "imm_puw" : storeImmClassName(False, True, True, size=size) 505 } 506 decode = ''' 507 { 508 uint32_t op1 = bits(machInst, 23, 21); 509 uint32_t op2 = bits(machInst, 11, 6); 510 bool op2Puw = ((op2 & 0x24) == 0x24 || 511 (op2 & 0x3c) == 0x30); 512 if (RN == 0xf) { 513 return new Unknown(machInst); 514 } 515 if (op1 == 4) { 516 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); 517 } else if (op1 == 0 && op2Puw) { 518 %(strb_puw)s; 519 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) { 520 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0); 521 } else if (op1 == 0 && op2 == 0) { 522 return new %(strb_reg)s(machInst, RT, RN, true, 523 bits(machInst, 5, 4), LSL, RM); 524 } else if (op1 == 5) { 525 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0); 526 } else if (op1 == 1 && op2Puw) { 527 %(strh_puw)s; 528 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) { 529 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0); 530 } else if (op1 == 1 && op2 == 0) { 531 return new %(strh_reg)s(machInst, RT, RN, true, 532 bits(machInst, 5, 4), LSL, RM); 533 } else if (op1 == 6) { 534 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0); 535 } else if (op1 == 2 && op2Puw) { 536 %(str_puw)s; 537 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) { 538 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0); 539 } else if (op1 == 2 && op2 == 0) { 540 return new %(str_reg)s(machInst, RT, RN, true, 541 bits(machInst, 5, 4), LSL, RM); 542 } else { 543 return new Unknown(machInst); 544 } 545 } 546 ''' 547 classNames = { 548 "strb_imm" : storeImmClassName(False, True, False, size=1), 549 "strb_puw" : buildPuwDecode(1), 550 "strbt" : storeImmClassName(False, True, False, user=True, size=1), 551 "strb_reg" : storeRegClassName(False, True, False, size=1), 552 "strh_imm" : storeImmClassName(False, True, False, size=2), 553 "strh_puw" : buildPuwDecode(2), 554 "strht" : storeImmClassName(False, True, False, user=True, size=2), 555 "strh_reg" : storeRegClassName(False, True, False, size=2), 556 "str_imm" : storeImmClassName(False, True, False), 557 "str_puw" : buildPuwDecode(4), 558 "strt" : storeImmClassName(False, True, False, user=True), 559 "str_reg" : storeRegClassName(False, True, False) 560 } 561 decode_block = decode % classNames 562}}; 563 564def format LoadByteMemoryHints() {{ 565 decode = ''' 566 { 567 const uint32_t op1 = bits(machInst, 24, 23); 568 const uint32_t op2 = bits(machInst, 11, 6); 569 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 570 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 571 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 572 const uint32_t imm12 = bits(machInst, 11, 0); 573 const uint32_t imm8 = bits(machInst, 7, 0); 574 bool pldw = bits(machInst, 21); 575 const uint32_t imm2 = bits(machInst, 5, 4); 576 if (rn == 0xf) { 577 if (rt == 0xf) { 578 const bool add = bits(machInst, 23); 579 if (bits(op1, 1) == 1) { 580 if (add) { 581 return new %(pli_iulit)s(machInst, INTREG_ZERO, 582 INTREG_PC, true, imm12); 583 } else { 584 return new %(pli_ilit)s(machInst, INTREG_ZERO, 585 INTREG_PC, false, imm12); 586 } 587 } else { 588 if (add) { 589 return new %(pld_iulit)s(machInst, INTREG_ZERO, 590 INTREG_PC, true, imm12); 591 } else { 592 return new %(pld_ilit)s(machInst, INTREG_ZERO, 593 INTREG_PC, false, imm12); 594 } 595 } 596 } else { 597 if (bits(op1, 1) == 1) { 598 if (bits(machInst, 23)) { 599 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC, 600 true, imm12); 601 } else { 602 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC, 603 false, imm12); 604 } 605 } else { 606 if (bits(machInst, 23)) { 607 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC, 608 true, imm12); 609 } else { 610 return new %(ldrb_lit)s(machInst, rt, INTREG_PC, 611 false, imm12); 612 } 613 } 614 } 615 } else if (rt == 0xf) { 616 switch (op1) { 617 case 0x0: 618 if (op2 == 0x0) { 619 if (pldw) { 620 return new %(pldw_radd)s(machInst, INTREG_ZERO, 621 rn, true, imm2, LSL, rm); 622 } else { 623 return new %(pld_radd)s(machInst, INTREG_ZERO, 624 rn, true, imm2, LSL, rm); 625 } 626 } else if (bits(op2, 5, 2) == 0xc) { 627 if (pldw) { 628 return new %(pldw_isub)s(machInst, INTREG_ZERO, 629 rn, false, imm8); 630 } else { 631 return new %(pld_isub)s(machInst, INTREG_ZERO, 632 rn, false, imm8); 633 } 634 } 635 break; 636 case 0x1: 637 if (pldw) { 638 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 639 rn, true, imm12); 640 } else { 641 return new %(pld_iadd)s(machInst, INTREG_ZERO, 642 rn, true, imm12); 643 } 644 case 0x2: 645 if (op2 == 0x0) { 646 return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 647 true, imm2, LSL, rm); 648 } else if (bits(op2, 5, 2) == 0xc) { 649 return new %(pli_ilit)s(machInst, INTREG_ZERO, 650 INTREG_PC, false, imm8); 651 } 652 break; 653 case 0x3: 654 return new %(pli_iulit)s(machInst, INTREG_ZERO, 655 INTREG_PC, true, imm12); 656 } 657 return new Unknown(machInst); 658 } else { 659 switch (op1) { 660 case 0x0: 661 if (op2 == 0) { 662 return new %(ldrb_radd)s(machInst, rt, rn, true, 663 imm2, LSL, rm); 664 } else if (bits(op2, 5, 2) == 0xe) { 665 return new %(ldrbt)s(machInst, rt, rn, true, imm8); 666 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 667 const uint32_t puw = bits(machInst, 10, 8); 668 switch (puw) { 669 case 0x1: 670 return new %(ldrb_iw)s(machInst, rt, 671 rn, false, imm8); 672 case 0x3: 673 return new %(ldrb_iuw)s(machInst, rt, 674 rn, true, imm8); 675 case 0x4: 676 return new %(ldrb_ip)s(machInst, rt, 677 rn, false, imm8); 678 case 0x5: 679 return new %(ldrb_ipw)s(machInst, rt, 680 rn, false, imm8); 681 case 0x7: 682 return new %(ldrb_ipuw)s(machInst, rt, 683 rn, true, imm8); 684 } 685 } 686 break; 687 case 0x1: 688 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12); 689 case 0x2: 690 if (op2 == 0) { 691 return new %(ldrsb_radd)s(machInst, rt, rn, true, 692 imm2, LSL, rm); 693 } else if (bits(op2, 5, 2) == 0xe) { 694 return new %(ldrsbt)s(machInst, rt, rn, true, imm8); 695 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 696 const uint32_t puw = bits(machInst, 10, 8); 697 switch (puw) { 698 case 0x1: 699 return new %(ldrsb_iw)s(machInst, rt, 700 rn, false, imm8); 701 case 0x3: 702 return new %(ldrsb_iuw)s(machInst, rt, 703 rn, true, imm8); 704 case 0x4: 705 return new %(ldrsb_ip)s(machInst, rt, 706 rn, false, imm8); 707 case 0x5: 708 return new %(ldrsb_ipw)s(machInst, rt, 709 rn, false, imm8); 710 case 0x7: 711 return new %(ldrsb_ipuw)s(machInst, rt, 712 rn, true, imm8); 713 } 714 } 715 break; 716 case 0x3: 717 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12); 718 } 719 return new Unknown(machInst); 720 } 721 } 722 ''' 723 substDict = { 724 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True), 725 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True), 726 "ldrb_lit_u" : loadImmClassName(False, True, False, 1), 727 "ldrb_lit" : loadImmClassName(False, False, False, 1), 728 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True), 729 "ldrb_radd" : loadRegClassName(False, True, False, 1), 730 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True), 731 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True), 732 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True), 733 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True), 734 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True), 735 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True), 736 "ldrb_iw" : loadImmClassName(True, False, True, 1), 737 "ldrb_iuw" : loadImmClassName(True, True, True, 1), 738 "ldrb_ip" : loadImmClassName(False, False, False, 1), 739 "ldrb_ipw" : loadImmClassName(False, False, True, 1), 740 "ldrb_ipuw" : loadImmClassName(False, True, True, 1), 741 "ldrb_iadd" : loadImmClassName(False, True, False, 1), 742 "ldrbt" : loadImmClassName(False, True, False, 1, user=True), 743 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True), 744 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 745 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 746 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 747 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 748 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 749 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 750 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1), 751 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1), 752 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 753 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1), 754 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 755 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 756 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1) 757 } 758 decode_block = decode % substDict 759}}; 760 761def format LoadHalfwordMemoryHints() {{ 762 decode = ''' 763 { 764 const uint32_t op1 = bits(machInst, 24, 23); 765 const uint32_t op2 = bits(machInst, 11, 6); 766 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 767 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 768 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 769 const uint32_t imm12 = bits(machInst, 11, 0); 770 const uint32_t imm8 = bits(machInst, 7, 0); 771 bool pldw = bits(machInst, 21); 772 const uint32_t imm2 = bits(machInst, 5, 4); 773 if (rn == 0xf) { 774 if (rt == 0xf) { 775 if (bits(op1, 1) == 1) { 776 // Unallocated memory hint 777 return new NopInst(machInst); 778 } else { 779 return new Unknown(machInst); 780 } 781 } else { 782 if (bits(op1, 1) == 1) { 783 if (bits(machInst, 23)) { 784 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC, 785 true, imm12); 786 } else { 787 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC, 788 false, imm12); 789 } 790 } else { 791 if (bits(machInst, 23)) { 792 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC, 793 true, imm12); 794 } else { 795 return new %(ldrh_lit)s(machInst, rt, INTREG_PC, 796 false, imm12); 797 } 798 } 799 } 800 } else if (rt == 0xf) { 801 switch (op1) { 802 case 0x0: 803 if (op2 == 0x0) { 804 if (pldw) { 805 return new %(pldw_radd)s(machInst, INTREG_ZERO, 806 rn, true, imm2, LSL, rm); 807 } else { 808 return new %(pld_radd)s(machInst, INTREG_ZERO, 809 rn, true, imm2, LSL, rm); 810 } 811 } else if (bits(op2, 5, 2) == 0xc) { 812 if (pldw) { 813 return new %(pldw_isub)s(machInst, INTREG_ZERO, 814 rn, false, imm8); 815 } else { 816 return new %(pld_isub)s(machInst, INTREG_ZERO, 817 rn, false, imm8); 818 } 819 } 820 break; 821 case 0x1: 822 if (pldw) { 823 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 824 rn, true, imm12); 825 } else { 826 return new %(pld_iadd)s(machInst, INTREG_ZERO, 827 rn, true, imm12); 828 } 829 case 0x2: 830 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) { 831 // Unallocated memory hint 832 return new NopInst(machInst); 833 } 834 break; 835 case 0x3: 836 return new NopInst(machInst); 837 } 838 return new Unknown(machInst); 839 } else { 840 switch (op1) { 841 case 0x0: 842 if (op2 == 0) { 843 return new %(ldrh_radd)s(machInst, rt, rn, true, 844 imm2, LSL, rm); 845 } else if (bits(op2, 5, 2) == 0xe) { 846 return new %(ldrht)s(machInst, rt, rn, true, imm8); 847 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 848 const uint32_t puw = bits(machInst, 10, 8); 849 switch (puw) { 850 case 0x1: 851 return new %(ldrh_iw)s(machInst, rt, 852 rn, false, imm8); 853 case 0x3: 854 return new %(ldrh_iuw)s(machInst, rt, 855 rn, true, imm8); 856 case 0x4: 857 return new %(ldrh_ip)s(machInst, rt, 858 rn, false, imm8); 859 case 0x5: 860 return new %(ldrh_ipw)s(machInst, rt, 861 rn, false, imm8); 862 case 0x7: 863 return new %(ldrh_ipuw)s(machInst, rt, 864 rn, true, imm8); 865 } 866 } 867 break; 868 case 0x1: 869 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12); 870 case 0x2: 871 if (op2 == 0) { 872 return new %(ldrsh_radd)s(machInst, rt, rn, true, 873 imm2, LSL, rm); 874 } else if (bits(op2, 5, 2) == 0xe) { 875 return new %(ldrsht)s(machInst, rt, rn, true, imm8); 876 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 877 const uint32_t puw = bits(machInst, 10, 8); 878 switch (puw) { 879 case 0x1: 880 return new %(ldrsh_iw)s(machInst, rt, 881 rn, false, imm8); 882 case 0x3: 883 return new %(ldrsh_iuw)s(machInst, rt, 884 rn, true, imm8); 885 case 0x4: 886 return new %(ldrsh_ip)s(machInst, rt, 887 rn, false, imm8); 888 case 0x5: 889 return new %(ldrsh_ipw)s(machInst, rt, 890 rn, false, imm8); 891 case 0x7: 892 return new %(ldrsh_ipuw)s(machInst, rt, 893 rn, true, imm8); 894 } 895 } 896 break; 897 case 0x3: 898 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12); 899 } 900 return new Unknown(machInst); 901 } 902 } 903 ''' 904 substDict = { 905 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True), 906 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True), 907 "ldrh_lit_u" : loadImmClassName(False, True, False, 2), 908 "ldrh_lit" : loadImmClassName(False, False, False, 2), 909 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True), 910 "ldrh_radd" : loadRegClassName(False, True, False, 2), 911 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True), 912 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True), 913 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True), 914 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True), 915 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True), 916 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True), 917 "ldrh_iw" : loadImmClassName(True, False, True, 2), 918 "ldrh_iuw" : loadImmClassName(True, True, True, 2), 919 "ldrh_ip" : loadImmClassName(False, False, False, 2), 920 "ldrh_ipw" : loadImmClassName(False, False, True, 2), 921 "ldrh_ipuw" : loadImmClassName(False, True, True, 2), 922 "ldrh_iadd" : loadImmClassName(False, True, False, 2), 923 "ldrht" : loadImmClassName(False, True, False, 2, user=True), 924 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True), 925 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 926 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 927 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 928 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 929 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 930 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1) 931 } 932 decode_block = decode % substDict 933}}; 934 935def format Thumb16MemReg() {{ 936 decode = ''' 937 { 938 const uint32_t opb = bits(machInst, 11, 9); 939 const uint32_t rt = bits(machInst, 2, 0); 940 const uint32_t rn = bits(machInst, 5, 3); 941 const uint32_t rm = bits(machInst, 8, 6); 942 switch (opb) { 943 case 0x0: 944 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm); 945 case 0x1: 946 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm); 947 case 0x2: 948 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm); 949 case 0x3: 950 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm); 951 case 0x4: 952 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm); 953 case 0x5: 954 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm); 955 case 0x6: 956 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm); 957 case 0x7: 958 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm); 959 } 960 } 961 ''' 962 classNames = { 963 "str" : storeRegClassName(False, True, False), 964 "strh" : storeRegClassName(False, True, False, size=2), 965 "strb" : storeRegClassName(False, True, False, size=1), 966 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1), 967 "ldr" : loadRegClassName(False, True, False), 968 "ldrh" : loadRegClassName(False, True, False, size=2), 969 "ldrb" : loadRegClassName(False, True, False, size=1), 970 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), 971 } 972 decode_block = decode % classNames 973}}; 974 975def format Thumb16MemImm() {{ 976 decode = ''' 977 { 978 const uint32_t opa = bits(machInst, 15, 12); 979 const uint32_t opb = bits(machInst, 11, 9); 980 const uint32_t lrt = bits(machInst, 2, 0); 981 const uint32_t lrn = bits(machInst, 5, 3); 982 const uint32_t hrt = bits(machInst, 10, 8); 983 const uint32_t imm5 = bits(machInst, 10, 6); 984 const uint32_t imm8 = bits(machInst, 7, 0); 985 const bool load = bits(opb, 2); 986 switch (opa) { 987 case 0x6: 988 if (load) { 989 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2); 990 } else { 991 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2); 992 } 993 case 0x7: 994 if (load) { 995 return new %(ldrb)s(machInst, lrt, lrn, true, imm5); 996 } else { 997 return new %(strb)s(machInst, lrt, lrn, true, imm5); 998 } 999 case 0x8: 1000 if (load) { 1001 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1); 1002 } else { 1003 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1); 1004 } 1005 case 0x9: 1006 if (load) { 1007 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1008 } else { 1009 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1010 } 1011 default: 1012 return new Unknown(machInst); 1013 } 1014 } 1015 ''' 1016 classNames = { 1017 "ldr" : loadImmClassName(False, True, False), 1018 "str" : storeImmClassName(False, True, False), 1019 "ldrh" : loadImmClassName(False, True, False, size=2), 1020 "strh" : storeImmClassName(False, True, False, size=2), 1021 "ldrb" : loadImmClassName(False, True, False, size=1), 1022 "strb" : storeImmClassName(False, True, False, size=1), 1023 } 1024 decode_block = decode % classNames 1025}}; 1026 1027def format Thumb16MemLit() {{ 1028 decode_block = ''' 1029 { 1030 const uint32_t rt = bits(machInst, 10, 8); 1031 const uint32_t imm8 = bits(machInst, 7, 0); 1032 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2); 1033 } 1034 ''' % loadImmClassName(False, True, False) 1035}}; 1036 1037