mem.isa revision 7293:a907ebdb7ee9
111723Sar4jc@virginia.edu// -*- mode:c++ -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu// Copyright (c) 2010 ARM Limited 411723Sar4jc@virginia.edu// All rights reserved 511723Sar4jc@virginia.edu// 611723Sar4jc@virginia.edu// The license below extends only to copyright in the software and shall 711723Sar4jc@virginia.edu// not be construed as granting a license to any other intellectual 811723Sar4jc@virginia.edu// property including but not limited to intellectual property relating 911723Sar4jc@virginia.edu// to a hardware implementation of the functionality of the software 1011723Sar4jc@virginia.edu// licensed hereunder. You may use the software subject to the license 1111723Sar4jc@virginia.edu// terms below provided that you ensure that this notice is replicated 1211723Sar4jc@virginia.edu// unmodified and in its entirety in all distributions of the software, 1311723Sar4jc@virginia.edu// modified or unmodified, in source code or in binary form. 1411723Sar4jc@virginia.edu// 1511723Sar4jc@virginia.edu// Copyright (c) 2007-2008 The Florida State University 1611723Sar4jc@virginia.edu// All rights reserved. 1711723Sar4jc@virginia.edu// 1811723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 1911723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 2011723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 2111723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 2211723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 2311723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 2411723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 2511723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 2611723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 2711723Sar4jc@virginia.edu// this software without specific prior written permission. 2811723Sar4jc@virginia.edu// 2911723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212808Srobert.scheffel1@tu-dresden.de// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011723Sar4jc@virginia.edu// 4111723Sar4jc@virginia.edu// Authors: Gabe Black 4211723Sar4jc@virginia.edu 4311723Sar4jc@virginia.edudef format AddrMode2(imm) {{ 4411723Sar4jc@virginia.edu if eval(imm): 4511723Sar4jc@virginia.edu imm = True 4611723Sar4jc@virginia.edu else: 4711723Sar4jc@virginia.edu imm = False 4812808Srobert.scheffel1@tu-dresden.de 4912808Srobert.scheffel1@tu-dresden.de def buildPUBWLCase(p, u, b, w, l): 5012808Srobert.scheffel1@tu-dresden.de return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0) 5112808Srobert.scheffel1@tu-dresden.de 5211723Sar4jc@virginia.edu header_output = decoder_output = exec_output = "" 5311723Sar4jc@virginia.edu decode_block = "switch(PUBWL) {\n" 5411723Sar4jc@virginia.edu 5511723Sar4jc@virginia.edu # Loop over all the values of p, u, b, w and l and build instructions and 5611723Sar4jc@virginia.edu # a decode block for them. 5711723Sar4jc@virginia.edu for p in (0, 1): 5811723Sar4jc@virginia.edu for u in (0, 1): 5911723Sar4jc@virginia.edu for b in (0, 1): 6011723Sar4jc@virginia.edu for w in (0, 1): 6111723Sar4jc@virginia.edu post = (p == 0) 6211723Sar4jc@virginia.edu user = (p == 0 and w == 1) 6311723Sar4jc@virginia.edu writeback = (p == 0 or w == 1) 6411723Sar4jc@virginia.edu add = (u == 1) 6511723Sar4jc@virginia.edu if b == 0: 6611723Sar4jc@virginia.edu size = 4 6711723Sar4jc@virginia.edu else: 6811723Sar4jc@virginia.edu size = 1 6911723Sar4jc@virginia.edu if add: 7011723Sar4jc@virginia.edu addStr = "true" 7111723Sar4jc@virginia.edu else: 7211723Sar4jc@virginia.edu addStr = "false" 7311723Sar4jc@virginia.edu if imm: 7411723Sar4jc@virginia.edu newDecode = "return new %s(machInst, RD, RN," + \ 7511723Sar4jc@virginia.edu "%s, machInst.immed11_0);" 7611723Sar4jc@virginia.edu loadClass = loadImmClassName(post, add, writeback, 7711723Sar4jc@virginia.edu size, False, user) 7811723Sar4jc@virginia.edu storeClass = storeImmClassName(post, add, writeback, 7911723Sar4jc@virginia.edu size, False, user) 8011723Sar4jc@virginia.edu loadDecode = newDecode % (loadClass, addStr) 81 storeDecode = newDecode % (storeClass, addStr) 82 else: 83 newDecode = "return new %s(machInst, RD, RN, %s," + \ 84 "machInst.shiftSize," + \ 85 "machInst.shift, RM);" 86 loadClass = loadRegClassName(post, add, writeback, 87 size, False, user) 88 storeClass = storeRegClassName(post, add, writeback, 89 size, False, user) 90 loadDecode = newDecode % (loadClass, addStr) 91 storeDecode = newDecode % (storeClass, addStr) 92 decode = ''' 93 case %#x: 94 {%s} 95 break; 96 ''' 97 decode_block += decode % \ 98 (buildPUBWLCase(p,u,b,w,1), loadDecode) 99 decode_block += decode % \ 100 (buildPUBWLCase(p,u,b,w,0), storeDecode) 101 decode_block += ''' 102 default: 103 return new Unknown(machInst); 104 break; 105 }''' 106}}; 107 108def format AddrMode3() {{ 109 decode = ''' 110 { 111 const uint32_t op1 = bits(machInst, 24, 20); 112 const uint32_t op2 = bits(machInst, 6, 5); 113 const uint32_t puiw = bits(machInst, 24, 21); 114 const uint32_t imm = IMMED_HI_11_8 << 4 | IMMED_LO_3_0; 115 switch (op2) { 116 case 0x1: 117 if (op1 & 0x1) { 118 %(ldrh)s 119 } else { 120 %(strh)s 121 } 122 case 0x2: 123 if (op1 & 0x1) { 124 %(ldrsb)s 125 } else { 126 %(ldrd)s 127 } 128 case 0x3: 129 if (op1 & 0x1) { 130 %(ldrsh)s 131 } else { 132 %(strd)s 133 } 134 default: 135 return new Unknown(machInst); 136 } 137 } 138 ''' 139 140 def decodePuiwCase(load, d, p, u, i, w, size=4, sign=False): 141 post = (p == 0) 142 user = (p == 0 and w == 1) 143 writeback = (p == 0 or w == 1) 144 add = (u == 1) 145 caseVal = (p << 3) + (u << 2) + (i << 1) + (w << 0) 146 decode = ''' 147 case %#x: 148 return new '''% caseVal 149 if add: 150 addStr = "true" 151 else: 152 addStr = "false" 153 if d: 154 dests = "RT & ~1, RT | 1" 155 else: 156 dests = "RT" 157 if i: 158 if load: 159 if d: 160 className = loadDoubleImmClassName(post, add, writeback) 161 else: 162 className = loadImmClassName(post, add, writeback, \ 163 size=size, sign=sign, \ 164 user=user) 165 else: 166 if d: 167 className = storeDoubleImmClassName(post, add, writeback) 168 else: 169 className = storeImmClassName(post, add, writeback, \ 170 size=size, sign=sign, \ 171 user=user) 172 decode += ("%s(machInst, %s, RN, %s, imm);\n" % \ 173 (className, dests, addStr)) 174 else: 175 if load: 176 if d: 177 className = loadDoubleRegClassName(post, add, writeback) 178 else: 179 className = loadRegClassName(post, add, writeback, \ 180 size=size, sign=sign, \ 181 user=user) 182 else: 183 if d: 184 className = storeDoubleRegClassName(post, add, writeback) 185 else: 186 className = storeRegClassName(post, add, writeback, \ 187 size=size, sign=sign, \ 188 user=user) 189 decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \ 190 (className, dests, addStr)) 191 return decode 192 193 def decodePuiw(load, d, size=4, sign=False): 194 global decodePuiwCase 195 decode = "switch (puiw) {\n" 196 for p in (0, 1): 197 for u in (0, 1): 198 for i in (0, 1): 199 for w in (0, 1): 200 decode += decodePuiwCase(load, d, p, u, i, w, 201 size, sign) 202 decode += ''' 203 default: 204 return new Unknown(machInst); 205 } 206 ''' 207 return decode 208 209 subs = { 210 "ldrh" : decodePuiw(True, False, size=2), 211 "strh" : decodePuiw(False, False, size=2), 212 "ldrsb" : decodePuiw(True, False, size=1, sign=True), 213 "ldrd" : decodePuiw(True, True), 214 "ldrsh" : decodePuiw(True, False, size=2, sign=True), 215 "strd" : decodePuiw(False, True) 216 } 217 decode_block = decode % subs 218}}; 219 220def format ArmSyncMem() {{ 221 decode_block = ''' 222 { 223 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 224 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 225 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 226 switch (PUBWL) { 227 case 0x10: 228 return new Swp(machInst, rt, rt2, rn); 229 case 0x14: 230 return new Swpb(machInst, rt, rt2, rn); 231 case 0x18: 232 return new WarnUnimplemented("strex", machInst); 233 case 0x19: 234 return new %(ldrex)s(machInst, rt, rn, true, 0); 235 case 0x1a: 236 return new WarnUnimplemented("strexd", machInst); 237 case 0x1b: 238 return new WarnUnimplemented("ldrexd", machInst); 239 case 0x1c: 240 return new WarnUnimplemented("strexb", machInst); 241 case 0x1d: 242 return new %(ldrexb)s(machInst, rt, rn, true, 0); 243 case 0x1e: 244 return new WarnUnimplemented("strexh", machInst); 245 case 0x1f: 246 return new %(ldrexh)s(machInst, rt, rn, true, 0); 247 default: 248 return new Unknown(machInst); 249 } 250 } 251 ''' % { 252 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 253 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 254 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2) 255 } 256}}; 257 258def format Thumb32SrsRfe() {{ 259 decode_block = ''' 260 { 261 if (bits(machInst, 20) == 1) { 262 const bool add = (bits(machInst, 24, 23) == 0x3); 263 // post == add 264 const bool wb = (bits(machInst, 21) == 1); 265 const IntRegIndex rn = 266 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 267 if (!add && !wb) { 268 return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb); 269 } else if (add && !wb) { 270 return new %(rfe_u)s(machInst, rn, RfeOp::IncrementAfter, wb); 271 } else if (!add && wb) { 272 return new %(rfe_w)s(machInst, rn, RfeOp::DecrementBefore, wb); 273 } else { 274 return new %(rfe_uw)s(machInst, rn, RfeOp::IncrementAfter, wb); 275 } 276 } else { 277 return new WarnUnimplemented("srs", machInst); 278 } 279 } 280 ''' % { 281 "rfe" : "RFE_" + loadImmClassName(False, False, False, 8), 282 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8), 283 "rfe_w" : "RFE_" + loadImmClassName(False, False, True, 8), 284 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8) 285 } 286}}; 287 288def format Thumb32LdrStrDExTbh() {{ 289 decode_block = ''' 290 { 291 const uint32_t op1 = bits(machInst, 24, 23); 292 const uint32_t op2 = bits(machInst, 21, 20); 293 const uint32_t op3 = bits(machInst, 7, 4); 294 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 295 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 296 const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 297 const uint32_t imm8 = bits(machInst, 7, 0); 298 if (bits(op1, 1) == 0 && bits(op2, 1) == 0) { 299 if (op1 == 0) { 300 const uint32_t imm = bits(machInst, 7, 0) << 2; 301 if (op2 == 0) { 302 return new WarnUnimplemented("strex", machInst); 303 } else { 304 return new %(ldrex)s(machInst, rt, rn, true, imm); 305 } 306 } else { 307 if (op2 == 0) { 308 switch (op3) { 309 case 0x4: 310 return new WarnUnimplemented("strexb", machInst); 311 case 0x5: 312 return new WarnUnimplemented("strexh", machInst); 313 case 0x7: 314 return new WarnUnimplemented("strexd", machInst); 315 default: 316 return new Unknown(machInst); 317 } 318 } else { 319 switch (op3) { 320 case 0x0: 321 return new WarnUnimplemented("tbb", machInst); 322 case 0x1: 323 return new WarnUnimplemented("tbh", machInst); 324 case 0x4: 325 return new %(ldrexb)s(machInst, rt, rn, true, 0); 326 case 0x5: 327 return new %(ldrexh)s(machInst, rt, rn, true, 0); 328 case 0x7: 329 return new %(ldrexd)s(machInst, rt, rt2, rn, true, 0); 330 default: 331 return new Unknown(machInst); 332 } 333 } 334 } 335 } else { 336 const uint32_t puw = (bits(machInst, 24, 23) << 1) | 337 bits(machInst, 21); 338 const uint32_t dimm = imm8 << 2; 339 if (bits(op2, 0) == 0) { 340 switch (puw) { 341 case 0x1: 342 return new %(strd_w)s(machInst, rt, rt2, rn, false, dimm); 343 case 0x3: 344 return new %(strd_uw)s(machInst, rt, rt2, rn, true, dimm); 345 case 0x4: 346 return new %(strd_p)s(machInst, rt, rt2, rn, false, dimm); 347 case 0x5: 348 return new %(strd_pw)s(machInst, rt, rt2, rn, false, dimm); 349 case 0x6: 350 return new %(strd_pu)s(machInst, rt, rt2, rn, true, dimm); 351 case 0x7: 352 return new %(strd_puw)s(machInst, rt, rt2, rn, true, dimm); 353 default: 354 return new Unknown(machInst); 355 } 356 } else { 357 switch (puw) { 358 case 0x1: 359 return new %(ldrd_w)s(machInst, rt, rt2, rn, false, dimm); 360 case 0x3: 361 return new %(ldrd_uw)s(machInst, rt, rt2, rn, true, dimm); 362 case 0x4: 363 return new %(ldrd_p)s(machInst, rt, rt2, rn, false, dimm); 364 case 0x5: 365 return new %(ldrd_pw)s(machInst, rt, rt2, rn, false, dimm); 366 case 0x6: 367 return new %(ldrd_pu)s(machInst, rt, rt2, rn, true, dimm); 368 case 0x7: 369 return new %(ldrd_puw)s(machInst, rt, rt2, rn, true, dimm); 370 default: 371 return new Unknown(machInst); 372 } 373 } 374 } 375 } 376 ''' % { 377 "ldrex" : "LDREX_" + loadImmClassName(False, True, False, size=4), 378 "ldrexb" : "LDREXB_" + loadImmClassName(False, True, False, size=1), 379 "ldrexh" : "LDREXH_" + loadImmClassName(False, True, False, size=2), 380 "ldrexd" : "LDREXD_" + loadDoubleImmClassName(False, True, False), 381 "ldrd_w" : loadDoubleImmClassName(True, False, True), 382 "ldrd_uw" : loadDoubleImmClassName(True, True, True), 383 "ldrd_p" : loadDoubleImmClassName(False, False, False), 384 "ldrd_pw" : loadDoubleImmClassName(False, False, True), 385 "ldrd_pu" : loadDoubleImmClassName(False, True, False), 386 "ldrd_puw" : loadDoubleImmClassName(False, True, True), 387 "strd_w" : storeDoubleImmClassName(True, False, True), 388 "strd_uw" : storeDoubleImmClassName(True, True, True), 389 "strd_p" : storeDoubleImmClassName(False, False, False), 390 "strd_pw" : storeDoubleImmClassName(False, False, True), 391 "strd_pu" : storeDoubleImmClassName(False, True, False), 392 "strd_puw" : storeDoubleImmClassName(False, True, True) 393 } 394}}; 395 396def format Thumb32LoadWord() {{ 397 decode = ''' 398 { 399 uint32_t op1 = bits(machInst, 24, 23); 400 if (bits(op1, 1) == 0) { 401 uint32_t op2 = bits(machInst, 11, 6); 402 if (HTRN == 0xF) { 403 if (UP) { 404 return new %(literal_u)s(machInst, RT, INTREG_PC, 405 true, IMMED_11_0); 406 } else { 407 return new %(literal)s(machInst, RT, INTREG_PC, 408 false, IMMED_11_0); 409 } 410 } else if (op1 == 0x1) { 411 return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0); 412 } else if (op2 == 0) { 413 return new %(register)s(machInst, RT, RN, UP, 414 bits(machInst, 5, 4), LSL, RM); 415 } else if ((op2 & 0x3c) == 0x38) { 416 return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0); 417 } else if ((op2 & 0x3c) == 0x30 || //P 418 (op2 & 0x24) == 0x24) { //W 419 uint32_t puw = bits(machInst, 10, 8); 420 uint32_t imm = IMMED_7_0; 421 switch (puw) { 422 case 0: 423 case 2: 424 // If we're here, either P or W must have been set. 425 panic("Neither P or W set, but that " 426 "shouldn't be possible.\\n"); 427 case 1: 428 return new %(imm_w)s(machInst, RT, RN, false, imm); 429 case 3: 430 return new %(imm_uw)s(machInst, RT, RN, true, imm); 431 case 4: 432 return new %(imm_p)s(machInst, RT, RN, false, imm); 433 case 5: 434 return new %(imm_pw)s(machInst, RT, RN, false, imm); 435 case 6: 436 return new %(imm_pu)s(machInst, RT, RN, true, imm); 437 case 7: 438 return new %(imm_puw)s(machInst, RT, RN, true, imm); 439 } 440 } 441 } else { 442 return new Unknown(machInst); 443 } 444 } 445 ''' 446 classNames = { 447 "literal_u" : loadImmClassName(False, True, False), 448 "literal" : loadImmClassName(False, False, False), 449 "register" : loadRegClassName(False, True, False), 450 "ldrt" : loadImmClassName(False, True, False, user=True), 451 "imm_w" : loadImmClassName(True, False, True), 452 "imm_uw" : loadImmClassName(True, True, True), 453 "imm_p" : loadImmClassName(False, False, False), 454 "imm_pw" : loadImmClassName(False, False, True), 455 "imm_pu" : loadImmClassName(False, True, False), 456 "imm_puw" : loadImmClassName(False, True, True) 457 } 458 decode_block = decode % classNames 459}}; 460 461def format Thumb32StoreSingle() {{ 462 def buildPuwDecode(size): 463 puwDecode = ''' 464 { 465 uint32_t puw = bits(machInst, 10, 8); 466 uint32_t imm = IMMED_7_0; 467 switch (puw) { 468 case 0: 469 case 2: 470 // If we're here, either P or W must have been set. 471 panic("Neither P or W set, but that " 472 "shouldn't be possible.\\n"); 473 case 1: 474 return new %(imm_w)s(machInst, RT, RN, false, imm); 475 case 3: 476 return new %(imm_uw)s(machInst, RT, RN, true, imm); 477 case 4: 478 return new %(imm_p)s(machInst, RT, RN, false, imm); 479 case 5: 480 return new %(imm_pw)s(machInst, RT, RN, false, imm); 481 case 6: 482 return new %(imm_pu)s(machInst, RT, RN, true, imm); 483 case 7: 484 return new %(imm_puw)s(machInst, RT, RN, true, imm); 485 } 486 } 487 ''' 488 return puwDecode % { 489 "imm_w" : storeImmClassName(True, False, True, size=size), 490 "imm_uw" : storeImmClassName(True, True, True, size=size), 491 "imm_p" : storeImmClassName(False, False, False, size=size), 492 "imm_pw" : storeImmClassName(False, False, True, size=size), 493 "imm_pu" : storeImmClassName(False, True, False, size=size), 494 "imm_puw" : storeImmClassName(False, True, True, size=size) 495 } 496 decode = ''' 497 { 498 uint32_t op1 = bits(machInst, 23, 21); 499 uint32_t op2 = bits(machInst, 11, 6); 500 bool op2Puw = ((op2 & 0x24) == 0x24 || 501 (op2 & 0x3c) == 0x30); 502 if (RN == 0xf) { 503 return new Unknown(machInst); 504 } 505 if (op1 == 4) { 506 return new %(strb_imm)s(machInst, RT, RN, true, IMMED_11_0); 507 } else if (op1 == 0 && op2Puw) { 508 %(strb_puw)s; 509 } else if (op1 == 0 && ((op2 & 0x3c) == 0x38)) { 510 return new %(strbt)s(machInst, RT, RN, true, IMMED_7_0); 511 } else if (op1 == 0 && op2 == 0) { 512 return new %(strb_reg)s(machInst, RT, RN, true, 513 bits(machInst, 5, 4), LSL, RM); 514 } else if (op1 == 5) { 515 return new %(strh_imm)s(machInst, RT, RN, true, IMMED_11_0); 516 } else if (op1 == 1 && op2Puw) { 517 %(strh_puw)s; 518 } else if (op1 == 1 && ((op2 & 0x3c) == 0x38)) { 519 return new %(strht)s(machInst, RT, RN, true, IMMED_7_0); 520 } else if (op1 == 1 && op2 == 0) { 521 return new %(strh_reg)s(machInst, RT, RN, true, 522 bits(machInst, 5, 4), LSL, RM); 523 } else if (op1 == 6) { 524 return new %(str_imm)s(machInst, RT, RN, true, IMMED_11_0); 525 } else if (op1 == 2 && op2Puw) { 526 %(str_puw)s; 527 } else if (op1 == 2 && ((op2 & 0x3c) == 0x38)) { 528 return new %(strt)s(machInst, RT, RN, true, IMMED_7_0); 529 } else if (op1 == 2 && op2 == 0) { 530 return new %(str_reg)s(machInst, RT, RN, true, 531 bits(machInst, 5, 4), LSL, RM); 532 } else { 533 return new Unknown(machInst); 534 } 535 } 536 ''' 537 classNames = { 538 "strb_imm" : storeImmClassName(False, True, False, size=1), 539 "strb_puw" : buildPuwDecode(1), 540 "strbt" : storeImmClassName(False, True, False, user=True, size=1), 541 "strb_reg" : storeRegClassName(False, True, False, size=1), 542 "strh_imm" : storeImmClassName(False, True, False, size=2), 543 "strh_puw" : buildPuwDecode(2), 544 "strht" : storeImmClassName(False, True, False, user=True, size=2), 545 "strh_reg" : storeRegClassName(False, True, False, size=2), 546 "str_imm" : storeImmClassName(False, True, False), 547 "str_puw" : buildPuwDecode(4), 548 "strt" : storeImmClassName(False, True, False, user=True), 549 "str_reg" : storeRegClassName(False, True, False) 550 } 551 decode_block = decode % classNames 552}}; 553 554def format LoadByteMemoryHints() {{ 555 decode = ''' 556 { 557 const uint32_t op1 = bits(machInst, 24, 23); 558 const uint32_t op2 = bits(machInst, 11, 6); 559 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 560 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 561 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 562 const uint32_t imm12 = bits(machInst, 11, 0); 563 const uint32_t imm8 = bits(machInst, 7, 0); 564 bool pldw = bits(machInst, 21); 565 const uint32_t imm2 = bits(machInst, 5, 4); 566 if (rn == 0xf) { 567 if (rt == 0xf) { 568 const bool add = bits(machInst, 23); 569 if (bits(op1, 1) == 1) { 570 if (add) { 571 return new %(pli_iulit)s(machInst, INTREG_ZERO, 572 INTREG_PC, true, imm12); 573 } else { 574 return new %(pli_ilit)s(machInst, INTREG_ZERO, 575 INTREG_PC, false, imm12); 576 } 577 } else { 578 if (add) { 579 return new %(pld_iulit)s(machInst, INTREG_ZERO, 580 INTREG_PC, true, imm12); 581 } else { 582 return new %(pld_ilit)s(machInst, INTREG_ZERO, 583 INTREG_PC, false, imm12); 584 } 585 } 586 } else { 587 if (bits(op1, 1) == 1) { 588 if (bits(machInst, 23)) { 589 return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC, 590 true, imm12); 591 } else { 592 return new %(ldrsb_lit)s(machInst, rt, INTREG_PC, 593 false, imm12); 594 } 595 } else { 596 if (bits(machInst, 23)) { 597 return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC, 598 true, imm12); 599 } else { 600 return new %(ldrb_lit)s(machInst, rt, INTREG_PC, 601 false, imm12); 602 } 603 } 604 } 605 } else if (rt == 0xf) { 606 switch (op1) { 607 case 0x0: 608 if (op2 == 0x0) { 609 if (pldw) { 610 return new %(pldw_radd)s(machInst, INTREG_ZERO, 611 rn, true, imm2, LSL, rm); 612 } else { 613 return new %(pld_radd)s(machInst, INTREG_ZERO, 614 rn, true, imm2, LSL, rm); 615 } 616 } else if (bits(op2, 5, 2) == 0xc) { 617 if (pldw) { 618 return new %(pldw_isub)s(machInst, INTREG_ZERO, 619 rn, false, imm8); 620 } else { 621 return new %(pld_isub)s(machInst, INTREG_ZERO, 622 rn, false, imm8); 623 } 624 } 625 break; 626 case 0x1: 627 if (pldw) { 628 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 629 rn, true, imm12); 630 } else { 631 return new %(pld_iadd)s(machInst, INTREG_ZERO, 632 rn, true, imm12); 633 } 634 case 0x2: 635 if (op2 == 0x0) { 636 return new %(pli_radd)s(machInst, INTREG_ZERO, rn, 637 true, imm2, LSL, rm); 638 } else if (bits(op2, 5, 2) == 0xc) { 639 return new %(pli_ilit)s(machInst, INTREG_ZERO, 640 INTREG_PC, false, imm8); 641 } 642 break; 643 case 0x3: 644 return new %(pli_iulit)s(machInst, INTREG_ZERO, 645 INTREG_PC, true, imm12); 646 } 647 return new Unknown(machInst); 648 } else { 649 switch (op1) { 650 case 0x0: 651 if (op2 == 0) { 652 return new %(ldrb_radd)s(machInst, rt, rn, true, 653 imm2, LSL, rm); 654 } else if (bits(op2, 5, 2) == 0xe) { 655 return new %(ldrbt)s(machInst, rt, rn, true, imm8); 656 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 657 const uint32_t puw = bits(machInst, 10, 8); 658 switch (puw) { 659 case 0x1: 660 return new %(ldrb_iw)s(machInst, rt, 661 rn, false, imm8); 662 case 0x3: 663 return new %(ldrb_iuw)s(machInst, rt, 664 rn, true, imm8); 665 case 0x4: 666 return new %(ldrb_ip)s(machInst, rt, 667 rn, false, imm8); 668 case 0x5: 669 return new %(ldrb_ipw)s(machInst, rt, 670 rn, false, imm8); 671 case 0x7: 672 return new %(ldrb_ipuw)s(machInst, rt, 673 rn, true, imm8); 674 } 675 } 676 break; 677 case 0x1: 678 return new %(ldrb_iadd)s(machInst, rt, rn, true, imm12); 679 case 0x2: 680 if (op2 == 0) { 681 return new %(ldrsb_radd)s(machInst, rt, rn, true, 682 imm2, LSL, rm); 683 } else if (bits(op2, 5, 2) == 0xe) { 684 return new %(ldrsbt)s(machInst, rt, rn, true, imm8); 685 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 686 const uint32_t puw = bits(machInst, 10, 8); 687 switch (puw) { 688 case 0x1: 689 return new %(ldrsb_iw)s(machInst, rt, 690 rn, false, imm8); 691 case 0x3: 692 return new %(ldrsb_iuw)s(machInst, rt, 693 rn, true, imm8); 694 case 0x4: 695 return new %(ldrsb_ip)s(machInst, rt, 696 rn, false, imm8); 697 case 0x5: 698 return new %(ldrsb_ipw)s(machInst, rt, 699 rn, false, imm8); 700 case 0x7: 701 return new %(ldrsb_ipuw)s(machInst, rt, 702 rn, true, imm8); 703 } 704 } 705 break; 706 case 0x3: 707 return new %(ldrsb_iadd)s(machInst, rt, rn, true, imm12); 708 } 709 return new Unknown(machInst); 710 } 711 } 712 ''' 713 substDict = { 714 "ldrsb_lit_u" : loadImmClassName(False, True, False, 1, True), 715 "ldrsb_lit" : loadImmClassName(False, False, False, 1, True), 716 "ldrb_lit_u" : loadImmClassName(False, True, False, 1), 717 "ldrb_lit" : loadImmClassName(False, False, False, 1), 718 "ldrsb_radd" : loadRegClassName(False, True, False, 1, True), 719 "ldrb_radd" : loadRegClassName(False, True, False, 1), 720 "ldrsb_iw" : loadImmClassName(True, False, True, 1, True), 721 "ldrsb_iuw" : loadImmClassName(True, True, True, 1, True), 722 "ldrsb_ip" : loadImmClassName(False, False, False, 1, True), 723 "ldrsb_ipw" : loadImmClassName(False, False, True, 1, True), 724 "ldrsb_ipuw" : loadImmClassName(False, True, True, 1, True), 725 "ldrsb_iadd" : loadImmClassName(False, True, False, 1, True), 726 "ldrb_iw" : loadImmClassName(True, False, True, 1), 727 "ldrb_iuw" : loadImmClassName(True, True, True, 1), 728 "ldrb_ip" : loadImmClassName(False, False, False, 1), 729 "ldrb_ipw" : loadImmClassName(False, False, True, 1), 730 "ldrb_ipuw" : loadImmClassName(False, True, True, 1), 731 "ldrb_iadd" : loadImmClassName(False, True, False, 1), 732 "ldrbt" : loadImmClassName(False, True, False, 1, user=True), 733 "ldrsbt" : loadImmClassName(False, True, False, 1, True, user=True), 734 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 735 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 736 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 737 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 738 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 739 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1), 740 "pld_iulit" : "PLD_" + loadImmClassName(False, True, False, 1), 741 "pld_ilit" : "PLD_" + loadImmClassName(False, False, False, 1), 742 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 743 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1), 744 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1), 745 "pli_iulit" : "PLI_" + loadImmClassName(False, True, False, 1), 746 "pli_ilit" : "PLI_" + loadImmClassName(False, False, False, 1) 747 } 748 decode_block = decode % substDict 749}}; 750 751def format LoadHalfwordMemoryHints() {{ 752 decode = ''' 753 { 754 const uint32_t op1 = bits(machInst, 24, 23); 755 const uint32_t op2 = bits(machInst, 11, 6); 756 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 757 const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 758 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 759 const uint32_t imm12 = bits(machInst, 11, 0); 760 const uint32_t imm8 = bits(machInst, 7, 0); 761 bool pldw = bits(machInst, 21); 762 const uint32_t imm2 = bits(machInst, 5, 4); 763 if (rn == 0xf) { 764 if (rt == 0xf) { 765 if (bits(op1, 1) == 1) { 766 // Unallocated memory hint 767 return new NopInst(machInst); 768 } else { 769 return new Unknown(machInst); 770 } 771 } else { 772 if (bits(op1, 1) == 1) { 773 if (bits(machInst, 23)) { 774 return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC, 775 true, imm12); 776 } else { 777 return new %(ldrsh_lit)s(machInst, rt, INTREG_PC, 778 false, imm12); 779 } 780 } else { 781 if (bits(machInst, 23)) { 782 return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC, 783 true, imm12); 784 } else { 785 return new %(ldrh_lit)s(machInst, rt, INTREG_PC, 786 false, imm12); 787 } 788 } 789 } 790 } else if (rt == 0xf) { 791 switch (op1) { 792 case 0x0: 793 if (op2 == 0x0) { 794 if (pldw) { 795 return new %(pldw_radd)s(machInst, INTREG_ZERO, 796 rn, true, imm2, LSL, rm); 797 } else { 798 return new %(pld_radd)s(machInst, INTREG_ZERO, 799 rn, true, imm2, LSL, rm); 800 } 801 } else if (bits(op2, 5, 2) == 0xc) { 802 if (pldw) { 803 return new %(pldw_isub)s(machInst, INTREG_ZERO, 804 rn, false, imm8); 805 } else { 806 return new %(pld_isub)s(machInst, INTREG_ZERO, 807 rn, false, imm8); 808 } 809 } 810 break; 811 case 0x1: 812 if (pldw) { 813 return new %(pldw_iadd)s(machInst, INTREG_ZERO, 814 rn, true, imm12); 815 } else { 816 return new %(pld_iadd)s(machInst, INTREG_ZERO, 817 rn, true, imm12); 818 } 819 case 0x2: 820 if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) { 821 // Unallocated memory hint 822 return new NopInst(machInst); 823 } 824 break; 825 case 0x3: 826 return new NopInst(machInst); 827 } 828 return new Unknown(machInst); 829 } else { 830 switch (op1) { 831 case 0x0: 832 if (op2 == 0) { 833 return new %(ldrh_radd)s(machInst, rt, rn, true, 834 imm2, LSL, rm); 835 } else if (bits(op2, 5, 2) == 0xe) { 836 return new %(ldrht)s(machInst, rt, rn, true, imm8); 837 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 838 const uint32_t puw = bits(machInst, 10, 8); 839 switch (puw) { 840 case 0x1: 841 return new %(ldrh_iw)s(machInst, rt, 842 rn, false, imm8); 843 case 0x3: 844 return new %(ldrh_iuw)s(machInst, rt, 845 rn, true, imm8); 846 case 0x4: 847 return new %(ldrh_ip)s(machInst, rt, 848 rn, false, imm8); 849 case 0x5: 850 return new %(ldrh_ipw)s(machInst, rt, 851 rn, false, imm8); 852 case 0x7: 853 return new %(ldrh_ipuw)s(machInst, rt, 854 rn, true, imm8); 855 } 856 } 857 break; 858 case 0x1: 859 return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12); 860 case 0x2: 861 if (op2 == 0) { 862 return new %(ldrsh_radd)s(machInst, rt, rn, true, 863 imm2, LSL, rm); 864 } else if (bits(op2, 5, 2) == 0xe) { 865 return new %(ldrsht)s(machInst, rt, rn, true, imm8); 866 } else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) { 867 const uint32_t puw = bits(machInst, 10, 8); 868 switch (puw) { 869 case 0x1: 870 return new %(ldrsh_iw)s(machInst, rt, 871 rn, false, imm8); 872 case 0x3: 873 return new %(ldrsh_iuw)s(machInst, rt, 874 rn, true, imm8); 875 case 0x4: 876 return new %(ldrsh_ip)s(machInst, rt, 877 rn, false, imm8); 878 case 0x5: 879 return new %(ldrsh_ipw)s(machInst, rt, 880 rn, false, imm8); 881 case 0x7: 882 return new %(ldrsh_ipuw)s(machInst, rt, 883 rn, true, imm8); 884 } 885 } 886 break; 887 case 0x3: 888 return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12); 889 } 890 return new Unknown(machInst); 891 } 892 } 893 ''' 894 substDict = { 895 "ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True), 896 "ldrsh_lit" : loadImmClassName(False, False, False, 2, True), 897 "ldrh_lit_u" : loadImmClassName(False, True, False, 2), 898 "ldrh_lit" : loadImmClassName(False, False, False, 2), 899 "ldrsh_radd" : loadRegClassName(False, True, False, 2, True), 900 "ldrh_radd" : loadRegClassName(False, True, False, 2), 901 "ldrsh_iw" : loadImmClassName(True, False, True, 2, True), 902 "ldrsh_iuw" : loadImmClassName(True, True, True, 2, True), 903 "ldrsh_ip" : loadImmClassName(False, False, False, 2, True), 904 "ldrsh_ipw" : loadImmClassName(False, False, True, 2, True), 905 "ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True), 906 "ldrsh_iadd" : loadImmClassName(False, True, False, 2, True), 907 "ldrh_iw" : loadImmClassName(True, False, True, 2), 908 "ldrh_iuw" : loadImmClassName(True, True, True, 2), 909 "ldrh_ip" : loadImmClassName(False, False, False, 2), 910 "ldrh_ipw" : loadImmClassName(False, False, True, 2), 911 "ldrh_ipuw" : loadImmClassName(False, True, True, 2), 912 "ldrh_iadd" : loadImmClassName(False, True, False, 2), 913 "ldrht" : loadImmClassName(False, True, False, 2, user=True), 914 "ldrsht" : loadImmClassName(False, True, False, 2, True, user=True), 915 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1), 916 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1), 917 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1), 918 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1), 919 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1), 920 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1) 921 } 922 decode_block = decode % substDict 923}}; 924 925def format Thumb16MemReg() {{ 926 decode = ''' 927 { 928 const uint32_t opb = bits(machInst, 11, 9); 929 const uint32_t rt = bits(machInst, 2, 0); 930 const uint32_t rn = bits(machInst, 5, 3); 931 const uint32_t rm = bits(machInst, 8, 6); 932 switch (opb) { 933 case 0x0: 934 return new %(str)s(machInst, rt, rn, true, 0, LSL, rm); 935 case 0x1: 936 return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm); 937 case 0x2: 938 return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm); 939 case 0x3: 940 return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm); 941 case 0x4: 942 return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm); 943 case 0x5: 944 return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm); 945 case 0x6: 946 return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm); 947 case 0x7: 948 return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm); 949 } 950 } 951 ''' 952 classNames = { 953 "str" : storeRegClassName(False, True, False), 954 "strh" : storeRegClassName(False, True, False, size=2), 955 "strb" : storeRegClassName(False, True, False, size=1), 956 "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1), 957 "ldr" : loadRegClassName(False, True, False), 958 "ldrh" : loadRegClassName(False, True, False, size=2), 959 "ldrb" : loadRegClassName(False, True, False, size=1), 960 "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2), 961 } 962 decode_block = decode % classNames 963}}; 964 965def format Thumb16MemImm() {{ 966 decode = ''' 967 { 968 const uint32_t opa = bits(machInst, 15, 12); 969 const uint32_t opb = bits(machInst, 11, 9); 970 const uint32_t lrt = bits(machInst, 2, 0); 971 const uint32_t lrn = bits(machInst, 5, 3); 972 const uint32_t hrt = bits(machInst, 10, 8); 973 const uint32_t imm5 = bits(machInst, 10, 6); 974 const uint32_t imm8 = bits(machInst, 7, 0); 975 const bool load = bits(opb, 2); 976 switch (opa) { 977 case 0x6: 978 if (load) { 979 return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2); 980 } else { 981 return new %(str)s(machInst, lrt, lrn, true, imm5 << 2); 982 } 983 case 0x7: 984 if (load) { 985 return new %(ldrb)s(machInst, lrt, lrn, true, imm5); 986 } else { 987 return new %(strb)s(machInst, lrt, lrn, true, imm5); 988 } 989 case 0x8: 990 if (load) { 991 return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1); 992 } else { 993 return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1); 994 } 995 case 0x9: 996 if (load) { 997 return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 998 } else { 999 return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2); 1000 } 1001 default: 1002 return new Unknown(machInst); 1003 } 1004 } 1005 ''' 1006 classNames = { 1007 "ldr" : loadImmClassName(False, True, False), 1008 "str" : storeImmClassName(False, True, False), 1009 "ldrh" : loadImmClassName(False, True, False, size=2), 1010 "strh" : storeImmClassName(False, True, False, size=2), 1011 "ldrb" : loadImmClassName(False, True, False, size=1), 1012 "strb" : storeImmClassName(False, True, False, size=1), 1013 } 1014 decode_block = decode % classNames 1015}}; 1016 1017def format Thumb16MemLit() {{ 1018 decode_block = ''' 1019 { 1020 const uint32_t rt = bits(machInst, 10, 8); 1021 const uint32_t imm8 = bits(machInst, 7, 0); 1022 return new %s(machInst, rt, INTREG_PC, true, imm8 << 2); 1023 } 1024 ''' % loadImmClassName(False, True, False) 1025}}; 1026 1027