macromem.isa revision 6310:be6658746087
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Stephen Hines 30// Gabe Black 31 32//////////////////////////////////////////////////////////////////// 33// 34// Common microop templates 35// 36 37def template MicroConstructor {{ 38 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 39 RegIndex _ura, 40 RegIndex _urb, 41 uint8_t _imm) 42 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 43 _ura, _urb, _imm) 44 { 45 %(constructor)s; 46 } 47}}; 48 49//////////////////////////////////////////////////////////////////// 50// 51// Load/store microops 52// 53 54def template MicroMemDeclare {{ 55 class %(class_name)s : public %(base_class)s 56 { 57 public: 58 %(class_name)s(ExtMachInst machInst, 59 RegIndex _ura, RegIndex _urb, 60 uint8_t _imm); 61 %(BasicExecDeclare)s 62 %(InitiateAccDeclare)s 63 %(CompleteAccDeclare)s 64 }; 65}}; 66 67let {{ 68 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 69 'MicroMemOp', 70 {'memacc_code': 'Ra = Mem;', 71 'ea_code': 'EA = Rb + (UP ? imm : -imm);', 72 'predicate_test': predicateTest}, 73 ['IsMicroop']) 74 75 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 76 'MicroMemOp', 77 {'memacc_code': 'Mem = Ra;', 78 'ea_code': 'EA = Rb + (UP ? imm : -imm);', 79 'predicate_test': predicateTest}, 80 ['IsMicroop']) 81 82 header_output = MicroMemDeclare.subst(microLdrUopIop) + \ 83 MicroMemDeclare.subst(microStrUopIop) 84 decoder_output = MicroConstructor.subst(microLdrUopIop) + \ 85 MicroConstructor.subst(microStrUopIop) 86 exec_output = LoadExecute.subst(microLdrUopIop) + \ 87 StoreExecute.subst(microStrUopIop) + \ 88 LoadInitiateAcc.subst(microLdrUopIop) + \ 89 StoreInitiateAcc.subst(microStrUopIop) + \ 90 LoadCompleteAcc.subst(microLdrUopIop) + \ 91 StoreCompleteAcc.subst(microStrUopIop) 92}}; 93 94//////////////////////////////////////////////////////////////////// 95// 96// Integer = Integer op Immediate microops 97// 98 99def template MicroIntDeclare {{ 100 class %(class_name)s : public %(base_class)s 101 { 102 public: 103 %(class_name)s(ExtMachInst machInst, 104 RegIndex _ura, RegIndex _urb, 105 uint8_t _imm); 106 %(BasicExecDeclare)s 107 }; 108}}; 109 110let {{ 111 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 112 'MicroIntOp', 113 {'code': 'Ra = Rb + imm;', 114 'predicate_test': predicateTest}, 115 ['IsMicroop']) 116 117 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 118 'MicroIntOp', 119 {'code': 'Ra = Rb - imm;', 120 'predicate_test': predicateTest}, 121 ['IsMicroop']) 122 123 header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 124 MicroIntDeclare.subst(microSubiUopIop) 125 decoder_output = MicroConstructor.subst(microAddiUopIop) + \ 126 MicroConstructor.subst(microSubiUopIop) 127 exec_output = PredOpExecute.subst(microAddiUopIop) + \ 128 PredOpExecute.subst(microSubiUopIop) 129}}; 130 131//////////////////////////////////////////////////////////////////// 132// 133// Moving to/from double floating point registers 134// 135 136let {{ 137 microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop', 138 'PredOp', 139 {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;', 140 'predicate_test': predicateTest}, 141 ['IsMicroop']) 142 143 microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop', 144 'PredOp', 145 {'code': '''Rhi = bits(Fd.ud, 63, 32); 146 Rlo = bits(Fd.ud, 31, 0);''', 147 'predicate_test': predicateTest}, 148 ['IsMicroop']) 149 150 header_output = BasicDeclare.subst(microMvtdUopIop) + \ 151 BasicDeclare.subst(microMvfdUopIop) 152 decoder_output = BasicConstructor.subst(microMvtdUopIop) + \ 153 BasicConstructor.subst(microMvfdUopIop) 154 exec_output = PredOpExecute.subst(microMvtdUopIop) + \ 155 PredOpExecute.subst(microMvfdUopIop) 156}}; 157 158//////////////////////////////////////////////////////////////////// 159// 160// Macro Memory-format instructions 161// 162 163def template MacroStoreDeclare {{ 164/** 165 * Static instructions class for a store multiple instruction 166 */ 167class %(class_name)s : public %(base_class)s 168{ 169 public: 170 // Constructor 171 %(class_name)s(ExtMachInst machInst); 172 %(BasicExecDeclare)s 173}; 174}}; 175 176def template MacroStoreConstructor {{ 177inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 178 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 179{ 180 %(constructor)s; 181 uint32_t regs_to_handle = reglist; 182 uint32_t start_addr = 0; 183 184 switch (puswl) 185 { 186 case 0x00: // stmda 187 case 0x01: // L ldmda_l 188 case 0x02: // W stmda_w 189 case 0x03: // WL ldmda_wl 190 start_addr = (ones << 2) - 4; 191 break; 192 case 0x08: // U stmia_u 193 case 0x09: // U L ldmia_ul 194 case 0x0a: // U W stmia 195 case 0x0b: // U WL ldmia 196 start_addr = 0; 197 break; 198 case 0x10: // P stmdb 199 case 0x11: // P L ldmdb 200 case 0x12: // P W stmdb 201 case 0x13: // P WL ldmdb 202 start_addr = (ones << 2); // U-bit is already 0 for subtract 203 break; 204 case 0x18: // PU stmib 205 case 0x19: // PU L ldmib 206 case 0x1a: // PU W stmib 207 case 0x1b: // PU WL ldmib 208 start_addr = 4; 209 break; 210 default: 211 panic("Unhandled Load/Store Multiple Instruction, " 212 "puswl = 0x%x", (unsigned) puswl); 213 break; 214 } 215 216 // Add 0 to Rn and stick it in Raddr (register 17). 217 // This is equivalent to a move. 218 microOps[0] = new MicroAddiUop(machInst, 17, RN, 0); 219 220 unsigned j = 0; 221 for (int i = 1; i < ones+1; i++) { 222 // Get next available bit for transfer 223 while (! ( regs_to_handle & (1<<j))) 224 j++; 225 regs_to_handle &= ~(1<<j); 226 227 if (loadop) 228 microOps[i] = new MicroLdrUop(machInst, j, 17, start_addr); 229 else 230 microOps[i] = new MicroStrUop(machInst, j, 17, start_addr); 231 232 if (up) 233 start_addr += 4; 234 else 235 start_addr -= 4; 236 } 237 238 if (writeback) { 239 if (up) { 240 microOps[numMicroops-1] = 241 new MicroAddiUop(machInst, RN, RN, ones * 4); 242 } else { 243 microOps[numMicroops-1] = 244 new MicroSubiUop(machInst, RN, RN, ones * 4); 245 } 246 } 247 microOps[numMicroops-1]->setLastMicroop(); 248} 249 250}}; 251 252def template MacroStoreExecute {{ 253Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 254{ 255 Fault fault = NoFault; 256 257 %(fp_enable_check)s; 258 %(op_decl)s; 259 %(op_rd)s; 260 %(code)s; 261 if (fault == NoFault) 262 { 263 %(op_wb)s; 264 } 265 266 return fault; 267} 268}}; 269 270def template MacroFPAConstructor {{ 271inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 272 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 273{ 274 %(constructor)s; 275 276 uint32_t start_addr = 0; 277 278 if (prepost) 279 start_addr = disp8; 280 else 281 start_addr = 0; 282 283 emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr); 284 285 if (writeback) 286 { 287 if (up) { 288 microOps[numMicroops-1] = 289 new MicroAddiUop(machInst, RN, RN, disp8); 290 } else { 291 microOps[numMicroops-1] = 292 new MicroSubiUop(machInst, RN, RN, disp8); 293 } 294 } 295 microOps[numMicroops-1]->setLastMicroop(); 296} 297 298}}; 299 300 301def template MacroFMConstructor {{ 302inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 303 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 304{ 305 %(constructor)s; 306 307 uint32_t start_addr = 0; 308 309 if (prepost) 310 start_addr = disp8; 311 else 312 start_addr = 0; 313 314 for (int i = 0; i < count; i++) 315 emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr); 316 317 if (writeback) { 318 if (up) { 319 microOps[numMicroops-1] = 320 new MicroAddiUop(machInst, RN, RN, disp8); 321 } else { 322 microOps[numMicroops-1] = 323 new MicroSubiUop(machInst, RN, RN, disp8); 324 } 325 } 326 microOps[numMicroops-1]->setLastMicroop(); 327} 328}}; 329 330 331def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 332 iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags) 333 header_output = MacroStoreDeclare.subst(iop) 334 decoder_output = MacroStoreConstructor.subst(iop) 335 decode_block = BasicDecode.subst(iop) 336 exec_output = MacroStoreExecute.subst(iop) 337}}; 338 339def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 340 iop = InstObjParams(name, Name, 'ArmMacroFPAOp', 341 {"code": code, 342 "predicate_test": predicateTest}, 343 opt_flags) 344 header_output = BasicDeclare.subst(iop) 345 decoder_output = MacroFPAConstructor.subst(iop) 346 decode_block = BasicDecode.subst(iop) 347 exec_output = PredOpExecute.subst(iop) 348}}; 349 350def format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 351 iop = InstObjParams(name, Name, 'ArmMacroFMOp', 352 {"code": code, 353 "predicate_test": predicateTest}, 354 opt_flags) 355 header_output = BasicDeclare.subst(iop) 356 decoder_output = MacroFMConstructor.subst(iop) 357 decode_block = BasicDecode.subst(iop) 358 exec_output = PredOpExecute.subst(iop) 359}}; 360