macromem.isa revision 6309
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 36019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu// All rights reserved. 56019Shines@cs.fsu.edu// 66019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu// this software without specific prior written permission. 166019Shines@cs.fsu.edu// 176019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// Authors: Stephen Hines 306308Sgblack@eecs.umich.edu// Gabe Black 316308Sgblack@eecs.umich.edu 326309Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 336309Sgblack@eecs.umich.edu// 346309Sgblack@eecs.umich.edu// Common microop templates 356309Sgblack@eecs.umich.edu// 366309Sgblack@eecs.umich.edu 376309Sgblack@eecs.umich.edudef template MicroConstructor {{ 386309Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 396309Sgblack@eecs.umich.edu RegIndex _ura, 406309Sgblack@eecs.umich.edu RegIndex _urb, 416309Sgblack@eecs.umich.edu uint8_t _imm) 426309Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 436309Sgblack@eecs.umich.edu _ura, _urb, _imm) 446309Sgblack@eecs.umich.edu { 456309Sgblack@eecs.umich.edu %(constructor)s; 466309Sgblack@eecs.umich.edu } 476309Sgblack@eecs.umich.edu}}; 486309Sgblack@eecs.umich.edu 496309Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 506309Sgblack@eecs.umich.edu// 516309Sgblack@eecs.umich.edu// Load/store microops 526309Sgblack@eecs.umich.edu// 536309Sgblack@eecs.umich.edu 546309Sgblack@eecs.umich.edudef template MicroMemDeclare {{ 556309Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 566309Sgblack@eecs.umich.edu { 576309Sgblack@eecs.umich.edu public: 586309Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 596309Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, 606309Sgblack@eecs.umich.edu uint8_t _imm); 616309Sgblack@eecs.umich.edu %(BasicExecDeclare)s 626309Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 636309Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 646309Sgblack@eecs.umich.edu }; 656309Sgblack@eecs.umich.edu}}; 666309Sgblack@eecs.umich.edu 676309Sgblack@eecs.umich.edulet {{ 686309Sgblack@eecs.umich.edu microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 696309Sgblack@eecs.umich.edu 'MicroMemOp', 706309Sgblack@eecs.umich.edu {'memacc_code': 'Ra = Mem;', 716309Sgblack@eecs.umich.edu 'ea_code': 'EA = Rb + (UP ? imm : -imm);', 726309Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 736309Sgblack@eecs.umich.edu ['IsMicroop']) 746309Sgblack@eecs.umich.edu 756309Sgblack@eecs.umich.edu microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 766309Sgblack@eecs.umich.edu 'MicroMemOp', 776309Sgblack@eecs.umich.edu {'memacc_code': 'Mem = Ra;', 786309Sgblack@eecs.umich.edu 'ea_code': 'EA = Rb + (UP ? imm : -imm);', 796309Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 806309Sgblack@eecs.umich.edu ['IsMicroop']) 816309Sgblack@eecs.umich.edu 826309Sgblack@eecs.umich.edu header_output = MicroMemDeclare.subst(microLdrUopIop) + \ 836309Sgblack@eecs.umich.edu MicroMemDeclare.subst(microStrUopIop) 846309Sgblack@eecs.umich.edu decoder_output = MicroConstructor.subst(microLdrUopIop) + \ 856309Sgblack@eecs.umich.edu MicroConstructor.subst(microStrUopIop) 866309Sgblack@eecs.umich.edu exec_output = LoadExecute.subst(microLdrUopIop) + \ 876309Sgblack@eecs.umich.edu StoreExecute.subst(microStrUopIop) + \ 886309Sgblack@eecs.umich.edu LoadInitiateAcc.subst(microLdrUopIop) + \ 896309Sgblack@eecs.umich.edu StoreInitiateAcc.subst(microStrUopIop) + \ 906309Sgblack@eecs.umich.edu LoadCompleteAcc.subst(microLdrUopIop) + \ 916309Sgblack@eecs.umich.edu StoreCompleteAcc.subst(microStrUopIop) 926309Sgblack@eecs.umich.edu}}; 936308Sgblack@eecs.umich.edu 946308Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 956308Sgblack@eecs.umich.edu// 966308Sgblack@eecs.umich.edu// Integer = Integer op Immediate microops 976308Sgblack@eecs.umich.edu// 986308Sgblack@eecs.umich.edu 996308Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1006308Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1016308Sgblack@eecs.umich.edu { 1026308Sgblack@eecs.umich.edu public: 1036308Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1046308Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, 1056308Sgblack@eecs.umich.edu uint8_t _imm); 1066308Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1076308Sgblack@eecs.umich.edu }; 1086308Sgblack@eecs.umich.edu}}; 1096308Sgblack@eecs.umich.edu 1106308Sgblack@eecs.umich.edulet {{ 1116308Sgblack@eecs.umich.edu microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 1126308Sgblack@eecs.umich.edu 'MicroIntOp', 1136308Sgblack@eecs.umich.edu {'code': 'Ra = Rb + imm;', 1146308Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1156308Sgblack@eecs.umich.edu ['IsMicroop']) 1166308Sgblack@eecs.umich.edu 1176308Sgblack@eecs.umich.edu microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 1186308Sgblack@eecs.umich.edu 'MicroIntOp', 1196308Sgblack@eecs.umich.edu {'code': 'Ra = Rb - imm;', 1206308Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1216308Sgblack@eecs.umich.edu ['IsMicroop']) 1226308Sgblack@eecs.umich.edu 1236308Sgblack@eecs.umich.edu header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 1246308Sgblack@eecs.umich.edu MicroIntDeclare.subst(microSubiUopIop) 1256309Sgblack@eecs.umich.edu decoder_output = MicroConstructor.subst(microAddiUopIop) + \ 1266309Sgblack@eecs.umich.edu MicroConstructor.subst(microSubiUopIop) 1276308Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(microAddiUopIop) + \ 1286308Sgblack@eecs.umich.edu PredOpExecute.subst(microSubiUopIop) 1296308Sgblack@eecs.umich.edu}}; 1306019Shines@cs.fsu.edu 1316019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 1326019Shines@cs.fsu.edu// 1336019Shines@cs.fsu.edu// Macro Memory-format instructions 1346019Shines@cs.fsu.edu// 1356019Shines@cs.fsu.edu 1366019Shines@cs.fsu.edudef template MacroStoreDeclare {{ 1376253Sgblack@eecs.umich.edu/** 1386253Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 1396253Sgblack@eecs.umich.edu */ 1406253Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1416253Sgblack@eecs.umich.edu{ 1426253Sgblack@eecs.umich.edu public: 1436253Sgblack@eecs.umich.edu // Constructor 1446253Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst); 1456253Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1466253Sgblack@eecs.umich.edu}; 1476019Shines@cs.fsu.edu}}; 1486019Shines@cs.fsu.edu 1496019Shines@cs.fsu.edudef template MacroStoreConstructor {{ 1506253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1516253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1526253Sgblack@eecs.umich.edu{ 1536253Sgblack@eecs.umich.edu %(constructor)s; 1546253Sgblack@eecs.umich.edu uint32_t regs_to_handle = reglist; 1556304Sgblack@eecs.umich.edu uint32_t start_addr = 0; 1566253Sgblack@eecs.umich.edu 1576253Sgblack@eecs.umich.edu switch (puswl) 1586019Shines@cs.fsu.edu { 1596258Sjack-m5ml2@cs.york.ac.uk case 0x00: // stmda 1606253Sgblack@eecs.umich.edu case 0x01: // L ldmda_l 1616258Sjack-m5ml2@cs.york.ac.uk case 0x02: // W stmda_w 1626253Sgblack@eecs.umich.edu case 0x03: // WL ldmda_wl 1636253Sgblack@eecs.umich.edu start_addr = (ones << 2) - 4; 1646253Sgblack@eecs.umich.edu break; 1656253Sgblack@eecs.umich.edu case 0x08: // U stmia_u 1666253Sgblack@eecs.umich.edu case 0x09: // U L ldmia_ul 1676258Sjack-m5ml2@cs.york.ac.uk case 0x0a: // U W stmia 1686253Sgblack@eecs.umich.edu case 0x0b: // U WL ldmia 1696253Sgblack@eecs.umich.edu start_addr = 0; 1706253Sgblack@eecs.umich.edu break; 1716258Sjack-m5ml2@cs.york.ac.uk case 0x10: // P stmdb 1726253Sgblack@eecs.umich.edu case 0x11: // P L ldmdb 1736253Sgblack@eecs.umich.edu case 0x12: // P W stmdb 1746258Sjack-m5ml2@cs.york.ac.uk case 0x13: // P WL ldmdb 1756253Sgblack@eecs.umich.edu start_addr = (ones << 2); // U-bit is already 0 for subtract 1766253Sgblack@eecs.umich.edu break; 1776253Sgblack@eecs.umich.edu case 0x18: // PU stmib 1786253Sgblack@eecs.umich.edu case 0x19: // PU L ldmib 1796258Sjack-m5ml2@cs.york.ac.uk case 0x1a: // PU W stmib 1806258Sjack-m5ml2@cs.york.ac.uk case 0x1b: // PU WL ldmib 1816253Sgblack@eecs.umich.edu start_addr = 4; 1826253Sgblack@eecs.umich.edu break; 1836253Sgblack@eecs.umich.edu default: 1846258Sjack-m5ml2@cs.york.ac.uk panic("Unhandled Load/Store Multiple Instruction, " 1856258Sjack-m5ml2@cs.york.ac.uk "puswl = 0x%x", (unsigned) puswl); 1866253Sgblack@eecs.umich.edu break; 1876253Sgblack@eecs.umich.edu } 1886019Shines@cs.fsu.edu 1896308Sgblack@eecs.umich.edu // Add 0 to Rn and stick it in Raddr (register 17). 1906308Sgblack@eecs.umich.edu // This is equivalent to a move. 1916308Sgblack@eecs.umich.edu microOps[0] = new MicroAddiUop(machInst, 17, RN, 0); 1926253Sgblack@eecs.umich.edu 1936304Sgblack@eecs.umich.edu unsigned j = 0; 1946308Sgblack@eecs.umich.edu for (int i = 1; i < ones+1; i++) { 1956253Sgblack@eecs.umich.edu // Get next available bit for transfer 1966253Sgblack@eecs.umich.edu while (! ( regs_to_handle & (1<<j))) 1976253Sgblack@eecs.umich.edu j++; 1986253Sgblack@eecs.umich.edu regs_to_handle &= ~(1<<j); 1996253Sgblack@eecs.umich.edu 2006309Sgblack@eecs.umich.edu if (loadop) 2016309Sgblack@eecs.umich.edu microOps[i] = new MicroLdrUop(machInst, j, 17, start_addr); 2026309Sgblack@eecs.umich.edu else 2036309Sgblack@eecs.umich.edu microOps[i] = new MicroStrUop(machInst, j, 17, start_addr); 2046253Sgblack@eecs.umich.edu 2056253Sgblack@eecs.umich.edu if (up) 2066253Sgblack@eecs.umich.edu start_addr += 4; 2076253Sgblack@eecs.umich.edu else 2086253Sgblack@eecs.umich.edu start_addr -= 4; 2096253Sgblack@eecs.umich.edu } 2106253Sgblack@eecs.umich.edu 2116308Sgblack@eecs.umich.edu if (writeback) { 2126308Sgblack@eecs.umich.edu if (up) { 2136308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2146308Sgblack@eecs.umich.edu new MicroAddiUop(machInst, RN, RN, ones * 4); 2156308Sgblack@eecs.umich.edu } else { 2166308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2176308Sgblack@eecs.umich.edu new MicroSubiUop(machInst, RN, RN, ones * 4); 2186019Shines@cs.fsu.edu } 2196019Shines@cs.fsu.edu } 2206253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 2216253Sgblack@eecs.umich.edu} 2226019Shines@cs.fsu.edu 2236019Shines@cs.fsu.edu}}; 2246019Shines@cs.fsu.edu 2256019Shines@cs.fsu.edudef template MacroStoreExecute {{ 2266253Sgblack@eecs.umich.eduFault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2276253Sgblack@eecs.umich.edu{ 2286253Sgblack@eecs.umich.edu Fault fault = NoFault; 2296253Sgblack@eecs.umich.edu 2306253Sgblack@eecs.umich.edu %(fp_enable_check)s; 2316253Sgblack@eecs.umich.edu %(op_decl)s; 2326253Sgblack@eecs.umich.edu %(op_rd)s; 2336253Sgblack@eecs.umich.edu %(code)s; 2346253Sgblack@eecs.umich.edu if (fault == NoFault) 2356019Shines@cs.fsu.edu { 2366253Sgblack@eecs.umich.edu %(op_wb)s; 2376253Sgblack@eecs.umich.edu } 2386019Shines@cs.fsu.edu 2396253Sgblack@eecs.umich.edu return fault; 2406253Sgblack@eecs.umich.edu} 2416019Shines@cs.fsu.edu}}; 2426019Shines@cs.fsu.edu 2436019Shines@cs.fsu.edudef template MacroFPAConstructor {{ 2446253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 2456253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 2466253Sgblack@eecs.umich.edu{ 2476253Sgblack@eecs.umich.edu %(constructor)s; 2486253Sgblack@eecs.umich.edu 2496253Sgblack@eecs.umich.edu uint32_t start_addr = 0; 2506253Sgblack@eecs.umich.edu 2516253Sgblack@eecs.umich.edu if (prepost) 2526253Sgblack@eecs.umich.edu start_addr = disp8; 2536253Sgblack@eecs.umich.edu else 2546253Sgblack@eecs.umich.edu start_addr = 0; 2556253Sgblack@eecs.umich.edu 2566253Sgblack@eecs.umich.edu emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr); 2576253Sgblack@eecs.umich.edu 2586253Sgblack@eecs.umich.edu if (writeback) 2596019Shines@cs.fsu.edu { 2606308Sgblack@eecs.umich.edu if (up) { 2616308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2626308Sgblack@eecs.umich.edu new MicroAddiUop(machInst, RN, RN, disp8); 2636308Sgblack@eecs.umich.edu } else { 2646308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2656308Sgblack@eecs.umich.edu new MicroSubiUop(machInst, RN, RN, disp8); 2666019Shines@cs.fsu.edu } 2676019Shines@cs.fsu.edu } 2686253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 2696253Sgblack@eecs.umich.edu} 2706019Shines@cs.fsu.edu 2716019Shines@cs.fsu.edu}}; 2726019Shines@cs.fsu.edu 2736019Shines@cs.fsu.edu 2746019Shines@cs.fsu.edudef template MacroFMConstructor {{ 2756253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 2766253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 2776253Sgblack@eecs.umich.edu{ 2786253Sgblack@eecs.umich.edu %(constructor)s; 2796253Sgblack@eecs.umich.edu 2806253Sgblack@eecs.umich.edu uint32_t start_addr = 0; 2816253Sgblack@eecs.umich.edu 2826253Sgblack@eecs.umich.edu if (prepost) 2836253Sgblack@eecs.umich.edu start_addr = disp8; 2846253Sgblack@eecs.umich.edu else 2856253Sgblack@eecs.umich.edu start_addr = 0; 2866253Sgblack@eecs.umich.edu 2876253Sgblack@eecs.umich.edu for (int i = 0; i < count; i++) 2886253Sgblack@eecs.umich.edu emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr); 2896019Shines@cs.fsu.edu 2906308Sgblack@eecs.umich.edu if (writeback) { 2916308Sgblack@eecs.umich.edu if (up) { 2926308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2936308Sgblack@eecs.umich.edu new MicroAddiUop(machInst, RN, RN, disp8); 2946308Sgblack@eecs.umich.edu } else { 2956308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2966308Sgblack@eecs.umich.edu new MicroSubiUop(machInst, RN, RN, disp8); 2976253Sgblack@eecs.umich.edu } 2986253Sgblack@eecs.umich.edu } 2996253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 3006253Sgblack@eecs.umich.edu} 3016019Shines@cs.fsu.edu}}; 3026019Shines@cs.fsu.edu 3036019Shines@cs.fsu.edu 3046019Shines@cs.fsu.edudef format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 3056019Shines@cs.fsu.edu iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags) 3066019Shines@cs.fsu.edu header_output = MacroStoreDeclare.subst(iop) 3076019Shines@cs.fsu.edu decoder_output = MacroStoreConstructor.subst(iop) 3086019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 3096019Shines@cs.fsu.edu exec_output = MacroStoreExecute.subst(iop) 3106019Shines@cs.fsu.edu}}; 3116019Shines@cs.fsu.edu 3126019Shines@cs.fsu.edudef format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 3136243Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'ArmMacroFPAOp', 3146243Sgblack@eecs.umich.edu {"code": code, 3156243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 3166243Sgblack@eecs.umich.edu opt_flags) 3176019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 3186019Shines@cs.fsu.edu decoder_output = MacroFPAConstructor.subst(iop) 3196019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 3206019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 3216019Shines@cs.fsu.edu}}; 3226019Shines@cs.fsu.edu 3236019Shines@cs.fsu.edudef format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 3246243Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'ArmMacroFMOp', 3256243Sgblack@eecs.umich.edu {"code": code, 3266243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 3276243Sgblack@eecs.umich.edu opt_flags) 3286019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 3296019Shines@cs.fsu.edu decoder_output = MacroFMConstructor.subst(iop) 3306019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 3316019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 3326019Shines@cs.fsu.edu}}; 333