macromem.isa revision 6308
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 36019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu// All rights reserved. 56019Shines@cs.fsu.edu// 66019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu// this software without specific prior written permission. 166019Shines@cs.fsu.edu// 176019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// Authors: Stephen Hines 306308Sgblack@eecs.umich.edu// Gabe Black 316308Sgblack@eecs.umich.edu 326308Sgblack@eecs.umich.edu 336308Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 346308Sgblack@eecs.umich.edu// 356308Sgblack@eecs.umich.edu// Integer = Integer op Immediate microops 366308Sgblack@eecs.umich.edu// 376308Sgblack@eecs.umich.edu 386308Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 396308Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 406308Sgblack@eecs.umich.edu { 416308Sgblack@eecs.umich.edu public: 426308Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 436308Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, 446308Sgblack@eecs.umich.edu uint8_t _imm); 456308Sgblack@eecs.umich.edu %(BasicExecDeclare)s 466308Sgblack@eecs.umich.edu }; 476308Sgblack@eecs.umich.edu}}; 486308Sgblack@eecs.umich.edu 496308Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 506308Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 516308Sgblack@eecs.umich.edu RegIndex _ura, 526308Sgblack@eecs.umich.edu RegIndex _urb, 536308Sgblack@eecs.umich.edu uint8_t _imm) 546308Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 556308Sgblack@eecs.umich.edu _ura, _urb, _imm) 566308Sgblack@eecs.umich.edu { 576308Sgblack@eecs.umich.edu %(constructor)s; 586308Sgblack@eecs.umich.edu } 596308Sgblack@eecs.umich.edu}}; 606308Sgblack@eecs.umich.edu 616308Sgblack@eecs.umich.edulet {{ 626308Sgblack@eecs.umich.edu microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 636308Sgblack@eecs.umich.edu 'MicroIntOp', 646308Sgblack@eecs.umich.edu {'code': 'Ra = Rb + imm;', 656308Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 666308Sgblack@eecs.umich.edu ['IsMicroop']) 676308Sgblack@eecs.umich.edu 686308Sgblack@eecs.umich.edu microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 696308Sgblack@eecs.umich.edu 'MicroIntOp', 706308Sgblack@eecs.umich.edu {'code': 'Ra = Rb - imm;', 716308Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 726308Sgblack@eecs.umich.edu ['IsMicroop']) 736308Sgblack@eecs.umich.edu 746308Sgblack@eecs.umich.edu header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 756308Sgblack@eecs.umich.edu MicroIntDeclare.subst(microSubiUopIop) 766308Sgblack@eecs.umich.edu decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \ 776308Sgblack@eecs.umich.edu MicroIntConstructor.subst(microSubiUopIop) 786308Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(microAddiUopIop) + \ 796308Sgblack@eecs.umich.edu PredOpExecute.subst(microSubiUopIop) 806308Sgblack@eecs.umich.edu}}; 816019Shines@cs.fsu.edu 826019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 836019Shines@cs.fsu.edu// 846019Shines@cs.fsu.edu// Macro Memory-format instructions 856019Shines@cs.fsu.edu// 866019Shines@cs.fsu.edu 876019Shines@cs.fsu.edudef template MacroStoreDeclare {{ 886253Sgblack@eecs.umich.edu/** 896253Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 906253Sgblack@eecs.umich.edu */ 916253Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 926253Sgblack@eecs.umich.edu{ 936253Sgblack@eecs.umich.edu public: 946253Sgblack@eecs.umich.edu // Constructor 956253Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst); 966253Sgblack@eecs.umich.edu %(BasicExecDeclare)s 976253Sgblack@eecs.umich.edu}; 986019Shines@cs.fsu.edu}}; 996019Shines@cs.fsu.edu 1006019Shines@cs.fsu.edudef template MacroStoreConstructor {{ 1016253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1026253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1036253Sgblack@eecs.umich.edu{ 1046253Sgblack@eecs.umich.edu %(constructor)s; 1056253Sgblack@eecs.umich.edu uint32_t regs_to_handle = reglist; 1066304Sgblack@eecs.umich.edu uint32_t start_addr = 0; 1076253Sgblack@eecs.umich.edu 1086253Sgblack@eecs.umich.edu switch (puswl) 1096019Shines@cs.fsu.edu { 1106258Sjack-m5ml2@cs.york.ac.uk case 0x00: // stmda 1116253Sgblack@eecs.umich.edu case 0x01: // L ldmda_l 1126258Sjack-m5ml2@cs.york.ac.uk case 0x02: // W stmda_w 1136253Sgblack@eecs.umich.edu case 0x03: // WL ldmda_wl 1146253Sgblack@eecs.umich.edu start_addr = (ones << 2) - 4; 1156253Sgblack@eecs.umich.edu break; 1166253Sgblack@eecs.umich.edu case 0x08: // U stmia_u 1176253Sgblack@eecs.umich.edu case 0x09: // U L ldmia_ul 1186258Sjack-m5ml2@cs.york.ac.uk case 0x0a: // U W stmia 1196253Sgblack@eecs.umich.edu case 0x0b: // U WL ldmia 1206253Sgblack@eecs.umich.edu start_addr = 0; 1216253Sgblack@eecs.umich.edu break; 1226258Sjack-m5ml2@cs.york.ac.uk case 0x10: // P stmdb 1236253Sgblack@eecs.umich.edu case 0x11: // P L ldmdb 1246253Sgblack@eecs.umich.edu case 0x12: // P W stmdb 1256258Sjack-m5ml2@cs.york.ac.uk case 0x13: // P WL ldmdb 1266253Sgblack@eecs.umich.edu start_addr = (ones << 2); // U-bit is already 0 for subtract 1276253Sgblack@eecs.umich.edu break; 1286253Sgblack@eecs.umich.edu case 0x18: // PU stmib 1296253Sgblack@eecs.umich.edu case 0x19: // PU L ldmib 1306258Sjack-m5ml2@cs.york.ac.uk case 0x1a: // PU W stmib 1316258Sjack-m5ml2@cs.york.ac.uk case 0x1b: // PU WL ldmib 1326253Sgblack@eecs.umich.edu start_addr = 4; 1336253Sgblack@eecs.umich.edu break; 1346253Sgblack@eecs.umich.edu default: 1356258Sjack-m5ml2@cs.york.ac.uk panic("Unhandled Load/Store Multiple Instruction, " 1366258Sjack-m5ml2@cs.york.ac.uk "puswl = 0x%x", (unsigned) puswl); 1376253Sgblack@eecs.umich.edu break; 1386253Sgblack@eecs.umich.edu } 1396019Shines@cs.fsu.edu 1406308Sgblack@eecs.umich.edu // Add 0 to Rn and stick it in Raddr (register 17). 1416308Sgblack@eecs.umich.edu // This is equivalent to a move. 1426308Sgblack@eecs.umich.edu microOps[0] = new MicroAddiUop(machInst, 17, RN, 0); 1436253Sgblack@eecs.umich.edu 1446304Sgblack@eecs.umich.edu unsigned j = 0; 1456308Sgblack@eecs.umich.edu for (int i = 1; i < ones+1; i++) { 1466253Sgblack@eecs.umich.edu // Get next available bit for transfer 1476253Sgblack@eecs.umich.edu while (! ( regs_to_handle & (1<<j))) 1486253Sgblack@eecs.umich.edu j++; 1496253Sgblack@eecs.umich.edu regs_to_handle &= ~(1<<j); 1506253Sgblack@eecs.umich.edu 1516253Sgblack@eecs.umich.edu microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr); 1526253Sgblack@eecs.umich.edu 1536253Sgblack@eecs.umich.edu if (up) 1546253Sgblack@eecs.umich.edu start_addr += 4; 1556253Sgblack@eecs.umich.edu else 1566253Sgblack@eecs.umich.edu start_addr -= 4; 1576253Sgblack@eecs.umich.edu } 1586253Sgblack@eecs.umich.edu 1596308Sgblack@eecs.umich.edu if (writeback) { 1606308Sgblack@eecs.umich.edu if (up) { 1616308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 1626308Sgblack@eecs.umich.edu new MicroAddiUop(machInst, RN, RN, ones * 4); 1636308Sgblack@eecs.umich.edu } else { 1646308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 1656308Sgblack@eecs.umich.edu new MicroSubiUop(machInst, RN, RN, ones * 4); 1666019Shines@cs.fsu.edu } 1676019Shines@cs.fsu.edu } 1686253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 1696253Sgblack@eecs.umich.edu} 1706019Shines@cs.fsu.edu 1716019Shines@cs.fsu.edu}}; 1726019Shines@cs.fsu.edu 1736019Shines@cs.fsu.edudef template MacroStoreExecute {{ 1746253Sgblack@eecs.umich.eduFault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1756253Sgblack@eecs.umich.edu{ 1766253Sgblack@eecs.umich.edu Fault fault = NoFault; 1776253Sgblack@eecs.umich.edu 1786253Sgblack@eecs.umich.edu %(fp_enable_check)s; 1796253Sgblack@eecs.umich.edu %(op_decl)s; 1806253Sgblack@eecs.umich.edu %(op_rd)s; 1816253Sgblack@eecs.umich.edu %(code)s; 1826253Sgblack@eecs.umich.edu if (fault == NoFault) 1836019Shines@cs.fsu.edu { 1846253Sgblack@eecs.umich.edu %(op_wb)s; 1856253Sgblack@eecs.umich.edu } 1866019Shines@cs.fsu.edu 1876253Sgblack@eecs.umich.edu return fault; 1886253Sgblack@eecs.umich.edu} 1896019Shines@cs.fsu.edu}}; 1906019Shines@cs.fsu.edu 1916019Shines@cs.fsu.edudef template MacroFPAConstructor {{ 1926253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1936253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1946253Sgblack@eecs.umich.edu{ 1956253Sgblack@eecs.umich.edu %(constructor)s; 1966253Sgblack@eecs.umich.edu 1976253Sgblack@eecs.umich.edu uint32_t start_addr = 0; 1986253Sgblack@eecs.umich.edu 1996253Sgblack@eecs.umich.edu if (prepost) 2006253Sgblack@eecs.umich.edu start_addr = disp8; 2016253Sgblack@eecs.umich.edu else 2026253Sgblack@eecs.umich.edu start_addr = 0; 2036253Sgblack@eecs.umich.edu 2046253Sgblack@eecs.umich.edu emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr); 2056253Sgblack@eecs.umich.edu 2066253Sgblack@eecs.umich.edu if (writeback) 2076019Shines@cs.fsu.edu { 2086308Sgblack@eecs.umich.edu if (up) { 2096308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2106308Sgblack@eecs.umich.edu new MicroAddiUop(machInst, RN, RN, disp8); 2116308Sgblack@eecs.umich.edu } else { 2126308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2136308Sgblack@eecs.umich.edu new MicroSubiUop(machInst, RN, RN, disp8); 2146019Shines@cs.fsu.edu } 2156019Shines@cs.fsu.edu } 2166253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 2176253Sgblack@eecs.umich.edu} 2186019Shines@cs.fsu.edu 2196019Shines@cs.fsu.edu}}; 2206019Shines@cs.fsu.edu 2216019Shines@cs.fsu.edu 2226019Shines@cs.fsu.edudef template MacroFMConstructor {{ 2236253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 2246253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 2256253Sgblack@eecs.umich.edu{ 2266253Sgblack@eecs.umich.edu %(constructor)s; 2276253Sgblack@eecs.umich.edu 2286253Sgblack@eecs.umich.edu uint32_t start_addr = 0; 2296253Sgblack@eecs.umich.edu 2306253Sgblack@eecs.umich.edu if (prepost) 2316253Sgblack@eecs.umich.edu start_addr = disp8; 2326253Sgblack@eecs.umich.edu else 2336253Sgblack@eecs.umich.edu start_addr = 0; 2346253Sgblack@eecs.umich.edu 2356253Sgblack@eecs.umich.edu for (int i = 0; i < count; i++) 2366253Sgblack@eecs.umich.edu emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr); 2376019Shines@cs.fsu.edu 2386308Sgblack@eecs.umich.edu if (writeback) { 2396308Sgblack@eecs.umich.edu if (up) { 2406308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2416308Sgblack@eecs.umich.edu new MicroAddiUop(machInst, RN, RN, disp8); 2426308Sgblack@eecs.umich.edu } else { 2436308Sgblack@eecs.umich.edu microOps[numMicroops-1] = 2446308Sgblack@eecs.umich.edu new MicroSubiUop(machInst, RN, RN, disp8); 2456253Sgblack@eecs.umich.edu } 2466253Sgblack@eecs.umich.edu } 2476253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 2486253Sgblack@eecs.umich.edu} 2496019Shines@cs.fsu.edu}}; 2506019Shines@cs.fsu.edu 2516019Shines@cs.fsu.edu 2526019Shines@cs.fsu.edudef format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 2536019Shines@cs.fsu.edu iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags) 2546019Shines@cs.fsu.edu header_output = MacroStoreDeclare.subst(iop) 2556019Shines@cs.fsu.edu decoder_output = MacroStoreConstructor.subst(iop) 2566019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 2576019Shines@cs.fsu.edu exec_output = MacroStoreExecute.subst(iop) 2586019Shines@cs.fsu.edu}}; 2596019Shines@cs.fsu.edu 2606019Shines@cs.fsu.edudef format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 2616243Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'ArmMacroFPAOp', 2626243Sgblack@eecs.umich.edu {"code": code, 2636243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 2646243Sgblack@eecs.umich.edu opt_flags) 2656019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 2666019Shines@cs.fsu.edu decoder_output = MacroFPAConstructor.subst(iop) 2676019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 2686019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 2696019Shines@cs.fsu.edu}}; 2706019Shines@cs.fsu.edu 2716019Shines@cs.fsu.edudef format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 2726243Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'ArmMacroFMOp', 2736243Sgblack@eecs.umich.edu {"code": code, 2746243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 2756243Sgblack@eecs.umich.edu opt_flags) 2766019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 2776019Shines@cs.fsu.edu decoder_output = MacroFMConstructor.subst(iop) 2786019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 2796019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 2806019Shines@cs.fsu.edu}}; 281