macromem.isa revision 6253
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 36019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu// All rights reserved. 56019Shines@cs.fsu.edu// 66019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu// this software without specific prior written permission. 166019Shines@cs.fsu.edu// 176019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// Authors: Stephen Hines 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 326019Shines@cs.fsu.edu// 336019Shines@cs.fsu.edu// Macro Memory-format instructions 346019Shines@cs.fsu.edu// 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edudef template MacroStoreDeclare {{ 376253Sgblack@eecs.umich.edu/** 386253Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 396253Sgblack@eecs.umich.edu */ 406253Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 416253Sgblack@eecs.umich.edu{ 426253Sgblack@eecs.umich.edu public: 436253Sgblack@eecs.umich.edu // Constructor 446253Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst); 456253Sgblack@eecs.umich.edu %(BasicExecDeclare)s 466253Sgblack@eecs.umich.edu}; 476019Shines@cs.fsu.edu}}; 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.edudef template MacroStoreConstructor {{ 506253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 516253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 526253Sgblack@eecs.umich.edu{ 536253Sgblack@eecs.umich.edu %(constructor)s; 546253Sgblack@eecs.umich.edu uint32_t regs_to_handle = reglist; 556253Sgblack@eecs.umich.edu uint32_t j = 0, 566253Sgblack@eecs.umich.edu start_addr = 0, 576253Sgblack@eecs.umich.edu end_addr = 0; 586253Sgblack@eecs.umich.edu 596253Sgblack@eecs.umich.edu switch (puswl) 606019Shines@cs.fsu.edu { 616253Sgblack@eecs.umich.edu case 0x01: // L ldmda_l 626253Sgblack@eecs.umich.edu start_addr = (ones << 2) - 4; 636253Sgblack@eecs.umich.edu end_addr = 0; 646253Sgblack@eecs.umich.edu break; 656253Sgblack@eecs.umich.edu case 0x03: // WL ldmda_wl 666253Sgblack@eecs.umich.edu start_addr = (ones << 2) - 4; 676253Sgblack@eecs.umich.edu end_addr = 0; 686253Sgblack@eecs.umich.edu break; 696253Sgblack@eecs.umich.edu case 0x08: // U stmia_u 706253Sgblack@eecs.umich.edu start_addr = 0; 716253Sgblack@eecs.umich.edu end_addr = (ones << 2) - 4; 726253Sgblack@eecs.umich.edu break; 736253Sgblack@eecs.umich.edu case 0x09: // U L ldmia_ul 746253Sgblack@eecs.umich.edu start_addr = 0; 756253Sgblack@eecs.umich.edu end_addr = (ones << 2) - 4; 766253Sgblack@eecs.umich.edu break; 776253Sgblack@eecs.umich.edu case 0x0b: // U WL ldmia 786253Sgblack@eecs.umich.edu start_addr = 0; 796253Sgblack@eecs.umich.edu end_addr = (ones << 2) - 4; 806253Sgblack@eecs.umich.edu break; 816253Sgblack@eecs.umich.edu case 0x11: // P L ldmdb 826253Sgblack@eecs.umich.edu start_addr = (ones << 2); // U-bit is already 0 for subtract 836253Sgblack@eecs.umich.edu end_addr = 4; // negative 4 846253Sgblack@eecs.umich.edu break; 856253Sgblack@eecs.umich.edu case 0x12: // P W stmdb 866253Sgblack@eecs.umich.edu start_addr = (ones << 2); // U-bit is already 0 for subtract 876253Sgblack@eecs.umich.edu end_addr = 4; // negative 4 886253Sgblack@eecs.umich.edu break; 896253Sgblack@eecs.umich.edu case 0x18: // PU stmib 906253Sgblack@eecs.umich.edu start_addr = 4; 916253Sgblack@eecs.umich.edu end_addr = (ones << 2) + 4; 926253Sgblack@eecs.umich.edu break; 936253Sgblack@eecs.umich.edu case 0x19: // PU L ldmib 946253Sgblack@eecs.umich.edu start_addr = 4; 956253Sgblack@eecs.umich.edu end_addr = (ones << 2) + 4; 966253Sgblack@eecs.umich.edu break; 976253Sgblack@eecs.umich.edu default: 986253Sgblack@eecs.umich.edu panic("Unhandled Load/Store Multiple Instruction"); 996253Sgblack@eecs.umich.edu break; 1006253Sgblack@eecs.umich.edu } 1016019Shines@cs.fsu.edu 1026253Sgblack@eecs.umich.edu //TODO - Add addi_uop/subi_uop here to create starting addresses 1036253Sgblack@eecs.umich.edu //Just using addi with 0 offset makes a "copy" of Rn for our use 1046253Sgblack@eecs.umich.edu uint32_t newMachInst = 0; 1056253Sgblack@eecs.umich.edu newMachInst = machInst & 0xffff0000; 1066253Sgblack@eecs.umich.edu microOps[0] = new Addi_uop(newMachInst); 1076253Sgblack@eecs.umich.edu 1086253Sgblack@eecs.umich.edu for (int i = 1; i < ones+1; i++) 1096253Sgblack@eecs.umich.edu { 1106253Sgblack@eecs.umich.edu // Get next available bit for transfer 1116253Sgblack@eecs.umich.edu while (! ( regs_to_handle & (1<<j))) 1126253Sgblack@eecs.umich.edu j++; 1136253Sgblack@eecs.umich.edu regs_to_handle &= ~(1<<j); 1146253Sgblack@eecs.umich.edu 1156253Sgblack@eecs.umich.edu microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr); 1166253Sgblack@eecs.umich.edu 1176253Sgblack@eecs.umich.edu if (up) 1186253Sgblack@eecs.umich.edu start_addr += 4; 1196253Sgblack@eecs.umich.edu else 1206253Sgblack@eecs.umich.edu start_addr -= 4; 1216253Sgblack@eecs.umich.edu } 1226253Sgblack@eecs.umich.edu 1236253Sgblack@eecs.umich.edu /* TODO: Take a look at how these 2 values should meet together 1246253Sgblack@eecs.umich.edu if (start_addr != (end_addr - 4)) 1256253Sgblack@eecs.umich.edu { 1266253Sgblack@eecs.umich.edu fprintf(stderr, "start_addr: %d\n", start_addr); 1276253Sgblack@eecs.umich.edu fprintf(stderr, "end_addr: %d\n", end_addr); 1286253Sgblack@eecs.umich.edu panic("start_addr does not meet end_addr"); 1296253Sgblack@eecs.umich.edu } 1306253Sgblack@eecs.umich.edu */ 1316253Sgblack@eecs.umich.edu 1326253Sgblack@eecs.umich.edu if (writeback) 1336253Sgblack@eecs.umich.edu { 1346253Sgblack@eecs.umich.edu uint32_t newMachInst = machInst & 0xf0000000; 1356253Sgblack@eecs.umich.edu uint32_t rn = (machInst >> 16) & 0x0f; 1366253Sgblack@eecs.umich.edu // 3322 2222 2222 1111 1111 11 1376253Sgblack@eecs.umich.edu // 1098 7654 3210 9876 5432 1098 7654 3210 1386253Sgblack@eecs.umich.edu // COND 0010 0100 [RN] [RD] 0000 [ IMM ] 1396253Sgblack@eecs.umich.edu // sub rn, rn, imm 1406253Sgblack@eecs.umich.edu newMachInst |= 0x02400000; 1416253Sgblack@eecs.umich.edu newMachInst |= ((rn << 16) | (rn << 12)); 1426253Sgblack@eecs.umich.edu newMachInst |= (ones << 2); 1436253Sgblack@eecs.umich.edu if (up) 1446019Shines@cs.fsu.edu { 1456253Sgblack@eecs.umich.edu microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); 1466019Shines@cs.fsu.edu } 1476253Sgblack@eecs.umich.edu else 1486019Shines@cs.fsu.edu { 1496253Sgblack@eecs.umich.edu microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); 1506019Shines@cs.fsu.edu } 1516019Shines@cs.fsu.edu } 1526253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 1536253Sgblack@eecs.umich.edu} 1546019Shines@cs.fsu.edu 1556019Shines@cs.fsu.edu}}; 1566019Shines@cs.fsu.edu 1576019Shines@cs.fsu.edudef template MacroStoreExecute {{ 1586253Sgblack@eecs.umich.eduFault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1596253Sgblack@eecs.umich.edu{ 1606253Sgblack@eecs.umich.edu Fault fault = NoFault; 1616253Sgblack@eecs.umich.edu 1626253Sgblack@eecs.umich.edu %(fp_enable_check)s; 1636253Sgblack@eecs.umich.edu %(op_decl)s; 1646253Sgblack@eecs.umich.edu %(op_rd)s; 1656253Sgblack@eecs.umich.edu %(code)s; 1666253Sgblack@eecs.umich.edu if (fault == NoFault) 1676019Shines@cs.fsu.edu { 1686253Sgblack@eecs.umich.edu %(op_wb)s; 1696253Sgblack@eecs.umich.edu } 1706019Shines@cs.fsu.edu 1716253Sgblack@eecs.umich.edu return fault; 1726253Sgblack@eecs.umich.edu} 1736019Shines@cs.fsu.edu}}; 1746019Shines@cs.fsu.edu 1756019Shines@cs.fsu.edudef template MacroFPAConstructor {{ 1766253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1776253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1786253Sgblack@eecs.umich.edu{ 1796253Sgblack@eecs.umich.edu %(constructor)s; 1806253Sgblack@eecs.umich.edu 1816253Sgblack@eecs.umich.edu uint32_t start_addr = 0; 1826253Sgblack@eecs.umich.edu 1836253Sgblack@eecs.umich.edu if (prepost) 1846253Sgblack@eecs.umich.edu start_addr = disp8; 1856253Sgblack@eecs.umich.edu else 1866253Sgblack@eecs.umich.edu start_addr = 0; 1876253Sgblack@eecs.umich.edu 1886253Sgblack@eecs.umich.edu emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr); 1896253Sgblack@eecs.umich.edu 1906253Sgblack@eecs.umich.edu if (writeback) 1916019Shines@cs.fsu.edu { 1926253Sgblack@eecs.umich.edu uint32_t newMachInst = machInst & 0xf0000000; 1936253Sgblack@eecs.umich.edu uint32_t rn = (machInst >> 16) & 0x0f; 1946253Sgblack@eecs.umich.edu // 3322 2222 2222 1111 1111 11 1956253Sgblack@eecs.umich.edu // 1098 7654 3210 9876 5432 1098 7654 3210 1966253Sgblack@eecs.umich.edu // COND 0010 0100 [RN] [RD] 0000 [ IMM ] 1976253Sgblack@eecs.umich.edu // sub rn, rn, imm 1986253Sgblack@eecs.umich.edu newMachInst |= 0x02400000; 1996253Sgblack@eecs.umich.edu newMachInst |= ((rn << 16) | (rn << 12)); 2006253Sgblack@eecs.umich.edu if (up) 2016253Sgblack@eecs.umich.edu { 2026253Sgblack@eecs.umich.edu newMachInst |= disp8; 2036253Sgblack@eecs.umich.edu microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); 2046253Sgblack@eecs.umich.edu } 2056019Shines@cs.fsu.edu else 2066019Shines@cs.fsu.edu { 2076253Sgblack@eecs.umich.edu newMachInst |= disp8; 2086253Sgblack@eecs.umich.edu microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); 2096019Shines@cs.fsu.edu } 2106019Shines@cs.fsu.edu } 2116253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 2126253Sgblack@eecs.umich.edu} 2136019Shines@cs.fsu.edu 2146019Shines@cs.fsu.edu}}; 2156019Shines@cs.fsu.edu 2166019Shines@cs.fsu.edu 2176019Shines@cs.fsu.edudef template MacroFMConstructor {{ 2186253Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst) 2196253Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 2206253Sgblack@eecs.umich.edu{ 2216253Sgblack@eecs.umich.edu %(constructor)s; 2226253Sgblack@eecs.umich.edu 2236253Sgblack@eecs.umich.edu uint32_t start_addr = 0; 2246253Sgblack@eecs.umich.edu 2256253Sgblack@eecs.umich.edu if (prepost) 2266253Sgblack@eecs.umich.edu start_addr = disp8; 2276253Sgblack@eecs.umich.edu else 2286253Sgblack@eecs.umich.edu start_addr = 0; 2296253Sgblack@eecs.umich.edu 2306253Sgblack@eecs.umich.edu for (int i = 0; i < count; i++) 2316019Shines@cs.fsu.edu { 2326253Sgblack@eecs.umich.edu emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr); 2336019Shines@cs.fsu.edu } 2346019Shines@cs.fsu.edu 2356253Sgblack@eecs.umich.edu if (writeback) 2366253Sgblack@eecs.umich.edu { 2376253Sgblack@eecs.umich.edu uint32_t newMachInst = machInst & 0xf0000000; 2386253Sgblack@eecs.umich.edu uint32_t rn = (machInst >> 16) & 0x0f; 2396253Sgblack@eecs.umich.edu // 3322 2222 2222 1111 1111 11 2406253Sgblack@eecs.umich.edu // 1098 7654 3210 9876 5432 1098 7654 3210 2416253Sgblack@eecs.umich.edu // COND 0010 0100 [RN] [RD] 0000 [ IMM ] 2426253Sgblack@eecs.umich.edu // sub rn, rn, imm 2436253Sgblack@eecs.umich.edu newMachInst |= 0x02400000; 2446253Sgblack@eecs.umich.edu newMachInst |= ((rn << 16) | (rn << 12)); 2456253Sgblack@eecs.umich.edu if (up) 2466253Sgblack@eecs.umich.edu { 2476253Sgblack@eecs.umich.edu newMachInst |= disp8; 2486253Sgblack@eecs.umich.edu microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); 2496253Sgblack@eecs.umich.edu } 2506253Sgblack@eecs.umich.edu else 2516253Sgblack@eecs.umich.edu { 2526253Sgblack@eecs.umich.edu newMachInst |= disp8; 2536253Sgblack@eecs.umich.edu microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); 2546253Sgblack@eecs.umich.edu } 2556253Sgblack@eecs.umich.edu } 2566253Sgblack@eecs.umich.edu microOps[numMicroops-1]->setLastMicroop(); 2576253Sgblack@eecs.umich.edu} 2586019Shines@cs.fsu.edu}}; 2596019Shines@cs.fsu.edu 2606019Shines@cs.fsu.edu 2616019Shines@cs.fsu.edudef format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 2626019Shines@cs.fsu.edu iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags) 2636019Shines@cs.fsu.edu header_output = MacroStoreDeclare.subst(iop) 2646019Shines@cs.fsu.edu decoder_output = MacroStoreConstructor.subst(iop) 2656019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 2666019Shines@cs.fsu.edu exec_output = MacroStoreExecute.subst(iop) 2676019Shines@cs.fsu.edu}}; 2686019Shines@cs.fsu.edu 2696019Shines@cs.fsu.edudef format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 2706243Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'ArmMacroFPAOp', 2716243Sgblack@eecs.umich.edu {"code": code, 2726243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 2736243Sgblack@eecs.umich.edu opt_flags) 2746019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 2756019Shines@cs.fsu.edu decoder_output = MacroFPAConstructor.subst(iop) 2766019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 2776019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 2786019Shines@cs.fsu.edu}}; 2796019Shines@cs.fsu.edu 2806019Shines@cs.fsu.edudef format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 2816243Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'ArmMacroFMOp', 2826243Sgblack@eecs.umich.edu {"code": code, 2836243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 2846243Sgblack@eecs.umich.edu opt_flags) 2856019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 2866019Shines@cs.fsu.edu decoder_output = MacroFMConstructor.subst(iop) 2876019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 2886019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 2896019Shines@cs.fsu.edu}}; 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