macromem.isa revision 6019
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 36019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu// All rights reserved. 56019Shines@cs.fsu.edu// 66019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu// this software without specific prior written permission. 166019Shines@cs.fsu.edu// 176019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// Authors: Stephen Hines 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 326019Shines@cs.fsu.edu// 336019Shines@cs.fsu.edu// Macro Memory-format instructions 346019Shines@cs.fsu.edu// 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.eduoutput header {{ 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.edu /** 396019Shines@cs.fsu.edu * Arm Macro Memory operations like LDM/STM 406019Shines@cs.fsu.edu */ 416019Shines@cs.fsu.edu class ArmMacroMemoryOp : public PredMacroOp 426019Shines@cs.fsu.edu { 436019Shines@cs.fsu.edu protected: 446019Shines@cs.fsu.edu /// Memory request flags. See mem_req_base.hh. 456019Shines@cs.fsu.edu unsigned memAccessFlags; 466019Shines@cs.fsu.edu /// Pointer to EAComp object. 476019Shines@cs.fsu.edu const StaticInstPtr eaCompPtr; 486019Shines@cs.fsu.edu /// Pointer to MemAcc object. 496019Shines@cs.fsu.edu const StaticInstPtr memAccPtr; 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.edu uint32_t reglist; 526019Shines@cs.fsu.edu uint32_t ones; 536019Shines@cs.fsu.edu uint32_t puswl, 546019Shines@cs.fsu.edu prepost, 556019Shines@cs.fsu.edu up, 566019Shines@cs.fsu.edu psruser, 576019Shines@cs.fsu.edu writeback, 586019Shines@cs.fsu.edu loadop; 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.edu ArmMacroMemoryOp(const char *mnem, MachInst _machInst, OpClass __opClass, 616019Shines@cs.fsu.edu StaticInstPtr _eaCompPtr = nullStaticInstPtr, 626019Shines@cs.fsu.edu StaticInstPtr _memAccPtr = nullStaticInstPtr) 636019Shines@cs.fsu.edu : PredMacroOp(mnem, _machInst, __opClass), 646019Shines@cs.fsu.edu memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 656019Shines@cs.fsu.edu reglist(REGLIST), ones(0), puswl(PUSWL), prepost(PREPOST), up(UP), 666019Shines@cs.fsu.edu psruser(PSRUSER), writeback(WRITEBACK), loadop(LOADOP) 676019Shines@cs.fsu.edu { 686019Shines@cs.fsu.edu ones = number_of_ones(reglist); 696019Shines@cs.fsu.edu numMicroops = ones + writeback + 1; 706019Shines@cs.fsu.edu // Remember that writeback adds a uop 716019Shines@cs.fsu.edu microOps = new StaticInstPtr[numMicroops]; 726019Shines@cs.fsu.edu } 736019Shines@cs.fsu.edu }; 746019Shines@cs.fsu.edu 756019Shines@cs.fsu.edu /** 766019Shines@cs.fsu.edu * Arm Macro FPA operations to fix ldfd and stfd instructions 776019Shines@cs.fsu.edu */ 786019Shines@cs.fsu.edu class ArmMacroFPAOp : public PredMacroOp 796019Shines@cs.fsu.edu { 806019Shines@cs.fsu.edu protected: 816019Shines@cs.fsu.edu uint32_t puswl, 826019Shines@cs.fsu.edu prepost, 836019Shines@cs.fsu.edu up, 846019Shines@cs.fsu.edu psruser, 856019Shines@cs.fsu.edu writeback, 866019Shines@cs.fsu.edu loadop; 876019Shines@cs.fsu.edu int32_t disp8; 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu ArmMacroFPAOp(const char *mnem, MachInst _machInst, OpClass __opClass) 906019Shines@cs.fsu.edu : PredMacroOp(mnem, _machInst, __opClass), 916019Shines@cs.fsu.edu puswl(PUSWL), prepost(PREPOST), up(UP), 926019Shines@cs.fsu.edu psruser(PSRUSER), writeback(WRITEBACK), loadop(LOADOP), 936019Shines@cs.fsu.edu disp8(IMMED_7_0 << 2) 946019Shines@cs.fsu.edu { 956019Shines@cs.fsu.edu numMicroops = 3 + writeback; 966019Shines@cs.fsu.edu microOps = new StaticInstPtr[numMicroops]; 976019Shines@cs.fsu.edu } 986019Shines@cs.fsu.edu }; 996019Shines@cs.fsu.edu 1006019Shines@cs.fsu.edu /** 1016019Shines@cs.fsu.edu * Arm Macro FM operations to fix lfm and sfm 1026019Shines@cs.fsu.edu */ 1036019Shines@cs.fsu.edu class ArmMacroFMOp : public PredMacroOp 1046019Shines@cs.fsu.edu { 1056019Shines@cs.fsu.edu protected: 1066019Shines@cs.fsu.edu uint32_t punwl, 1076019Shines@cs.fsu.edu prepost, 1086019Shines@cs.fsu.edu up, 1096019Shines@cs.fsu.edu n1bit, 1106019Shines@cs.fsu.edu writeback, 1116019Shines@cs.fsu.edu loadop, 1126019Shines@cs.fsu.edu n0bit, 1136019Shines@cs.fsu.edu count; 1146019Shines@cs.fsu.edu int32_t disp8; 1156019Shines@cs.fsu.edu 1166019Shines@cs.fsu.edu ArmMacroFMOp(const char *mnem, MachInst _machInst, OpClass __opClass) 1176019Shines@cs.fsu.edu : PredMacroOp(mnem, _machInst, __opClass), 1186019Shines@cs.fsu.edu punwl(PUNWL), prepost(PREPOST), up(UP), 1196019Shines@cs.fsu.edu n1bit(OPCODE_22), writeback(WRITEBACK), loadop(LOADOP), 1206019Shines@cs.fsu.edu n0bit(OPCODE_15), disp8(IMMED_7_0 << 2) 1216019Shines@cs.fsu.edu { 1226019Shines@cs.fsu.edu // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4) 1236019Shines@cs.fsu.edu count = (n1bit << 1) | n0bit; 1246019Shines@cs.fsu.edu if (count == 0) 1256019Shines@cs.fsu.edu count = 4; 1266019Shines@cs.fsu.edu numMicroops = (3*count) + writeback; 1276019Shines@cs.fsu.edu microOps = new StaticInstPtr[numMicroops]; 1286019Shines@cs.fsu.edu } 1296019Shines@cs.fsu.edu }; 1306019Shines@cs.fsu.edu 1316019Shines@cs.fsu.edu 1326019Shines@cs.fsu.edu}}; 1336019Shines@cs.fsu.edu 1346019Shines@cs.fsu.edu 1356019Shines@cs.fsu.eduoutput decoder {{ 1366019Shines@cs.fsu.edu}}; 1376019Shines@cs.fsu.edu 1386019Shines@cs.fsu.edudef template MacroStoreDeclare {{ 1396019Shines@cs.fsu.edu /** 1406019Shines@cs.fsu.edu * Static instructions class for a store multiple instruction 1416019Shines@cs.fsu.edu */ 1426019Shines@cs.fsu.edu class %(class_name)s : public %(base_class)s 1436019Shines@cs.fsu.edu { 1446019Shines@cs.fsu.edu public: 1456019Shines@cs.fsu.edu // Constructor 1466019Shines@cs.fsu.edu %(class_name)s(MachInst machInst); 1476019Shines@cs.fsu.edu %(BasicExecDeclare)s 1486019Shines@cs.fsu.edu }; 1496019Shines@cs.fsu.edu}}; 1506019Shines@cs.fsu.edu 1516019Shines@cs.fsu.edudef template MacroStoreConstructor {{ 1526019Shines@cs.fsu.edu inline %(class_name)s::%(class_name)s(MachInst machInst) 1536019Shines@cs.fsu.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1546019Shines@cs.fsu.edu { 1556019Shines@cs.fsu.edu %(constructor)s; 1566019Shines@cs.fsu.edu uint32_t regs_to_handle = reglist; 1576019Shines@cs.fsu.edu uint32_t j = 0, 1586019Shines@cs.fsu.edu start_addr = 0, 1596019Shines@cs.fsu.edu end_addr = 0; 1606019Shines@cs.fsu.edu 1616019Shines@cs.fsu.edu switch (puswl) 1626019Shines@cs.fsu.edu { 1636019Shines@cs.fsu.edu case 0x01: // L ldmda_l 1646019Shines@cs.fsu.edu start_addr = (ones << 2) - 4; 1656019Shines@cs.fsu.edu end_addr = 0; 1666019Shines@cs.fsu.edu break; 1676019Shines@cs.fsu.edu case 0x03: // WL ldmda_wl 1686019Shines@cs.fsu.edu start_addr = (ones << 2) - 4; 1696019Shines@cs.fsu.edu end_addr = 0; 1706019Shines@cs.fsu.edu break; 1716019Shines@cs.fsu.edu case 0x08: // U stmia_u 1726019Shines@cs.fsu.edu start_addr = 0; 1736019Shines@cs.fsu.edu end_addr = (ones << 2) - 4; 1746019Shines@cs.fsu.edu break; 1756019Shines@cs.fsu.edu case 0x09: // U L ldmia_ul 1766019Shines@cs.fsu.edu start_addr = 0; 1776019Shines@cs.fsu.edu end_addr = (ones << 2) - 4; 1786019Shines@cs.fsu.edu break; 1796019Shines@cs.fsu.edu case 0x0b: // U WL ldmia 1806019Shines@cs.fsu.edu start_addr = 0; 1816019Shines@cs.fsu.edu end_addr = (ones << 2) - 4; 1826019Shines@cs.fsu.edu break; 1836019Shines@cs.fsu.edu case 0x11: // P L ldmdb 1846019Shines@cs.fsu.edu start_addr = (ones << 2); // U-bit is already 0 for subtract 1856019Shines@cs.fsu.edu end_addr = 4; // negative 4 1866019Shines@cs.fsu.edu break; 1876019Shines@cs.fsu.edu case 0x12: // P W stmdb 1886019Shines@cs.fsu.edu start_addr = (ones << 2); // U-bit is already 0 for subtract 1896019Shines@cs.fsu.edu end_addr = 4; // negative 4 1906019Shines@cs.fsu.edu break; 1916019Shines@cs.fsu.edu case 0x18: // PU stmib 1926019Shines@cs.fsu.edu start_addr = 4; 1936019Shines@cs.fsu.edu end_addr = (ones << 2) + 4; 1946019Shines@cs.fsu.edu break; 1956019Shines@cs.fsu.edu case 0x19: // PU L ldmib 1966019Shines@cs.fsu.edu start_addr = 4; 1976019Shines@cs.fsu.edu end_addr = (ones << 2) + 4; 1986019Shines@cs.fsu.edu break; 1996019Shines@cs.fsu.edu default: 2006019Shines@cs.fsu.edu panic("Unhandled Load/Store Multiple Instruction"); 2016019Shines@cs.fsu.edu break; 2026019Shines@cs.fsu.edu } 2036019Shines@cs.fsu.edu 2046019Shines@cs.fsu.edu //TODO - Add addi_uop/subi_uop here to create starting addresses 2056019Shines@cs.fsu.edu //Just using addi with 0 offset makes a "copy" of Rn for our use 2066019Shines@cs.fsu.edu uint32_t newMachInst = 0; 2076019Shines@cs.fsu.edu newMachInst = machInst & 0xffff0000; 2086019Shines@cs.fsu.edu microOps[0] = new Addi_uop(newMachInst); 2096019Shines@cs.fsu.edu 2106019Shines@cs.fsu.edu for (int i = 1; i < ones+1; i++) 2116019Shines@cs.fsu.edu { 2126019Shines@cs.fsu.edu // Get next available bit for transfer 2136019Shines@cs.fsu.edu while (! ( regs_to_handle & (1<<j))) 2146019Shines@cs.fsu.edu j++; 2156019Shines@cs.fsu.edu regs_to_handle &= ~(1<<j); 2166019Shines@cs.fsu.edu 2176019Shines@cs.fsu.edu microOps[i] = gen_ldrstr_uop(machInst, loadop, j, start_addr); 2186019Shines@cs.fsu.edu 2196019Shines@cs.fsu.edu if (up) 2206019Shines@cs.fsu.edu start_addr += 4; 2216019Shines@cs.fsu.edu else 2226019Shines@cs.fsu.edu start_addr -= 4; 2236019Shines@cs.fsu.edu } 2246019Shines@cs.fsu.edu 2256019Shines@cs.fsu.edu /* TODO: Take a look at how these 2 values should meet together 2266019Shines@cs.fsu.edu if (start_addr != (end_addr - 4)) 2276019Shines@cs.fsu.edu { 2286019Shines@cs.fsu.edu fprintf(stderr, "start_addr: %d\n", start_addr); 2296019Shines@cs.fsu.edu fprintf(stderr, "end_addr: %d\n", end_addr); 2306019Shines@cs.fsu.edu panic("start_addr does not meet end_addr"); 2316019Shines@cs.fsu.edu } 2326019Shines@cs.fsu.edu */ 2336019Shines@cs.fsu.edu 2346019Shines@cs.fsu.edu if (writeback) 2356019Shines@cs.fsu.edu { 2366019Shines@cs.fsu.edu uint32_t newMachInst = machInst & 0xf0000000; 2376019Shines@cs.fsu.edu uint32_t rn = (machInst >> 16) & 0x0f; 2386019Shines@cs.fsu.edu // 3322 2222 2222 1111 1111 11 2396019Shines@cs.fsu.edu // 1098 7654 3210 9876 5432 1098 7654 3210 2406019Shines@cs.fsu.edu // COND 0010 0100 [RN] [RD] 0000 [ IMM ] 2416019Shines@cs.fsu.edu // sub rn, rn, imm 2426019Shines@cs.fsu.edu newMachInst |= 0x02400000; 2436019Shines@cs.fsu.edu newMachInst |= ((rn << 16) | (rn << 12)); 2446019Shines@cs.fsu.edu newMachInst |= (ones << 2); 2456019Shines@cs.fsu.edu if (up) 2466019Shines@cs.fsu.edu { 2476019Shines@cs.fsu.edu microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); 2486019Shines@cs.fsu.edu } 2496019Shines@cs.fsu.edu else 2506019Shines@cs.fsu.edu { 2516019Shines@cs.fsu.edu microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); 2526019Shines@cs.fsu.edu } 2536019Shines@cs.fsu.edu } 2546019Shines@cs.fsu.edu microOps[numMicroops-1]->setLastMicroop(); 2556019Shines@cs.fsu.edu } 2566019Shines@cs.fsu.edu 2576019Shines@cs.fsu.edu}}; 2586019Shines@cs.fsu.edu 2596019Shines@cs.fsu.edudef template MacroStoreExecute {{ 2606019Shines@cs.fsu.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2616019Shines@cs.fsu.edu { 2626019Shines@cs.fsu.edu Fault fault = NoFault; 2636019Shines@cs.fsu.edu 2646019Shines@cs.fsu.edu %(fp_enable_check)s; 2656019Shines@cs.fsu.edu %(op_decl)s; 2666019Shines@cs.fsu.edu %(op_rd)s; 2676019Shines@cs.fsu.edu %(code)s; 2686019Shines@cs.fsu.edu if (fault == NoFault) 2696019Shines@cs.fsu.edu { 2706019Shines@cs.fsu.edu %(op_wb)s; 2716019Shines@cs.fsu.edu } 2726019Shines@cs.fsu.edu 2736019Shines@cs.fsu.edu return fault; 2746019Shines@cs.fsu.edu } 2756019Shines@cs.fsu.edu}}; 2766019Shines@cs.fsu.edu 2776019Shines@cs.fsu.edudef template MacroFPAConstructor {{ 2786019Shines@cs.fsu.edu inline %(class_name)s::%(class_name)s(MachInst machInst) 2796019Shines@cs.fsu.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 2806019Shines@cs.fsu.edu { 2816019Shines@cs.fsu.edu %(constructor)s; 2826019Shines@cs.fsu.edu 2836019Shines@cs.fsu.edu uint32_t start_addr = 0; 2846019Shines@cs.fsu.edu 2856019Shines@cs.fsu.edu if (prepost) 2866019Shines@cs.fsu.edu start_addr = disp8; 2876019Shines@cs.fsu.edu else 2886019Shines@cs.fsu.edu start_addr = 0; 2896019Shines@cs.fsu.edu 2906019Shines@cs.fsu.edu emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr); 2916019Shines@cs.fsu.edu 2926019Shines@cs.fsu.edu if (writeback) 2936019Shines@cs.fsu.edu { 2946019Shines@cs.fsu.edu uint32_t newMachInst = machInst & 0xf0000000; 2956019Shines@cs.fsu.edu uint32_t rn = (machInst >> 16) & 0x0f; 2966019Shines@cs.fsu.edu // 3322 2222 2222 1111 1111 11 2976019Shines@cs.fsu.edu // 1098 7654 3210 9876 5432 1098 7654 3210 2986019Shines@cs.fsu.edu // COND 0010 0100 [RN] [RD] 0000 [ IMM ] 2996019Shines@cs.fsu.edu // sub rn, rn, imm 3006019Shines@cs.fsu.edu newMachInst |= 0x02400000; 3016019Shines@cs.fsu.edu newMachInst |= ((rn << 16) | (rn << 12)); 3026019Shines@cs.fsu.edu if (up) 3036019Shines@cs.fsu.edu { 3046019Shines@cs.fsu.edu newMachInst |= disp8; 3056019Shines@cs.fsu.edu microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); 3066019Shines@cs.fsu.edu } 3076019Shines@cs.fsu.edu else 3086019Shines@cs.fsu.edu { 3096019Shines@cs.fsu.edu newMachInst |= disp8; 3106019Shines@cs.fsu.edu microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); 3116019Shines@cs.fsu.edu } 3126019Shines@cs.fsu.edu } 3136019Shines@cs.fsu.edu microOps[numMicroops-1]->setLastMicroop(); 3146019Shines@cs.fsu.edu } 3156019Shines@cs.fsu.edu 3166019Shines@cs.fsu.edu}}; 3176019Shines@cs.fsu.edu 3186019Shines@cs.fsu.edu 3196019Shines@cs.fsu.edudef template MacroFMConstructor {{ 3206019Shines@cs.fsu.edu inline %(class_name)s::%(class_name)s(MachInst machInst) 3216019Shines@cs.fsu.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 3226019Shines@cs.fsu.edu { 3236019Shines@cs.fsu.edu %(constructor)s; 3246019Shines@cs.fsu.edu 3256019Shines@cs.fsu.edu uint32_t start_addr = 0; 3266019Shines@cs.fsu.edu 3276019Shines@cs.fsu.edu if (prepost) 3286019Shines@cs.fsu.edu start_addr = disp8; 3296019Shines@cs.fsu.edu else 3306019Shines@cs.fsu.edu start_addr = 0; 3316019Shines@cs.fsu.edu 3326019Shines@cs.fsu.edu for (int i = 0; i < count; i++) 3336019Shines@cs.fsu.edu { 3346019Shines@cs.fsu.edu emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr); 3356019Shines@cs.fsu.edu } 3366019Shines@cs.fsu.edu 3376019Shines@cs.fsu.edu if (writeback) 3386019Shines@cs.fsu.edu { 3396019Shines@cs.fsu.edu uint32_t newMachInst = machInst & 0xf0000000; 3406019Shines@cs.fsu.edu uint32_t rn = (machInst >> 16) & 0x0f; 3416019Shines@cs.fsu.edu // 3322 2222 2222 1111 1111 11 3426019Shines@cs.fsu.edu // 1098 7654 3210 9876 5432 1098 7654 3210 3436019Shines@cs.fsu.edu // COND 0010 0100 [RN] [RD] 0000 [ IMM ] 3446019Shines@cs.fsu.edu // sub rn, rn, imm 3456019Shines@cs.fsu.edu newMachInst |= 0x02400000; 3466019Shines@cs.fsu.edu newMachInst |= ((rn << 16) | (rn << 12)); 3476019Shines@cs.fsu.edu if (up) 3486019Shines@cs.fsu.edu { 3496019Shines@cs.fsu.edu newMachInst |= disp8; 3506019Shines@cs.fsu.edu microOps[numMicroops-1] = new Addi_rd_uop(newMachInst); 3516019Shines@cs.fsu.edu } 3526019Shines@cs.fsu.edu else 3536019Shines@cs.fsu.edu { 3546019Shines@cs.fsu.edu newMachInst |= disp8; 3556019Shines@cs.fsu.edu microOps[numMicroops-1] = new Subi_rd_uop(newMachInst); 3566019Shines@cs.fsu.edu } 3576019Shines@cs.fsu.edu } 3586019Shines@cs.fsu.edu microOps[numMicroops-1]->setLastMicroop(); 3596019Shines@cs.fsu.edu } 3606019Shines@cs.fsu.edu 3616019Shines@cs.fsu.edu}}; 3626019Shines@cs.fsu.edu 3636019Shines@cs.fsu.edu 3646019Shines@cs.fsu.edudef format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 3656019Shines@cs.fsu.edu iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags) 3666019Shines@cs.fsu.edu header_output = MacroStoreDeclare.subst(iop) 3676019Shines@cs.fsu.edu decoder_output = MacroStoreConstructor.subst(iop) 3686019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 3696019Shines@cs.fsu.edu exec_output = MacroStoreExecute.subst(iop) 3706019Shines@cs.fsu.edu}}; 3716019Shines@cs.fsu.edu 3726019Shines@cs.fsu.edudef format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 3736019Shines@cs.fsu.edu iop = InstObjParams(name, Name, 'ArmMacroFPAOp', code, opt_flags) 3746019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 3756019Shines@cs.fsu.edu decoder_output = MacroFPAConstructor.subst(iop) 3766019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 3776019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 3786019Shines@cs.fsu.edu}}; 3796019Shines@cs.fsu.edu 3806019Shines@cs.fsu.edudef format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ 3816019Shines@cs.fsu.edu iop = InstObjParams(name, Name, 'ArmMacroFMOp', code, opt_flags) 3826019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 3836019Shines@cs.fsu.edu decoder_output = MacroFMConstructor.subst(iop) 3846019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 3856019Shines@cs.fsu.edu exec_output = PredOpExecute.subst(iop) 3866019Shines@cs.fsu.edu}}; 3876019Shines@cs.fsu.edu 3886019Shines@cs.fsu.edu 3896019Shines@cs.fsu.edu 390