xref: /gem5/src/arch/arm/isa/formats/m5ops.isa

//
// Copyright (c) 2010 ARM Limited
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// Authors: Gene Wu
///

def format M5ops() {{
    decode_block = '''
    {
        const uint32_t m5func = bits(machInst, 23, 16);
        switch(m5func) {
            case M5OP_ARM: return new Arm(machInst);
            case M5OP_QUIESCE: return new Quiesce(machInst);
            case M5OP_QUIESCE_NS: return new QuiesceNs(machInst);
            case M5OP_QUIESCE_CYCLE: return new QuiesceCycles(machInst);
            case M5OP_QUIESCE_TIME: return new QuiesceTime(machInst);
            case M5OP_RPNS: return new Rpns(machInst);
            case M5OP_WAKE_CPU: return new WakeCPU(machInst);
            case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
            case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
            case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
            case M5OP_EXIT: return new M5exit(machInst);
            case M5OP_FAIL: return new M5fail(machInst);
            case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
            case M5OP_INIT_PARAM: return new Initparam(machInst);
            case M5OP_RESET_STATS: return new Resetstats(machInst);
            case M5OP_DUMP_STATS: return new Dumpstats(machInst);
            case M5OP_DUMP_RESET_STATS: return new Dumpresetstats(machInst);
            case M5OP_CHECKPOINT: return new M5checkpoint(machInst);
            case M5OP_WRITE_FILE: return new M5writefile(machInst);
            case M5OP_READ_FILE: return new M5readfile(machInst);
            case M5OP_DEBUG_BREAK: return new M5break(machInst);
            case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
            case M5OP_ADD_SYMBOL: return new M5addsymbol(machInst);
            case M5OP_PANIC: return new M5panic(machInst);
            case M5OP_WORK_BEGIN: return new M5workbegin(machInst);
            case M5OP_WORK_END: return new M5workend(machInst);
        }
   }
   '''
}};