fp.isa revision 7389:714dea5b5298
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Floating Point operate instructions 46// 47 48def template FPAExecute {{ 49 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 50 { 51 Fault fault = NoFault; 52 53 %(fp_enable_check)s; 54 55 %(op_decl)s; 56 %(op_rd)s; 57 58 if (%(predicate_test)s) { 59 %(code)s; 60 if (fault == NoFault) { 61 %(op_wb)s; 62 } 63 } 64 65 return fault; 66 } 67}}; 68 69def template FloatDoubleDecode {{ 70 { 71 ArmStaticInst *i = NULL; 72 switch (OPCODE_19 << 1 | OPCODE_7) 73 { 74 case 0: 75 i = (ArmStaticInst *)new %(class_name)sS(machInst); 76 break; 77 case 1: 78 i = (ArmStaticInst *)new %(class_name)sD(machInst); 79 break; 80 case 2: 81 case 3: 82 default: 83 panic("Cannot decode float/double nature of the instruction"); 84 } 85 return i; 86 } 87}}; 88 89// Primary format for float point operate instructions: 90def format FloatOp(code, *flags) {{ 91 orig_code = code 92 93 cblk = code 94 iop = InstObjParams(name, Name, 'PredOp', 95 {"code": cblk, 96 "predicate_test": predicateTest}, 97 flags) 98 header_output = BasicDeclare.subst(iop) 99 decoder_output = BasicConstructor.subst(iop) 100 exec_output = FPAExecute.subst(iop) 101 102 sng_cblk = code 103 sng_iop = InstObjParams(name, Name+'S', 'PredOp', 104 {"code": sng_cblk, 105 "predicate_test": predicateTest}, 106 flags) 107 header_output += BasicDeclare.subst(sng_iop) 108 decoder_output += BasicConstructor.subst(sng_iop) 109 exec_output += FPAExecute.subst(sng_iop) 110 111 dbl_code = re.sub(r'\.sf', '.df', orig_code) 112 113 dbl_cblk = dbl_code 114 dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 115 {"code": dbl_cblk, 116 "predicate_test": predicateTest}, 117 flags) 118 header_output += BasicDeclare.subst(dbl_iop) 119 decoder_output += BasicConstructor.subst(dbl_iop) 120 exec_output += FPAExecute.subst(dbl_iop) 121 122 decode_block = FloatDoubleDecode.subst(iop) 123}}; 124 125let {{ 126 calcFPCcCode = ''' 127 uint16_t _in, _iz, _ic, _iv; 128 129 _in = %(fReg1)s < %(fReg2)s; 130 _iz = %(fReg1)s == %(fReg2)s; 131 _ic = %(fReg1)s >= %(fReg2)s; 132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 133 134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 135 (CondCodes & 0x0FFFFFFF); 136 ''' 137}}; 138 139def format FloatCmp(fReg1, fReg2, *flags) {{ 140 code = calcFPCcCode % vars() 141 iop = InstObjParams(name, Name, 'PredOp', 142 {"code": code, 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 151let {{ 152 header_output = ''' 153 StaticInstPtr 154 decodeExtensionRegLoadStore(ExtMachInst machInst); 155 ''' 156 decoder_output = ''' 157 StaticInstPtr 158 decodeExtensionRegLoadStore(ExtMachInst machInst) 159 { 160 const uint32_t opcode = bits(machInst, 24, 20); 161 const uint32_t offset = bits(machInst, 7, 0); 162 const bool single = (bits(machInst, 8) == 0); 163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 164 RegIndex vd; 165 if (single) { 166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 167 bits(machInst, 22)); 168 } else { 169 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 170 (bits(machInst, 22) << 5)); 171 } 172 switch (bits(opcode, 4, 3)) { 173 case 0x0: 174 if (bits(opcode, 4, 1) == 0x2 && 175 !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 176 !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 177 if ((bits(machInst, 7, 4) & 0xd) != 1) { 178 break; 179 } 180 const IntRegIndex rt = 181 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 182 const IntRegIndex rt2 = 183 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 184 const bool op = bits(machInst, 20); 185 uint32_t vm; 186 if (single) { 187 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 188 } else { 189 vm = (bits(machInst, 3, 0) << 1) | 190 (bits(machInst, 5) << 5); 191 } 192 if (op) { 193 return new Vmov2Core2Reg(machInst, rt, rt2, 194 (IntRegIndex)vm); 195 } else { 196 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 197 rt, rt2); 198 } 199 } 200 break; 201 case 0x1: 202 switch (bits(opcode, 1, 0)) { 203 case 0x0: 204 return new VLdmStm(machInst, rn, vd, single, 205 true, false, false, offset); 206 case 0x1: 207 return new VLdmStm(machInst, rn, vd, single, 208 true, false, true, offset); 209 case 0x2: 210 return new VLdmStm(machInst, rn, vd, single, 211 true, true, false, offset); 212 case 0x3: 213 // If rn == sp, then this is called vpop. 214 return new VLdmStm(machInst, rn, vd, single, 215 true, true, true, offset); 216 } 217 case 0x2: 218 if (bits(opcode, 1, 0) == 0x2) { 219 // If rn == sp, then this is called vpush. 220 return new VLdmStm(machInst, rn, vd, single, 221 false, true, false, offset); 222 } else if (bits(opcode, 1, 0) == 0x3) { 223 return new VLdmStm(machInst, rn, vd, single, 224 false, true, true, offset); 225 } 226 // Fall through on purpose 227 case 0x3: 228 const bool up = (bits(machInst, 23) == 1); 229 const uint32_t imm = bits(machInst, 7, 0) << 2; 230 RegIndex vd; 231 if (single) { 232 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 233 (bits(machInst, 22))); 234 } else { 235 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 236 (bits(machInst, 22) << 5)); 237 } 238 if (bits(opcode, 1, 0) == 0x0) { 239 if (single) { 240 if (up) { 241 return new %(vstr_us)s(machInst, vd, rn, up, imm); 242 } else { 243 return new %(vstr_s)s(machInst, vd, rn, up, imm); 244 } 245 } else { 246 if (up) { 247 return new %(vstr_ud)s(machInst, vd, vd + 1, 248 rn, up, imm); 249 } else { 250 return new %(vstr_d)s(machInst, vd, vd + 1, 251 rn, up, imm); 252 } 253 } 254 } else if (bits(opcode, 1, 0) == 0x1) { 255 if (single) { 256 if (up) { 257 return new %(vldr_us)s(machInst, vd, rn, up, imm); 258 } else { 259 return new %(vldr_s)s(machInst, vd, rn, up, imm); 260 } 261 } else { 262 if (up) { 263 return new %(vldr_ud)s(machInst, vd, vd + 1, 264 rn, up, imm); 265 } else { 266 return new %(vldr_d)s(machInst, vd, vd + 1, 267 rn, up, imm); 268 } 269 } 270 } 271 } 272 return new Unknown(machInst); 273 } 274 ''' % { 275 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 276 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 277 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 283 } 284}}; 285 286def format ExtensionRegLoadStore() {{ 287 decode_block = ''' 288 return decodeExtensionRegLoadStore(machInst); 289 ''' 290}}; 291 292let {{ 293 header_output = ''' 294 StaticInstPtr 295 decodeShortFpTransfer(ExtMachInst machInst); 296 ''' 297 decoder_output = ''' 298 StaticInstPtr 299 decodeShortFpTransfer(ExtMachInst machInst) 300 { 301 const uint32_t l = bits(machInst, 20); 302 const uint32_t c = bits(machInst, 8); 303 const uint32_t a = bits(machInst, 23, 21); 304 const uint32_t b = bits(machInst, 6, 5); 305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 306 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 307 return new Unknown(machInst); 308 } 309 if (l == 0 && c == 0) { 310 if (a == 0) { 311 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 312 bits(machInst, 7); 313 const IntRegIndex rt = 314 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 315 if (bits(machInst, 20) == 1) { 316 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 317 } else { 318 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 319 } 320 } else if (a == 0x7) { 321 const IntRegIndex rt = 322 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 323 uint32_t specReg = bits(machInst, 19, 16); 324 switch (specReg) { 325 case 0: 326 specReg = MISCREG_FPSID; 327 break; 328 case 1: 329 specReg = MISCREG_FPSCR; 330 break; 331 case 8: 332 specReg = MISCREG_FPEXC; 333 break; 334 default: 335 return new Unknown(machInst); 336 } 337 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 338 } 339 } else if (l == 0 && c == 1) { 340 if (bits(a, 2) == 0) { 341 uint32_t vd = (bits(machInst, 7) << 5) | 342 (bits(machInst, 19, 16) << 1); 343 uint32_t index, size; 344 const IntRegIndex rt = 345 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 346 if (bits(machInst, 22) == 1) { 347 size = 8; 348 index = (bits(machInst, 21) << 2) | 349 bits(machInst, 6, 5); 350 } else if (bits(machInst, 5) == 1) { 351 size = 16; 352 index = (bits(machInst, 21) << 1) | 353 bits(machInst, 6); 354 } else if (bits(machInst, 6) == 0) { 355 size = 32; 356 index = bits(machInst, 21); 357 } else { 358 return new Unknown(machInst); 359 } 360 if (index >= (32 / size)) { 361 index -= (32 / size); 362 vd++; 363 } 364 switch (size) { 365 case 8: 366 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 367 rt, index); 368 case 16: 369 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 370 rt, index); 371 case 32: 372 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 373 } 374 } else if (bits(b, 1) == 0) { 375 // A8-594 376 return new WarnUnimplemented("vdup", machInst); 377 } 378 } else if (l == 1 && c == 0) { 379 if (a == 0) { 380 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 381 bits(machInst, 7); 382 const IntRegIndex rt = 383 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 384 if (bits(machInst, 20) == 1) { 385 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 386 } else { 387 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 388 } 389 } else if (a == 7) { 390 const IntRegIndex rt = 391 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 392 uint32_t specReg = bits(machInst, 19, 16); 393 switch (specReg) { 394 case 0: 395 specReg = MISCREG_FPSID; 396 break; 397 case 1: 398 specReg = MISCREG_FPSCR; 399 break; 400 case 6: 401 specReg = MISCREG_MVFR1; 402 break; 403 case 7: 404 specReg = MISCREG_MVFR0; 405 break; 406 case 8: 407 specReg = MISCREG_FPEXC; 408 break; 409 default: 410 return new Unknown(machInst); 411 } 412 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 413 } 414 } else { 415 uint32_t vd = (bits(machInst, 7) << 5) | 416 (bits(machInst, 19, 16) << 1); 417 uint32_t index, size; 418 const IntRegIndex rt = 419 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 420 const bool u = (bits(machInst, 23) == 1); 421 if (bits(machInst, 22) == 1) { 422 size = 8; 423 index = (bits(machInst, 21) << 2) | 424 bits(machInst, 6, 5); 425 } else if (bits(machInst, 5) == 1) { 426 size = 16; 427 index = (bits(machInst, 21) << 1) | 428 bits(machInst, 6); 429 } else if (bits(machInst, 6) == 0 && !u) { 430 size = 32; 431 index = bits(machInst, 21); 432 } else { 433 return new Unknown(machInst); 434 } 435 if (index >= (32 / size)) { 436 index -= (32 / size); 437 vd++; 438 } 439 switch (size) { 440 case 8: 441 if (u) { 442 return new VmovRegCoreUB(machInst, rt, 443 (IntRegIndex)vd, index); 444 } else { 445 return new VmovRegCoreSB(machInst, rt, 446 (IntRegIndex)vd, index); 447 } 448 case 16: 449 if (u) { 450 return new VmovRegCoreUH(machInst, rt, 451 (IntRegIndex)vd, index); 452 } else { 453 return new VmovRegCoreSH(machInst, rt, 454 (IntRegIndex)vd, index); 455 } 456 case 32: 457 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 458 } 459 } 460 return new Unknown(machInst); 461 } 462 ''' 463}}; 464 465def format ShortFpTransfer() {{ 466 decode_block = ''' 467 return decodeShortFpTransfer(machInst); 468 ''' 469}}; 470 471let {{ 472 header_output = ''' 473 StaticInstPtr 474 decodeVfpData(ExtMachInst machInst); 475 ''' 476 decoder_output = ''' 477 StaticInstPtr 478 decodeVfpData(ExtMachInst machInst) 479 { 480 const uint32_t opc1 = bits(machInst, 23, 20); 481 const uint32_t opc2 = bits(machInst, 19, 16); 482 const uint32_t opc3 = bits(machInst, 7, 6); 483 //const uint32_t opc4 = bits(machInst, 3, 0); 484 const bool single = (bits(machInst, 8) == 0); 485 // Used to select between vcmp and vcmpe. 486 const bool e = (bits(machInst, 7) == 1); 487 IntRegIndex vd; 488 IntRegIndex vm; 489 IntRegIndex vn; 490 if (single) { 491 vd = (IntRegIndex)(bits(machInst, 22) | 492 (bits(machInst, 15, 12) << 1)); 493 vm = (IntRegIndex)(bits(machInst, 5) | 494 (bits(machInst, 3, 0) << 1)); 495 vn = (IntRegIndex)(bits(machInst, 7) | 496 (bits(machInst, 19, 16) << 1)); 497 } else { 498 vd = (IntRegIndex)((bits(machInst, 22) << 5) | 499 (bits(machInst, 15, 12) << 1)); 500 vm = (IntRegIndex)((bits(machInst, 5) << 5) | 501 (bits(machInst, 3, 0) << 1)); 502 vn = (IntRegIndex)((bits(machInst, 7) << 5) | 503 (bits(machInst, 19, 16) << 1)); 504 } 505 switch (opc1 & 0xb /* 1011 */) { 506 case 0x0: 507 if (bits(machInst, 6) == 0) { 508 if (single) { 509 return decodeVfpRegRegRegOp<VmlaS>( 510 machInst, vd, vn, vm, false); 511 } else { 512 return decodeVfpRegRegRegOp<VmlaD>( 513 machInst, vd, vn, vm, true); 514 } 515 } else { 516 if (single) { 517 return decodeVfpRegRegRegOp<VmlsS>( 518 machInst, vd, vn, vm, false); 519 } else { 520 return decodeVfpRegRegRegOp<VmlsD>( 521 machInst, vd, vn, vm, true); 522 } 523 } 524 case 0x1: 525 if (bits(machInst, 6) == 1) { 526 if (single) { 527 return decodeVfpRegRegRegOp<VnmlaS>( 528 machInst, vd, vn, vm, false); 529 } else { 530 return decodeVfpRegRegRegOp<VnmlaD>( 531 machInst, vd, vn, vm, true); 532 } 533 } else { 534 if (single) { 535 return decodeVfpRegRegRegOp<VnmlsS>( 536 machInst, vd, vn, vm, false); 537 } else { 538 return decodeVfpRegRegRegOp<VnmlsD>( 539 machInst, vd, vn, vm, true); 540 } 541 } 542 case 0x2: 543 if ((opc3 & 0x1) == 0) { 544 if (single) { 545 return decodeVfpRegRegRegOp<VmulS>( 546 machInst, vd, vn, vm, false); 547 } else { 548 return decodeVfpRegRegRegOp<VmulD>( 549 machInst, vd, vn, vm, true); 550 } 551 } else { 552 if (single) { 553 return decodeVfpRegRegRegOp<VnmulS>( 554 machInst, vd, vn, vm, false); 555 } else { 556 return decodeVfpRegRegRegOp<VnmulD>( 557 machInst, vd, vn, vm, true); 558 } 559 } 560 case 0x3: 561 if ((opc3 & 0x1) == 0) { 562 if (single) { 563 return decodeVfpRegRegRegOp<VaddS>( 564 machInst, vd, vn, vm, false); 565 } else { 566 return decodeVfpRegRegRegOp<VaddD>( 567 machInst, vd, vn, vm, true); 568 } 569 } else { 570 if (single) { 571 return decodeVfpRegRegRegOp<VsubS>( 572 machInst, vd, vn, vm, false); 573 } else { 574 return decodeVfpRegRegRegOp<VsubD>( 575 machInst, vd, vn, vm, true); 576 } 577 } 578 case 0x8: 579 if ((opc3 & 0x1) == 0) { 580 if (single) { 581 return decodeVfpRegRegRegOp<VdivS>( 582 machInst, vd, vn, vm, false); 583 } else { 584 return decodeVfpRegRegRegOp<VdivD>( 585 machInst, vd, vn, vm, true); 586 } 587 } 588 break; 589 case 0xb: 590 if ((opc3 & 0x1) == 0) { 591 const uint32_t baseImm = 592 bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 593 if (single) { 594 uint32_t imm = vfp_modified_imm(baseImm, false); 595 return decodeVfpRegImmOp<VmovImmS>( 596 machInst, vd, imm, false); 597 } else { 598 uint64_t imm = vfp_modified_imm(baseImm, true); 599 return decodeVfpRegImmOp<VmovImmD>( 600 machInst, vd, imm, true); 601 } 602 } 603 switch (opc2) { 604 case 0x0: 605 if (opc3 == 1) { 606 if (single) { 607 return decodeVfpRegRegOp<VmovRegS>( 608 machInst, vd, vm, false); 609 } else { 610 return decodeVfpRegRegOp<VmovRegD>( 611 machInst, vd, vm, true); 612 } 613 } else { 614 if (single) { 615 return decodeVfpRegRegOp<VabsS>( 616 machInst, vd, vm, false); 617 } else { 618 return decodeVfpRegRegOp<VabsD>( 619 machInst, vd, vm, true); 620 } 621 } 622 case 0x1: 623 if (opc3 == 1) { 624 if (single) { 625 return decodeVfpRegRegOp<VnegS>( 626 machInst, vd, vm, false); 627 } else { 628 return decodeVfpRegRegOp<VnegD>( 629 machInst, vd, vm, true); 630 } 631 } else { 632 if (single) { 633 return decodeVfpRegRegOp<VsqrtS>( 634 machInst, vd, vm, false); 635 } else { 636 return decodeVfpRegRegOp<VsqrtD>( 637 machInst, vd, vm, true); 638 } 639 } 640 case 0x2: 641 case 0x3: 642 // Between half and single precision. 643 return new WarnUnimplemented("vcvtb, vcvtt", machInst); 644 case 0x4: 645 if (single) { 646 if (e) { 647 return new VcmpeS(machInst, vd, vm); 648 } else { 649 return new VcmpS(machInst, vd, vm); 650 } 651 } else { 652 if (e) { 653 return new VcmpeD(machInst, vd, vm); 654 } else { 655 return new VcmpD(machInst, vd, vm); 656 } 657 } 658 case 0x5: 659 if (single) { 660 if (e) { 661 return new VcmpeZeroS(machInst, vd, 0); 662 } else { 663 return new VcmpZeroS(machInst, vd, 0); 664 } 665 } else { 666 if (e) { 667 return new VcmpeZeroD(machInst, vd, 0); 668 } else { 669 return new VcmpZeroD(machInst, vd, 0); 670 } 671 } 672 case 0x7: 673 if (opc3 == 0x3) { 674 if (single) { 675 vm = (IntRegIndex)(bits(machInst, 5) | 676 (bits(machInst, 3, 0) << 1)); 677 return new VcvtFpSFpD(machInst, vd, vm); 678 } else { 679 vd = (IntRegIndex)(bits(machInst, 22) | 680 (bits(machInst, 15, 12) << 1)); 681 return new VcvtFpDFpS(machInst, vd, vm); 682 } 683 } 684 break; 685 case 0x8: 686 if (bits(machInst, 7) == 0) { 687 if (single) { 688 return new VcvtUIntFpS(machInst, vd, vm); 689 } else { 690 vm = (IntRegIndex)(bits(machInst, 5) | 691 (bits(machInst, 3, 0) << 1)); 692 return new VcvtUIntFpD(machInst, vd, vm); 693 } 694 } else { 695 if (single) { 696 return new VcvtSIntFpS(machInst, vd, vm); 697 } else { 698 vm = (IntRegIndex)(bits(machInst, 5) | 699 (bits(machInst, 3, 0) << 1)); 700 return new VcvtSIntFpD(machInst, vd, vm); 701 } 702 } 703 case 0xa: 704 { 705 const bool half = (bits(machInst, 7) == 0); 706 const uint32_t imm = bits(machInst, 5) | 707 (bits(machInst, 3, 0) << 1); 708 const uint32_t size = 709 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 710 if (single) { 711 if (half) { 712 return new VcvtSHFixedFpS(machInst, vd, vd, size); 713 } else { 714 return new VcvtSFixedFpS(machInst, vd, vd, size); 715 } 716 } else { 717 if (half) { 718 return new VcvtSHFixedFpD(machInst, vd, vd, size); 719 } else { 720 return new VcvtSFixedFpD(machInst, vd, vd, size); 721 } 722 } 723 } 724 case 0xb: 725 { 726 const bool half = (bits(machInst, 7) == 0); 727 const uint32_t imm = bits(machInst, 5) | 728 (bits(machInst, 3, 0) << 1); 729 const uint32_t size = 730 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 731 if (single) { 732 if (half) { 733 return new VcvtUHFixedFpS(machInst, vd, vd, size); 734 } else { 735 return new VcvtUFixedFpS(machInst, vd, vd, size); 736 } 737 } else { 738 if (half) { 739 return new VcvtUHFixedFpD(machInst, vd, vd, size); 740 } else { 741 return new VcvtUFixedFpD(machInst, vd, vd, size); 742 } 743 } 744 } 745 case 0xc: 746 if (bits(machInst, 7) == 0) { 747 if (single) { 748 return new VcvtFpUIntSR(machInst, vd, vm); 749 } else { 750 vd = (IntRegIndex)(bits(machInst, 22) | 751 (bits(machInst, 15, 12) << 1)); 752 return new VcvtFpUIntDR(machInst, vd, vm); 753 } 754 } else { 755 if (single) { 756 return new VcvtFpUIntS(machInst, vd, vm); 757 } else { 758 vd = (IntRegIndex)(bits(machInst, 22) | 759 (bits(machInst, 15, 12) << 1)); 760 return new VcvtFpUIntD(machInst, vd, vm); 761 } 762 } 763 case 0xd: 764 if (bits(machInst, 7) == 0) { 765 if (single) { 766 return new VcvtFpSIntSR(machInst, vd, vm); 767 } else { 768 vd = (IntRegIndex)(bits(machInst, 22) | 769 (bits(machInst, 15, 12) << 1)); 770 return new VcvtFpSIntDR(machInst, vd, vm); 771 } 772 } else { 773 if (single) { 774 return new VcvtFpSIntS(machInst, vd, vm); 775 } else { 776 vd = (IntRegIndex)(bits(machInst, 22) | 777 (bits(machInst, 15, 12) << 1)); 778 return new VcvtFpSIntD(machInst, vd, vm); 779 } 780 } 781 case 0xe: 782 { 783 const bool half = (bits(machInst, 7) == 0); 784 const uint32_t imm = bits(machInst, 5) | 785 (bits(machInst, 3, 0) << 1); 786 const uint32_t size = 787 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 788 if (single) { 789 if (half) { 790 return new VcvtFpSHFixedS(machInst, vd, vd, size); 791 } else { 792 return new VcvtFpSFixedS(machInst, vd, vd, size); 793 } 794 } else { 795 if (half) { 796 return new VcvtFpSHFixedD(machInst, vd, vd, size); 797 } else { 798 return new VcvtFpSFixedD(machInst, vd, vd, size); 799 } 800 } 801 } 802 case 0xf: 803 { 804 const bool half = (bits(machInst, 7) == 0); 805 const uint32_t imm = bits(machInst, 5) | 806 (bits(machInst, 3, 0) << 1); 807 const uint32_t size = 808 (bits(machInst, 7) == 0 ? 16 : 32) - imm; 809 if (single) { 810 if (half) { 811 return new VcvtFpUHFixedS(machInst, vd, vd, size); 812 } else { 813 return new VcvtFpUFixedS(machInst, vd, vd, size); 814 } 815 } else { 816 if (half) { 817 return new VcvtFpUHFixedD(machInst, vd, vd, size); 818 } else { 819 return new VcvtFpUFixedD(machInst, vd, vd, size); 820 } 821 } 822 } 823 } 824 break; 825 } 826 return new Unknown(machInst); 827 } 828 ''' 829}}; 830 831def format VfpData() {{ 832 decode_block = ''' 833 return decodeVfpData(machInst); 834 ''' 835}}; 836