fp.isa revision 7367:8c3ec534f022
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 37178Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47178Sgblack@eecs.umich.edu// All rights reserved 57178Sgblack@eecs.umich.edu// 67178Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77178Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87178Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97178Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107178Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117178Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127178Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137178Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147178Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Floating Point operate instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 487639Sgblack@eecs.umich.edudef template FPAExecute {{ 497639Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 507639Sgblack@eecs.umich.edu { 517639Sgblack@eecs.umich.edu Fault fault = NoFault; 527639Sgblack@eecs.umich.edu 537639Sgblack@eecs.umich.edu %(fp_enable_check)s; 547639Sgblack@eecs.umich.edu 557639Sgblack@eecs.umich.edu %(op_decl)s; 567639Sgblack@eecs.umich.edu %(op_rd)s; 577639Sgblack@eecs.umich.edu 587639Sgblack@eecs.umich.edu if (%(predicate_test)s) { 597639Sgblack@eecs.umich.edu %(code)s; 607639Sgblack@eecs.umich.edu if (fault == NoFault) { 617639Sgblack@eecs.umich.edu %(op_wb)s; 627639Sgblack@eecs.umich.edu } 637639Sgblack@eecs.umich.edu } 647639Sgblack@eecs.umich.edu 657639Sgblack@eecs.umich.edu return fault; 667639Sgblack@eecs.umich.edu } 677639Sgblack@eecs.umich.edu}}; 687639Sgblack@eecs.umich.edu 697639Sgblack@eecs.umich.edudef template FloatDoubleDecode {{ 707639Sgblack@eecs.umich.edu { 717639Sgblack@eecs.umich.edu ArmStaticInst *i = NULL; 727639Sgblack@eecs.umich.edu switch (OPCODE_19 << 1 | OPCODE_7) 737639Sgblack@eecs.umich.edu { 747639Sgblack@eecs.umich.edu case 0: 757639Sgblack@eecs.umich.edu i = (ArmStaticInst *)new %(class_name)sS(machInst); 767639Sgblack@eecs.umich.edu break; 777639Sgblack@eecs.umich.edu case 1: 787639Sgblack@eecs.umich.edu i = (ArmStaticInst *)new %(class_name)sD(machInst); 797639Sgblack@eecs.umich.edu break; 807639Sgblack@eecs.umich.edu case 2: 817639Sgblack@eecs.umich.edu case 3: 827639Sgblack@eecs.umich.edu default: 837639Sgblack@eecs.umich.edu panic("Cannot decode float/double nature of the instruction"); 847639Sgblack@eecs.umich.edu } 857639Sgblack@eecs.umich.edu return i; 867639Sgblack@eecs.umich.edu } 877639Sgblack@eecs.umich.edu}}; 887639Sgblack@eecs.umich.edu 897639Sgblack@eecs.umich.edu// Primary format for float point operate instructions: 907639Sgblack@eecs.umich.edudef format FloatOp(code, *flags) {{ 917639Sgblack@eecs.umich.edu orig_code = code 927639Sgblack@eecs.umich.edu 937639Sgblack@eecs.umich.edu cblk = code 947356Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 957356Sgblack@eecs.umich.edu {"code": cblk, 967356Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 977435Sgblack@eecs.umich.edu flags) 987435Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(iop) 997435Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(iop) 1007435Sgblack@eecs.umich.edu exec_output = FPAExecute.subst(iop) 1017435Sgblack@eecs.umich.edu 1027435Sgblack@eecs.umich.edu sng_cblk = code 1037435Sgblack@eecs.umich.edu sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1047435Sgblack@eecs.umich.edu {"code": sng_cblk, 1057435Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1067435Sgblack@eecs.umich.edu flags) 1077435Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sng_iop) 1087639Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sng_iop) 1097639Sgblack@eecs.umich.edu exec_output += FPAExecute.subst(sng_iop) 1107639Sgblack@eecs.umich.edu 1117435Sgblack@eecs.umich.edu dbl_code = re.sub(r'\.sf', '.df', orig_code) 1127639Sgblack@eecs.umich.edu 1137639Sgblack@eecs.umich.edu dbl_cblk = dbl_code 1147639Sgblack@eecs.umich.edu dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1157639Sgblack@eecs.umich.edu {"code": dbl_cblk, 1167639Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1177639Sgblack@eecs.umich.edu flags) 1187639Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(dbl_iop) 1197639Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(dbl_iop) 1207639Sgblack@eecs.umich.edu exec_output += FPAExecute.subst(dbl_iop) 1217639Sgblack@eecs.umich.edu 1227639Sgblack@eecs.umich.edu decode_block = FloatDoubleDecode.subst(iop) 1237639Sgblack@eecs.umich.edu}}; 1247639Sgblack@eecs.umich.edu 1257639Sgblack@eecs.umich.edulet {{ 1267639Sgblack@eecs.umich.edu calcFPCcCode = ''' 1277639Sgblack@eecs.umich.edu uint16_t _in, _iz, _ic, _iv; 1287639Sgblack@eecs.umich.edu 1297639Sgblack@eecs.umich.edu _in = %(fReg1)s < %(fReg2)s; 1307639Sgblack@eecs.umich.edu _iz = %(fReg1)s == %(fReg2)s; 1317639Sgblack@eecs.umich.edu _ic = %(fReg1)s >= %(fReg2)s; 1327639Sgblack@eecs.umich.edu _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 1337639Sgblack@eecs.umich.edu 1347639Sgblack@eecs.umich.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 1357639Sgblack@eecs.umich.edu (CondCodes & 0x0FFFFFFF); 1367639Sgblack@eecs.umich.edu ''' 1377639Sgblack@eecs.umich.edu}}; 1387639Sgblack@eecs.umich.edu 1397639Sgblack@eecs.umich.edudef format FloatCmp(fReg1, fReg2, *flags) {{ 1407639Sgblack@eecs.umich.edu code = calcFPCcCode % vars() 1417639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 1427639Sgblack@eecs.umich.edu {"code": code, 1437639Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1447639Sgblack@eecs.umich.edu flags) 1457639Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(iop) 1468144SAli.Saidi@ARM.com decoder_output = BasicConstructor.subst(iop) 1477639Sgblack@eecs.umich.edu decode_block = BasicDecode.subst(iop) 1487639Sgblack@eecs.umich.edu exec_output = FPAExecute.subst(iop) 1497639Sgblack@eecs.umich.edu}}; 1507639Sgblack@eecs.umich.edu 1517639Sgblack@eecs.umich.edulet {{ 1527639Sgblack@eecs.umich.edu header_output = ''' 1537639Sgblack@eecs.umich.edu StaticInstPtr 1547639Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst); 1557639Sgblack@eecs.umich.edu ''' 1567639Sgblack@eecs.umich.edu decoder_output = ''' 1577639Sgblack@eecs.umich.edu StaticInstPtr 1587639Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst) 1597639Sgblack@eecs.umich.edu { 1607639Sgblack@eecs.umich.edu const uint32_t opcode = bits(machInst, 24, 20); 1617639Sgblack@eecs.umich.edu const uint32_t offset = bits(machInst, 7, 0); 1627639Sgblack@eecs.umich.edu const bool single = (bits(machInst, 8) == 0); 1637639Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1647639Sgblack@eecs.umich.edu RegIndex vd; 1657639Sgblack@eecs.umich.edu if (single) { 1667639Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1677639Sgblack@eecs.umich.edu bits(machInst, 22)); 1687639Sgblack@eecs.umich.edu } else { 1697639Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1707639Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 1717639Sgblack@eecs.umich.edu } 1727639Sgblack@eecs.umich.edu switch (bits(opcode, 4, 3)) { 1737639Sgblack@eecs.umich.edu case 0x0: 1747639Sgblack@eecs.umich.edu if (bits(opcode, 4, 1) == 0x2 && 1757639Sgblack@eecs.umich.edu !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 1767639Sgblack@eecs.umich.edu !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 1777639Sgblack@eecs.umich.edu if ((bits(machInst, 7, 4) & 0xd) != 1) { 1787639Sgblack@eecs.umich.edu break; 1797639Sgblack@eecs.umich.edu } 1807639Sgblack@eecs.umich.edu const IntRegIndex rt = 1817639Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1827639Sgblack@eecs.umich.edu const IntRegIndex rt2 = 1837591SAli.Saidi@ARM.com (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1847639Sgblack@eecs.umich.edu const bool op = bits(machInst, 20); 1857435Sgblack@eecs.umich.edu uint32_t vm; 1867435Sgblack@eecs.umich.edu if (single) { 1877639Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 1887639Sgblack@eecs.umich.edu } else { 1897639Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | 1907639Sgblack@eecs.umich.edu (bits(machInst, 5) << 5); 1917639Sgblack@eecs.umich.edu } 1927639Sgblack@eecs.umich.edu if (op) { 1937639Sgblack@eecs.umich.edu return new Vmov2Core2Reg(machInst, rt, rt2, 1947639Sgblack@eecs.umich.edu (IntRegIndex)vm); 1957639Sgblack@eecs.umich.edu } else { 1967639Sgblack@eecs.umich.edu return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 1977639Sgblack@eecs.umich.edu rt, rt2); 1987639Sgblack@eecs.umich.edu } 1997639Sgblack@eecs.umich.edu } 2007639Sgblack@eecs.umich.edu break; 2017639Sgblack@eecs.umich.edu case 0x1: 2027639Sgblack@eecs.umich.edu switch (bits(opcode, 1, 0)) { 2037639Sgblack@eecs.umich.edu case 0x0: 2047639Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2057639Sgblack@eecs.umich.edu true, false, false, offset); 2067639Sgblack@eecs.umich.edu case 0x1: 2077639Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2087639Sgblack@eecs.umich.edu true, false, true, offset); 2097639Sgblack@eecs.umich.edu case 0x2: 2107639Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2117639Sgblack@eecs.umich.edu true, true, false, offset); 2127639Sgblack@eecs.umich.edu case 0x3: 2137639Sgblack@eecs.umich.edu // If rn == sp, then this is called vpop. 2147639Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2157639Sgblack@eecs.umich.edu true, true, true, offset); 2167639Sgblack@eecs.umich.edu } 2177639Sgblack@eecs.umich.edu case 0x2: 2187639Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x2) { 2197639Sgblack@eecs.umich.edu // If rn == sp, then this is called vpush. 2207639Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2217639Sgblack@eecs.umich.edu false, true, false, offset); 2227639Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x3) { 2237591SAli.Saidi@ARM.com return new VLdmStm(machInst, rn, vd, single, 2247591SAli.Saidi@ARM.com false, true, true, offset); 2257639Sgblack@eecs.umich.edu } 2267639Sgblack@eecs.umich.edu // Fall through on purpose 2277639Sgblack@eecs.umich.edu case 0x3: 2287639Sgblack@eecs.umich.edu const bool up = (bits(machInst, 23) == 1); 2297639Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) << 2; 2307639Sgblack@eecs.umich.edu RegIndex vd; 2317639Sgblack@eecs.umich.edu if (single) { 2327639Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2337639Sgblack@eecs.umich.edu (bits(machInst, 22))); 2347639Sgblack@eecs.umich.edu } else { 2357639Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2367639Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 2377639Sgblack@eecs.umich.edu } 2387639Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x0) { 2397639Sgblack@eecs.umich.edu if (single) { 2407639Sgblack@eecs.umich.edu if (up) { 2417639Sgblack@eecs.umich.edu return new %(vstr_us)s(machInst, vd, rn, up, imm); 2427639Sgblack@eecs.umich.edu } else { 2437639Sgblack@eecs.umich.edu return new %(vstr_s)s(machInst, vd, rn, up, imm); 2447639Sgblack@eecs.umich.edu } 2457435Sgblack@eecs.umich.edu } else { 2467435Sgblack@eecs.umich.edu if (up) { 2477639Sgblack@eecs.umich.edu return new %(vstr_ud)s(machInst, vd, vd + 1, 2487639Sgblack@eecs.umich.edu rn, up, imm); 2497639Sgblack@eecs.umich.edu } else { 2507639Sgblack@eecs.umich.edu return new %(vstr_d)s(machInst, vd, vd + 1, 2517639Sgblack@eecs.umich.edu rn, up, imm); 2527639Sgblack@eecs.umich.edu } 2537639Sgblack@eecs.umich.edu } 2547639Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x1) { 2557639Sgblack@eecs.umich.edu if (single) { 2567639Sgblack@eecs.umich.edu if (up) { 2577639Sgblack@eecs.umich.edu return new %(vldr_us)s(machInst, vd, rn, up, imm); 2587639Sgblack@eecs.umich.edu } else { 2597639Sgblack@eecs.umich.edu return new %(vldr_s)s(machInst, vd, rn, up, imm); 2607639Sgblack@eecs.umich.edu } 2617639Sgblack@eecs.umich.edu } else { 2627639Sgblack@eecs.umich.edu if (up) { 2637639Sgblack@eecs.umich.edu return new %(vldr_ud)s(machInst, vd, vd + 1, 2647639Sgblack@eecs.umich.edu rn, up, imm); 2657639Sgblack@eecs.umich.edu } else { 2667639Sgblack@eecs.umich.edu return new %(vldr_d)s(machInst, vd, vd + 1, 2677639Sgblack@eecs.umich.edu rn, up, imm); 2687639Sgblack@eecs.umich.edu } 2697639Sgblack@eecs.umich.edu } 2707639Sgblack@eecs.umich.edu } 2717639Sgblack@eecs.umich.edu } 2727639Sgblack@eecs.umich.edu return new Unknown(machInst); 2737639Sgblack@eecs.umich.edu } 2747639Sgblack@eecs.umich.edu ''' % { 2757639Sgblack@eecs.umich.edu "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 2767639Sgblack@eecs.umich.edu "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 2777639Sgblack@eecs.umich.edu "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 2787639Sgblack@eecs.umich.edu "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 2797639Sgblack@eecs.umich.edu "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 2807639Sgblack@eecs.umich.edu "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 2817639Sgblack@eecs.umich.edu "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 2827639Sgblack@eecs.umich.edu "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 2837639Sgblack@eecs.umich.edu } 2847639Sgblack@eecs.umich.edu}}; 2857639Sgblack@eecs.umich.edu 2867639Sgblack@eecs.umich.edudef format ExtensionRegLoadStore() {{ 2877639Sgblack@eecs.umich.edu decode_block = ''' 2887639Sgblack@eecs.umich.edu return decodeExtensionRegLoadStore(machInst); 2897639Sgblack@eecs.umich.edu ''' 2907639Sgblack@eecs.umich.edu}}; 2917639Sgblack@eecs.umich.edu 2927639Sgblack@eecs.umich.edulet {{ 2937639Sgblack@eecs.umich.edu header_output = ''' 2947639Sgblack@eecs.umich.edu StaticInstPtr 2957639Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst); 2967639Sgblack@eecs.umich.edu ''' 2977639Sgblack@eecs.umich.edu decoder_output = ''' 2987639Sgblack@eecs.umich.edu StaticInstPtr 2997639Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst) 3007639Sgblack@eecs.umich.edu { 3017639Sgblack@eecs.umich.edu const uint32_t l = bits(machInst, 20); 3027639Sgblack@eecs.umich.edu const uint32_t c = bits(machInst, 8); 3037639Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 23, 21); 3047639Sgblack@eecs.umich.edu const uint32_t b = bits(machInst, 6, 5); 3057639Sgblack@eecs.umich.edu if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 3067639Sgblack@eecs.umich.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 3077639Sgblack@eecs.umich.edu return new Unknown(machInst); 3087639Sgblack@eecs.umich.edu } 3097639Sgblack@eecs.umich.edu if (l == 0 && c == 0) { 3107639Sgblack@eecs.umich.edu if (a == 0) { 3117639Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3127639Sgblack@eecs.umich.edu bits(machInst, 7); 3137639Sgblack@eecs.umich.edu const IntRegIndex rt = 3147639Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3157639Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3167639Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3177639Sgblack@eecs.umich.edu } else { 3187639Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3197639Sgblack@eecs.umich.edu } 3207639Sgblack@eecs.umich.edu } else if (a == 0x7) { 3217639Sgblack@eecs.umich.edu const IntRegIndex rt = 3227639Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3237435Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3247435Sgblack@eecs.umich.edu switch (specReg) { 3257639Sgblack@eecs.umich.edu case 0: 3267639Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3277639Sgblack@eecs.umich.edu break; 3287591SAli.Saidi@ARM.com case 1: 3297639Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3307639Sgblack@eecs.umich.edu break; 3317435Sgblack@eecs.umich.edu case 8: 3327435Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 3337639Sgblack@eecs.umich.edu break; 3347639Sgblack@eecs.umich.edu default: 3357435Sgblack@eecs.umich.edu return new Unknown(machInst); 3367435Sgblack@eecs.umich.edu } 3377591SAli.Saidi@ARM.com return new Vmsr(machInst, (IntRegIndex)specReg, rt); 3387435Sgblack@eecs.umich.edu } 3397435Sgblack@eecs.umich.edu } else if (l == 0 && c == 1) { 3407435Sgblack@eecs.umich.edu if (bits(a, 2) == 0) { 3417435Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 3427435Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 3437435Sgblack@eecs.umich.edu uint32_t index, size; 3447435Sgblack@eecs.umich.edu const IntRegIndex rt = 3457435Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3467435Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 3477435Sgblack@eecs.umich.edu size = 8; 3487435Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 3497639Sgblack@eecs.umich.edu bits(machInst, 6, 5); 3507639Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 3517639Sgblack@eecs.umich.edu size = 16; 3527639Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 3537639Sgblack@eecs.umich.edu bits(machInst, 6); 3547639Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0) { 3557639Sgblack@eecs.umich.edu size = 32; 3567639Sgblack@eecs.umich.edu index = bits(machInst, 21); 3577639Sgblack@eecs.umich.edu } else { 3587639Sgblack@eecs.umich.edu return new Unknown(machInst); 3597639Sgblack@eecs.umich.edu } 3607639Sgblack@eecs.umich.edu if (index >= (32 / size)) { 3617639Sgblack@eecs.umich.edu index -= (32 / size); 3627435Sgblack@eecs.umich.edu vd++; 3637435Sgblack@eecs.umich.edu } 3647435Sgblack@eecs.umich.edu switch (size) { 3657639Sgblack@eecs.umich.edu case 8: 3667639Sgblack@eecs.umich.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 3677639Sgblack@eecs.umich.edu rt, index); 3687435Sgblack@eecs.umich.edu case 16: 3697639Sgblack@eecs.umich.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 3707639Sgblack@eecs.umich.edu rt, index); 3717435Sgblack@eecs.umich.edu case 32: 3727435Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 3737639Sgblack@eecs.umich.edu } 3747639Sgblack@eecs.umich.edu } else if (bits(b, 1) == 0) { 3757639Sgblack@eecs.umich.edu // A8-594 3767639Sgblack@eecs.umich.edu return new WarnUnimplemented("vdup", machInst); 3777435Sgblack@eecs.umich.edu } 3787435Sgblack@eecs.umich.edu } else if (l == 1 && c == 0) { 3797435Sgblack@eecs.umich.edu if (a == 0) { 3807639Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3817639Sgblack@eecs.umich.edu bits(machInst, 7); 3827435Sgblack@eecs.umich.edu const IntRegIndex rt = 3837435Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3847435Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3857435Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3867639Sgblack@eecs.umich.edu } else { 3877639Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3887639Sgblack@eecs.umich.edu } 3897639Sgblack@eecs.umich.edu } else if (a == 7) { 3907639Sgblack@eecs.umich.edu const IntRegIndex rt = 3917435Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3927639Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3937639Sgblack@eecs.umich.edu switch (specReg) { 3947639Sgblack@eecs.umich.edu case 0: 3957639Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3967639Sgblack@eecs.umich.edu break; 3977435Sgblack@eecs.umich.edu case 1: 3987639Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3997639Sgblack@eecs.umich.edu break; 4007639Sgblack@eecs.umich.edu case 6: 4017639Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 4027639Sgblack@eecs.umich.edu break; 4037435Sgblack@eecs.umich.edu case 7: 4047639Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 4057639Sgblack@eecs.umich.edu break; 4067639Sgblack@eecs.umich.edu case 8: 4077639Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 4087639Sgblack@eecs.umich.edu break; 4097435Sgblack@eecs.umich.edu default: 4107435Sgblack@eecs.umich.edu return new Unknown(machInst); 4117435Sgblack@eecs.umich.edu } 4127435Sgblack@eecs.umich.edu return new Vmrs(machInst, rt, (IntRegIndex)specReg); 4137639Sgblack@eecs.umich.edu } 4147639Sgblack@eecs.umich.edu } else { 4157639Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 4167639Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 4177639Sgblack@eecs.umich.edu uint32_t index, size; 4187435Sgblack@eecs.umich.edu const IntRegIndex rt = 4197639Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 4207639Sgblack@eecs.umich.edu const bool u = (bits(machInst, 23) == 1); 4217639Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 4227639Sgblack@eecs.umich.edu size = 8; 4237639Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 4247435Sgblack@eecs.umich.edu bits(machInst, 6, 5); 4257639Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 4267639Sgblack@eecs.umich.edu size = 16; 4277639Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 4287639Sgblack@eecs.umich.edu bits(machInst, 6); 4297435Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0 && !u) { 4307639Sgblack@eecs.umich.edu size = 32; 4317639Sgblack@eecs.umich.edu index = bits(machInst, 21); 4327639Sgblack@eecs.umich.edu } else { 4337639Sgblack@eecs.umich.edu return new Unknown(machInst); 4347639Sgblack@eecs.umich.edu } 4357639Sgblack@eecs.umich.edu if (index >= (32 / size)) { 4367639Sgblack@eecs.umich.edu index -= (32 / size); 4377639Sgblack@eecs.umich.edu vd++; 4387639Sgblack@eecs.umich.edu } 4397639Sgblack@eecs.umich.edu switch (size) { 4407435Sgblack@eecs.umich.edu case 8: 4417435Sgblack@eecs.umich.edu if (u) { 4427435Sgblack@eecs.umich.edu return new VmovRegCoreUB(machInst, rt, 4437639Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4447639Sgblack@eecs.umich.edu } else { 4457639Sgblack@eecs.umich.edu return new VmovRegCoreSB(machInst, rt, 4467639Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4477639Sgblack@eecs.umich.edu } 4487639Sgblack@eecs.umich.edu case 16: 4497639Sgblack@eecs.umich.edu if (u) { 4507435Sgblack@eecs.umich.edu return new VmovRegCoreUH(machInst, rt, 4517435Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4527435Sgblack@eecs.umich.edu } else { 4537435Sgblack@eecs.umich.edu return new VmovRegCoreSH(machInst, rt, 4547435Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4557639Sgblack@eecs.umich.edu } 4567639Sgblack@eecs.umich.edu case 32: 4577639Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 4587639Sgblack@eecs.umich.edu } 4597639Sgblack@eecs.umich.edu } 4607639Sgblack@eecs.umich.edu return new Unknown(machInst); 4617639Sgblack@eecs.umich.edu } 4627435Sgblack@eecs.umich.edu ''' 4637639Sgblack@eecs.umich.edu}}; 4647639Sgblack@eecs.umich.edu 4657639Sgblack@eecs.umich.edudef format ShortFpTransfer() {{ 4667639Sgblack@eecs.umich.edu decode_block = ''' 4677435Sgblack@eecs.umich.edu return decodeShortFpTransfer(machInst); 4687435Sgblack@eecs.umich.edu ''' 4697435Sgblack@eecs.umich.edu}}; 4707639Sgblack@eecs.umich.edu 4717639Sgblack@eecs.umich.edulet {{ 4727435Sgblack@eecs.umich.edu header_output = ''' 4737639Sgblack@eecs.umich.edu StaticInstPtr 4747639Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst); 4757435Sgblack@eecs.umich.edu ''' 4767435Sgblack@eecs.umich.edu decoder_output = ''' 4777435Sgblack@eecs.umich.edu StaticInstPtr 4787639Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst) 4797639Sgblack@eecs.umich.edu { 4807639Sgblack@eecs.umich.edu const uint32_t opc1 = bits(machInst, 23, 20); 4817639Sgblack@eecs.umich.edu const uint32_t opc2 = bits(machInst, 19, 16); 4827639Sgblack@eecs.umich.edu const uint32_t opc3 = bits(machInst, 7, 6); 4837639Sgblack@eecs.umich.edu //const uint32_t opc4 = bits(machInst, 3, 0); 4847639Sgblack@eecs.umich.edu switch (opc1 & 0xb /* 1011 */) { 4857435Sgblack@eecs.umich.edu case 0x0: 4867639Sgblack@eecs.umich.edu return new WarnUnimplemented("vmla, vmls", machInst); 4877639Sgblack@eecs.umich.edu case 0x2: 4887435Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 4897435Sgblack@eecs.umich.edu uint32_t vd; 4907435Sgblack@eecs.umich.edu uint32_t vm; 4917639Sgblack@eecs.umich.edu uint32_t vn; 4927639Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 4937639Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 4947639Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 4957639Sgblack@eecs.umich.edu vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); 4967639Sgblack@eecs.umich.edu return new VmulS(machInst, (IntRegIndex)vd, 4977639Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 4987435Sgblack@eecs.umich.edu } else { 4997639Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5007639Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5017435Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5027435Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5037435Sgblack@eecs.umich.edu vn = (bits(machInst, 7) << 5) | 5047639Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 5057639Sgblack@eecs.umich.edu return new VmulD(machInst, (IntRegIndex)vd, 5067435Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5077639Sgblack@eecs.umich.edu } 5087639Sgblack@eecs.umich.edu } 5097435Sgblack@eecs.umich.edu case 0x1: 5107435Sgblack@eecs.umich.edu return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst); 5117435Sgblack@eecs.umich.edu case 0x3: 5127639Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5137639Sgblack@eecs.umich.edu uint32_t vd; 5147435Sgblack@eecs.umich.edu uint32_t vm; 5157435Sgblack@eecs.umich.edu uint32_t vn; 5167639Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5177435Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5187435Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5197639Sgblack@eecs.umich.edu vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); 5207639Sgblack@eecs.umich.edu return new VaddS(machInst, (IntRegIndex)vd, 5217435Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5227435Sgblack@eecs.umich.edu } else { 5237639Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5247639Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5257435Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5267435Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5277435Sgblack@eecs.umich.edu vn = (bits(machInst, 7) << 5) | 5287435Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 5297435Sgblack@eecs.umich.edu return new VaddD(machInst, (IntRegIndex)vd, 5307639Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5317639Sgblack@eecs.umich.edu } 5327435Sgblack@eecs.umich.edu } else { 5337639Sgblack@eecs.umich.edu return new WarnUnimplemented("vsub", machInst); 5347639Sgblack@eecs.umich.edu } 5357435Sgblack@eecs.umich.edu case 0x8: 5367435Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5377435Sgblack@eecs.umich.edu return new WarnUnimplemented("vdiv", machInst); 5387639Sgblack@eecs.umich.edu } 5397639Sgblack@eecs.umich.edu break; 5407435Sgblack@eecs.umich.edu case 0xb: 5417639Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5427639Sgblack@eecs.umich.edu uint32_t vd; 5437435Sgblack@eecs.umich.edu const uint32_t baseImm = 5447435Sgblack@eecs.umich.edu bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 5457435Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5467435Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5477435Sgblack@eecs.umich.edu uint32_t imm = vfp_modified_imm(baseImm, false); 5487639Sgblack@eecs.umich.edu return new VmovImmS(machInst, (IntRegIndex)vd, imm); 5497639Sgblack@eecs.umich.edu } else { 5507435Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5517639Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5527639Sgblack@eecs.umich.edu uint64_t imm = vfp_modified_imm(baseImm, true); 5537435Sgblack@eecs.umich.edu return new VmovImmD(machInst, (IntRegIndex)vd, imm); 5547435Sgblack@eecs.umich.edu } 5557435Sgblack@eecs.umich.edu } 5567639Sgblack@eecs.umich.edu switch (opc2) { 5577639Sgblack@eecs.umich.edu case 0x0: 5587435Sgblack@eecs.umich.edu if (opc3 == 1) { 5597639Sgblack@eecs.umich.edu uint32_t vd; 5607639Sgblack@eecs.umich.edu uint32_t vm; 5617435Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5627435Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5637435Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5647435Sgblack@eecs.umich.edu return new VmovRegS(machInst, 5657639Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 5667639Sgblack@eecs.umich.edu } else { 5677435Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5687639Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5697639Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5707435Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5717435Sgblack@eecs.umich.edu return new VmovRegD(machInst, 5727435Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 5737435Sgblack@eecs.umich.edu } 5747435Sgblack@eecs.umich.edu } else { 5757435Sgblack@eecs.umich.edu uint32_t vd; 5767639Sgblack@eecs.umich.edu uint32_t vm; 5777639Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5787435Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5797435Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5807435Sgblack@eecs.umich.edu return new VabsS(machInst, 5817639Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 5827639Sgblack@eecs.umich.edu } else { 5837435Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5847639Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5857639Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5867435Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5877435Sgblack@eecs.umich.edu return new VabsD(machInst, 5887435Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 5897435Sgblack@eecs.umich.edu } 5907435Sgblack@eecs.umich.edu } 5917435Sgblack@eecs.umich.edu case 0x1: 5927435Sgblack@eecs.umich.edu if (opc3 == 1) { 5937435Sgblack@eecs.umich.edu uint32_t vd; 5947639Sgblack@eecs.umich.edu uint32_t vm; 5957639Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5967639Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5977639Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5987639Sgblack@eecs.umich.edu return new VnegS(machInst, 5997435Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 6007435Sgblack@eecs.umich.edu } else { 6017435Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 6027435Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 6037435Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 6047639Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 6057639Sgblack@eecs.umich.edu return new VnegD(machInst, 6067639Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 6077639Sgblack@eecs.umich.edu } 6087639Sgblack@eecs.umich.edu } else { 6097435Sgblack@eecs.umich.edu return new WarnUnimplemented("vsqrt", machInst); 6107639Sgblack@eecs.umich.edu } 6117639Sgblack@eecs.umich.edu case 0x2: 6127639Sgblack@eecs.umich.edu case 0x3: 6137639Sgblack@eecs.umich.edu // Between half and single precision. 6147639Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvtb, vcvtt", machInst); 6157435Sgblack@eecs.umich.edu case 0x4: 6167435Sgblack@eecs.umich.edu case 0x5: 6177435Sgblack@eecs.umich.edu return new WarnUnimplemented("vcmp, vcmpe", machInst); 6187435Sgblack@eecs.umich.edu case 0x7: 6197435Sgblack@eecs.umich.edu if (opc3 == 0x3) { 6207639Sgblack@eecs.umich.edu // Between double and single precision. 6217639Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt", machInst); 6227639Sgblack@eecs.umich.edu } 6237639Sgblack@eecs.umich.edu break; 6247639Sgblack@eecs.umich.edu case 0x8: 6257435Sgblack@eecs.umich.edu // Between FP and int. 6267639Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt, vcvtr", machInst); 6277639Sgblack@eecs.umich.edu case 0xa: 6287639Sgblack@eecs.umich.edu case 0xb: 6297639Sgblack@eecs.umich.edu // Between FP and fixed point. 6307639Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt", machInst); 6317435Sgblack@eecs.umich.edu case 0xc: 6327435Sgblack@eecs.umich.edu case 0xd: 6337435Sgblack@eecs.umich.edu // Between FP and int. 6347639Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt, vcvtr", machInst); 6357639Sgblack@eecs.umich.edu case 0xe: 6367639Sgblack@eecs.umich.edu case 0xf: 6377639Sgblack@eecs.umich.edu // Between FP and fixed point. 6387639Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt", machInst); 6397435Sgblack@eecs.umich.edu } 6407639Sgblack@eecs.umich.edu break; 6417639Sgblack@eecs.umich.edu } 6427639Sgblack@eecs.umich.edu return new Unknown(machInst); 6437639Sgblack@eecs.umich.edu } 6447639Sgblack@eecs.umich.edu ''' 6457435Sgblack@eecs.umich.edu}}; 6467435Sgblack@eecs.umich.edu 6477435Sgblack@eecs.umich.edudef format VfpData() {{ 6487435Sgblack@eecs.umich.edu decode_block = ''' 6497435Sgblack@eecs.umich.edu return decodeVfpData(machInst); 6507435Sgblack@eecs.umich.edu ''' 6517435Sgblack@eecs.umich.edu}}; 6527639Sgblack@eecs.umich.edu