fp.isa revision 7366
16657Snate@binkert.org// -*- mode:c++ -*- 26657Snate@binkert.org 36657Snate@binkert.org// Copyright (c) 2010 ARM Limited 46657Snate@binkert.org// All rights reserved 56657Snate@binkert.org// 66657Snate@binkert.org// The license below extends only to copyright in the software and shall 76657Snate@binkert.org// not be construed as granting a license to any other intellectual 86657Snate@binkert.org// property including but not limited to intellectual property relating 96657Snate@binkert.org// to a hardware implementation of the functionality of the software 106657Snate@binkert.org// licensed hereunder. You may use the software subject to the license 116657Snate@binkert.org// terms below provided that you ensure that this notice is replicated 126657Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 136657Snate@binkert.org// modified or unmodified, in source code or in binary form. 146657Snate@binkert.org// 156657Snate@binkert.org// Copyright (c) 2007-2008 The Florida State University 166657Snate@binkert.org// All rights reserved. 176657Snate@binkert.org// 186657Snate@binkert.org// Redistribution and use in source and binary forms, with or without 196657Snate@binkert.org// modification, are permitted provided that the following conditions are 206657Snate@binkert.org// met: redistributions of source code must retain the above copyright 216657Snate@binkert.org// notice, this list of conditions and the following disclaimer; 226657Snate@binkert.org// redistributions in binary form must reproduce the above copyright 236657Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 246657Snate@binkert.org// documentation and/or other materials provided with the distribution; 256657Snate@binkert.org// neither the name of the copyright holders nor the names of its 266657Snate@binkert.org// contributors may be used to endorse or promote products derived from 276657Snate@binkert.org// this software without specific prior written permission. 286999Snate@binkert.org// 296657Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306657Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316657Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326657Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 338189SLisa.Hsu@amd.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346657Snate@binkert.org// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356882SBrad.Beckmann@amd.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367055Snate@binkert.org// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376882SBrad.Beckmann@amd.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386882SBrad.Beckmann@amd.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 398191SLisa.Hsu@amd.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406882SBrad.Beckmann@amd.com// 416882SBrad.Beckmann@amd.com// Authors: Stephen Hines 426882SBrad.Beckmann@amd.com 436888SBrad.Beckmann@amd.com//////////////////////////////////////////////////////////////////// 446882SBrad.Beckmann@amd.com// 456882SBrad.Beckmann@amd.com// Floating Point operate instructions 466657Snate@binkert.org// 476657Snate@binkert.org 486657Snate@binkert.orgdef template FPAExecute {{ 496657Snate@binkert.org Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 506657Snate@binkert.org { 517839Snilay@cs.wisc.edu Fault fault = NoFault; 526657Snate@binkert.org 536882SBrad.Beckmann@amd.com %(fp_enable_check)s; 546882SBrad.Beckmann@amd.com 556882SBrad.Beckmann@amd.com %(op_decl)s; 566882SBrad.Beckmann@amd.com %(op_rd)s; 576882SBrad.Beckmann@amd.com 586882SBrad.Beckmann@amd.com if (%(predicate_test)s) { 596657Snate@binkert.org %(code)s; 606657Snate@binkert.org if (fault == NoFault) { 616657Snate@binkert.org %(op_wb)s; 626657Snate@binkert.org } 636657Snate@binkert.org } 646657Snate@binkert.org 656657Snate@binkert.org return fault; 666657Snate@binkert.org } 676657Snate@binkert.org}}; 687839Snilay@cs.wisc.edu 697839Snilay@cs.wisc.edudef template FloatDoubleDecode {{ 706657Snate@binkert.org { 716657Snate@binkert.org ArmStaticInst *i = NULL; 726657Snate@binkert.org switch (OPCODE_19 << 1 | OPCODE_7) 736657Snate@binkert.org { 746657Snate@binkert.org case 0: 756657Snate@binkert.org i = (ArmStaticInst *)new %(class_name)sS(machInst); 766657Snate@binkert.org break; 776657Snate@binkert.org case 1: 786657Snate@binkert.org i = (ArmStaticInst *)new %(class_name)sD(machInst); 796657Snate@binkert.org break; 806657Snate@binkert.org case 2: 816657Snate@binkert.org case 3: 826657Snate@binkert.org default: 836657Snate@binkert.org panic("Cannot decode float/double nature of the instruction"); 846657Snate@binkert.org } 856657Snate@binkert.org return i; 866657Snate@binkert.org } 876657Snate@binkert.org}}; 886657Snate@binkert.org 896657Snate@binkert.org// Primary format for float point operate instructions: 906779SBrad.Beckmann@amd.comdef format FloatOp(code, *flags) {{ 916657Snate@binkert.org orig_code = code 926657Snate@binkert.org 936657Snate@binkert.org cblk = code 946657Snate@binkert.org iop = InstObjParams(name, Name, 'PredOp', 956657Snate@binkert.org {"code": cblk, 966657Snate@binkert.org "predicate_test": predicateTest}, 976657Snate@binkert.org flags) 986657Snate@binkert.org header_output = BasicDeclare.subst(iop) 996657Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 1006657Snate@binkert.org exec_output = FPAExecute.subst(iop) 1016657Snate@binkert.org 1026657Snate@binkert.org sng_cblk = code 1036657Snate@binkert.org sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1046657Snate@binkert.org {"code": sng_cblk, 1056657Snate@binkert.org "predicate_test": predicateTest}, 1066657Snate@binkert.org flags) 1076657Snate@binkert.org header_output += BasicDeclare.subst(sng_iop) 1086657Snate@binkert.org decoder_output += BasicConstructor.subst(sng_iop) 1096657Snate@binkert.org exec_output += FPAExecute.subst(sng_iop) 1106657Snate@binkert.org 1116657Snate@binkert.org dbl_code = re.sub(r'\.sf', '.df', orig_code) 1126657Snate@binkert.org 1136657Snate@binkert.org dbl_cblk = dbl_code 1146657Snate@binkert.org dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1157839Snilay@cs.wisc.edu {"code": dbl_cblk, 1167839Snilay@cs.wisc.edu "predicate_test": predicateTest}, 1177839Snilay@cs.wisc.edu flags) 1187839Snilay@cs.wisc.edu header_output += BasicDeclare.subst(dbl_iop) 1197839Snilay@cs.wisc.edu decoder_output += BasicConstructor.subst(dbl_iop) 1207839Snilay@cs.wisc.edu exec_output += FPAExecute.subst(dbl_iop) 1217839Snilay@cs.wisc.edu 1227839Snilay@cs.wisc.edu decode_block = FloatDoubleDecode.subst(iop) 1237839Snilay@cs.wisc.edu}}; 1247839Snilay@cs.wisc.edu 1257839Snilay@cs.wisc.edulet {{ 1267839Snilay@cs.wisc.edu calcFPCcCode = ''' 1277839Snilay@cs.wisc.edu uint16_t _in, _iz, _ic, _iv; 1287839Snilay@cs.wisc.edu 1297839Snilay@cs.wisc.edu _in = %(fReg1)s < %(fReg2)s; 1306657Snate@binkert.org _iz = %(fReg1)s == %(fReg2)s; 1316657Snate@binkert.org _ic = %(fReg1)s >= %(fReg2)s; 1326657Snate@binkert.org _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 1336657Snate@binkert.org 1346657Snate@binkert.org CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 1356657Snate@binkert.org (CondCodes & 0x0FFFFFFF); 1366657Snate@binkert.org ''' 1376657Snate@binkert.org}}; 1386657Snate@binkert.org 1396657Snate@binkert.orgdef format FloatCmp(fReg1, fReg2, *flags) {{ 1406657Snate@binkert.org code = calcFPCcCode % vars() 1416657Snate@binkert.org iop = InstObjParams(name, Name, 'PredOp', 1426657Snate@binkert.org {"code": code, 1436657Snate@binkert.org "predicate_test": predicateTest}, 1446657Snate@binkert.org flags) 1456657Snate@binkert.org header_output = BasicDeclare.subst(iop) 1466657Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 1476657Snate@binkert.org decode_block = BasicDecode.subst(iop) 1486657Snate@binkert.org exec_output = FPAExecute.subst(iop) 1496657Snate@binkert.org}}; 1506657Snate@binkert.org 1516657Snate@binkert.orglet {{ 1526657Snate@binkert.org header_output = ''' 1536657Snate@binkert.org StaticInstPtr 1546657Snate@binkert.org decodeExtensionRegLoadStore(ExtMachInst machInst); 1556657Snate@binkert.org ''' 1566657Snate@binkert.org decoder_output = ''' 1576657Snate@binkert.org StaticInstPtr 1586657Snate@binkert.org decodeExtensionRegLoadStore(ExtMachInst machInst) 1596657Snate@binkert.org { 1606657Snate@binkert.org const uint32_t opcode = bits(machInst, 24, 20); 1616877Ssteve.reinhardt@amd.com const uint32_t offset = bits(machInst, 7, 0); 1626657Snate@binkert.org const bool single = (bits(machInst, 8) == 0); 1636657Snate@binkert.org const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1646657Snate@binkert.org RegIndex vd; 1656657Snate@binkert.org if (single) { 1666657Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1676657Snate@binkert.org bits(machInst, 22)); 1687542SBrad.Beckmann@amd.com } else { 1697542SBrad.Beckmann@amd.com vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1706657Snate@binkert.org (bits(machInst, 22) << 5)); 1716877Ssteve.reinhardt@amd.com } 1726999Snate@binkert.org switch (bits(opcode, 4, 3)) { 1736877Ssteve.reinhardt@amd.com case 0x0: 1746877Ssteve.reinhardt@amd.com if (bits(opcode, 4, 1) == 0x2 && 1756877Ssteve.reinhardt@amd.com !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 1766877Ssteve.reinhardt@amd.com !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 1776877Ssteve.reinhardt@amd.com if ((bits(machInst, 7, 4) & 0xd) != 1) { 1786877Ssteve.reinhardt@amd.com break; 1796877Ssteve.reinhardt@amd.com } 1806877Ssteve.reinhardt@amd.com const IntRegIndex rt = 1816877Ssteve.reinhardt@amd.com (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1826877Ssteve.reinhardt@amd.com const IntRegIndex rt2 = 1836877Ssteve.reinhardt@amd.com (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1846877Ssteve.reinhardt@amd.com const bool op = bits(machInst, 20); 1856877Ssteve.reinhardt@amd.com uint32_t vm; 1866877Ssteve.reinhardt@amd.com if (single) { 1876877Ssteve.reinhardt@amd.com vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 1886877Ssteve.reinhardt@amd.com } else { 1896882SBrad.Beckmann@amd.com vm = (bits(machInst, 3, 0) << 1) | 1906882SBrad.Beckmann@amd.com (bits(machInst, 5) << 5); 1916882SBrad.Beckmann@amd.com } 1926882SBrad.Beckmann@amd.com if (op) { 1936882SBrad.Beckmann@amd.com return new Vmov2Core2Reg(machInst, rt, rt2, 1946882SBrad.Beckmann@amd.com (IntRegIndex)vm); 1956882SBrad.Beckmann@amd.com } else { 1966877Ssteve.reinhardt@amd.com return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 1976877Ssteve.reinhardt@amd.com rt, rt2); 1986877Ssteve.reinhardt@amd.com } 1996877Ssteve.reinhardt@amd.com } 2006657Snate@binkert.org break; 2016657Snate@binkert.org case 0x1: 2026999Snate@binkert.org switch (bits(opcode, 1, 0)) { 2036657Snate@binkert.org case 0x0: 2046657Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2056657Snate@binkert.org true, false, false, offset); 2066657Snate@binkert.org case 0x1: 2076657Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2086657Snate@binkert.org true, false, true, offset); 2097007Snate@binkert.org case 0x2: 2106657Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2116657Snate@binkert.org true, true, false, offset); 2126657Snate@binkert.org case 0x3: 2136657Snate@binkert.org // If rn == sp, then this is called vpop. 2146657Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2157007Snate@binkert.org true, true, true, offset); 2167007Snate@binkert.org } 2176657Snate@binkert.org case 0x2: 2187002Snate@binkert.org if (bits(opcode, 1, 0) == 0x2) { 2197002Snate@binkert.org // If rn == sp, then this is called vpush. 2207002Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2217002Snate@binkert.org false, true, false, offset); 2228229Snate@binkert.org } else if (bits(opcode, 1, 0) == 0x3) { 2238229Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2246657Snate@binkert.org false, true, true, offset); 2256657Snate@binkert.org } 2268229Snate@binkert.org // Fall through on purpose 2278229Snate@binkert.org case 0x3: 2288229Snate@binkert.org const bool up = (bits(machInst, 23) == 1); 2298229Snate@binkert.org const uint32_t imm = bits(machInst, 7, 0) << 2; 2306657Snate@binkert.org RegIndex vd; 2316657Snate@binkert.org if (single) { 2326657Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2336657Snate@binkert.org (bits(machInst, 22))); 2346793SBrad.Beckmann@amd.com } else { 2356657Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2366657Snate@binkert.org (bits(machInst, 22) << 5)); 2376657Snate@binkert.org } 2386657Snate@binkert.org if (bits(opcode, 1, 0) == 0x0) { 2396657Snate@binkert.org if (single) { 2407002Snate@binkert.org if (up) { 2416657Snate@binkert.org return new %(vstr_us)s(machInst, vd, rn, up, imm); 2427007Snate@binkert.org } else { 2437007Snate@binkert.org return new %(vstr_s)s(machInst, vd, rn, up, imm); 2447007Snate@binkert.org } 2457007Snate@binkert.org } else { 2467007Snate@binkert.org if (up) { 2476657Snate@binkert.org return new %(vstr_ud)s(machInst, vd, vd + 1, 2486877Ssteve.reinhardt@amd.com rn, up, imm); 2496877Ssteve.reinhardt@amd.com } else { 2506657Snate@binkert.org return new %(vstr_d)s(machInst, vd, vd + 1, 2516877Ssteve.reinhardt@amd.com rn, up, imm); 2526657Snate@binkert.org } 2536657Snate@binkert.org } 2547002Snate@binkert.org } else if (bits(opcode, 1, 0) == 0x1) { 2557002Snate@binkert.org if (single) { 2566657Snate@binkert.org if (up) { 2577567SBrad.Beckmann@amd.com return new %(vldr_us)s(machInst, vd, rn, up, imm); 2587567SBrad.Beckmann@amd.com } else { 2597922SBrad.Beckmann@amd.com return new %(vldr_s)s(machInst, vd, rn, up, imm); 2606881SBrad.Beckmann@amd.com } 2617002Snate@binkert.org } else { 2627002Snate@binkert.org if (up) { 2636657Snate@binkert.org return new %(vldr_ud)s(machInst, vd, vd + 1, 2647002Snate@binkert.org rn, up, imm); 2656902SBrad.Beckmann@amd.com } else { 2666863Sdrh5@cs.wisc.edu return new %(vldr_d)s(machInst, vd, vd + 1, 2676863Sdrh5@cs.wisc.edu rn, up, imm); 2687007Snate@binkert.org } 2696657Snate@binkert.org } 2706657Snate@binkert.org } 2716657Snate@binkert.org } 2726657Snate@binkert.org return new Unknown(machInst); 2736657Snate@binkert.org } 2746657Snate@binkert.org ''' % { 2756882SBrad.Beckmann@amd.com "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 2766882SBrad.Beckmann@amd.com "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 2776882SBrad.Beckmann@amd.com "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 2786882SBrad.Beckmann@amd.com "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 2796657Snate@binkert.org "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 2806657Snate@binkert.org "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 2816657Snate@binkert.org "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 2826657Snate@binkert.org "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 2837007Snate@binkert.org } 2847839Snilay@cs.wisc.edu}}; 2857839Snilay@cs.wisc.edu 2867839Snilay@cs.wisc.edudef format ExtensionRegLoadStore() {{ 2877839Snilay@cs.wisc.edu decode_block = ''' 2887839Snilay@cs.wisc.edu return decodeExtensionRegLoadStore(machInst); 2897839Snilay@cs.wisc.edu ''' 2907839Snilay@cs.wisc.edu}}; 2917839Snilay@cs.wisc.edu 2927839Snilay@cs.wisc.edulet {{ 2937839Snilay@cs.wisc.edu header_output = ''' 2947839Snilay@cs.wisc.edu StaticInstPtr 2957839Snilay@cs.wisc.edu decodeShortFpTransfer(ExtMachInst machInst); 2967007Snate@binkert.org ''' 2977007Snate@binkert.org decoder_output = ''' 2987007Snate@binkert.org StaticInstPtr 2997007Snate@binkert.org decodeShortFpTransfer(ExtMachInst machInst) 3007007Snate@binkert.org { 3017839Snilay@cs.wisc.edu const uint32_t l = bits(machInst, 20); 3027839Snilay@cs.wisc.edu const uint32_t c = bits(machInst, 8); 3037839Snilay@cs.wisc.edu const uint32_t a = bits(machInst, 23, 21); 3047839Snilay@cs.wisc.edu const uint32_t b = bits(machInst, 6, 5); 3057839Snilay@cs.wisc.edu if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 3067839Snilay@cs.wisc.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 3077839Snilay@cs.wisc.edu return new Unknown(machInst); 3087839Snilay@cs.wisc.edu } 3097839Snilay@cs.wisc.edu if (l == 0 && c == 0) { 3107839Snilay@cs.wisc.edu if (a == 0) { 3117839Snilay@cs.wisc.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3127839Snilay@cs.wisc.edu bits(machInst, 7); 3137007Snate@binkert.org const IntRegIndex rt = 3147007Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3157002Snate@binkert.org if (bits(machInst, 20) == 1) { 3166657Snate@binkert.org return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3176657Snate@binkert.org } else { 3186657Snate@binkert.org return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3197055Snate@binkert.org } 3206657Snate@binkert.org } else if (a == 0x7) { 3216657Snate@binkert.org const IntRegIndex rt = 3226657Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3236863Sdrh5@cs.wisc.edu uint32_t specReg = bits(machInst, 19, 16); 3247055Snate@binkert.org switch (specReg) { 3257567SBrad.Beckmann@amd.com case 0: 3267567SBrad.Beckmann@amd.com specReg = MISCREG_FPSID; 3277567SBrad.Beckmann@amd.com break; 3287567SBrad.Beckmann@amd.com case 1: 3297567SBrad.Beckmann@amd.com specReg = MISCREG_FPSCR; 3307542SBrad.Beckmann@amd.com break; 3317542SBrad.Beckmann@amd.com case 8: 3326657Snate@binkert.org specReg = MISCREG_FPEXC; 3337007Snate@binkert.org break; 3346657Snate@binkert.org default: 3356657Snate@binkert.org return new Unknown(machInst); 3366657Snate@binkert.org } 3376657Snate@binkert.org return new Vmsr(machInst, (IntRegIndex)specReg, rt); 3386657Snate@binkert.org } 3396657Snate@binkert.org } else if (l == 0 && c == 1) { 3406657Snate@binkert.org if (bits(a, 2) == 0) { 3416657Snate@binkert.org uint32_t vd = (bits(machInst, 7) << 5) | 3427839Snilay@cs.wisc.edu (bits(machInst, 19, 16) << 1); 3437839Snilay@cs.wisc.edu uint32_t index, size; 3447839Snilay@cs.wisc.edu const IntRegIndex rt = 3457839Snilay@cs.wisc.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3467839Snilay@cs.wisc.edu if (bits(machInst, 22) == 1) { 3477839Snilay@cs.wisc.edu size = 8; 3487839Snilay@cs.wisc.edu index = (bits(machInst, 21) << 2) | 3497839Snilay@cs.wisc.edu bits(machInst, 6, 5); 3507839Snilay@cs.wisc.edu } else if (bits(machInst, 5) == 1) { 3517839Snilay@cs.wisc.edu size = 16; 3527839Snilay@cs.wisc.edu index = (bits(machInst, 21) << 1) | 3537839Snilay@cs.wisc.edu bits(machInst, 6); 3547839Snilay@cs.wisc.edu } else if (bits(machInst, 6) == 0) { 3557839Snilay@cs.wisc.edu size = 32; 3567839Snilay@cs.wisc.edu index = bits(machInst, 21); 3577839Snilay@cs.wisc.edu } else { 3586657Snate@binkert.org return new Unknown(machInst); 3596657Snate@binkert.org } 3606657Snate@binkert.org if (index >= (32 / size)) { 3616657Snate@binkert.org index -= (32 / size); 3627839Snilay@cs.wisc.edu vd++; 3637839Snilay@cs.wisc.edu } 3647839Snilay@cs.wisc.edu switch (size) { 3657839Snilay@cs.wisc.edu case 8: 3667839Snilay@cs.wisc.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 3677839Snilay@cs.wisc.edu rt, index); 3687839Snilay@cs.wisc.edu case 16: 3697839Snilay@cs.wisc.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 3707839Snilay@cs.wisc.edu rt, index); 3717839Snilay@cs.wisc.edu case 32: 3727839Snilay@cs.wisc.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 3737839Snilay@cs.wisc.edu } 3747839Snilay@cs.wisc.edu } else if (bits(b, 1) == 0) { 3757839Snilay@cs.wisc.edu // A8-594 3767839Snilay@cs.wisc.edu return new WarnUnimplemented("vdup", machInst); 3777839Snilay@cs.wisc.edu } 3786657Snate@binkert.org } else if (l == 1 && c == 0) { 3796657Snate@binkert.org if (a == 0) { 3806657Snate@binkert.org const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3816657Snate@binkert.org bits(machInst, 7); 3827007Snate@binkert.org const IntRegIndex rt = 3836657Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3846657Snate@binkert.org if (bits(machInst, 20) == 1) { 3856657Snate@binkert.org return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3866657Snate@binkert.org } else { 3876657Snate@binkert.org return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3886657Snate@binkert.org } 3896657Snate@binkert.org } else if (a == 7) { 3906657Snate@binkert.org const IntRegIndex rt = 3916657Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3926657Snate@binkert.org uint32_t specReg = bits(machInst, 19, 16); 3937007Snate@binkert.org switch (specReg) { 3946657Snate@binkert.org case 0: 3956657Snate@binkert.org specReg = MISCREG_FPSID; 3966657Snate@binkert.org break; 3976657Snate@binkert.org case 1: 3986657Snate@binkert.org specReg = MISCREG_FPSCR; 3996999Snate@binkert.org break; 4006657Snate@binkert.org case 6: 4016657Snate@binkert.org specReg = MISCREG_MVFR1; 4026657Snate@binkert.org break; 4036657Snate@binkert.org case 7: 4047007Snate@binkert.org specReg = MISCREG_MVFR0; 4056657Snate@binkert.org break; 4066657Snate@binkert.org case 8: 4076657Snate@binkert.org specReg = MISCREG_FPEXC; 4086657Snate@binkert.org break; 4096657Snate@binkert.org default: 4107832Snate@binkert.org return new Unknown(machInst); 4117002Snate@binkert.org } 4127002Snate@binkert.org return new Vmrs(machInst, rt, (IntRegIndex)specReg); 4137002Snate@binkert.org } 4147056Snate@binkert.org } else { 4158232Snate@binkert.org uint32_t vd = (bits(machInst, 7) << 5) | 4168232Snate@binkert.org (bits(machInst, 19, 16) << 1); 4176657Snate@binkert.org uint32_t index, size; 4188229Snate@binkert.org const IntRegIndex rt = 4196657Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 4206657Snate@binkert.org const bool u = (bits(machInst, 23) == 1); 4217056Snate@binkert.org if (bits(machInst, 22) == 1) { 4227056Snate@binkert.org size = 8; 4236657Snate@binkert.org index = (bits(machInst, 21) << 2) | 4247002Snate@binkert.org bits(machInst, 6, 5); 4257002Snate@binkert.org } else if (bits(machInst, 5) == 1) { 4266657Snate@binkert.org size = 16; 4276657Snate@binkert.org index = (bits(machInst, 21) << 1) | 4286657Snate@binkert.org bits(machInst, 6); 4296657Snate@binkert.org } else if (bits(machInst, 6) == 0 && !u) { 4306657Snate@binkert.org size = 32; 4316793SBrad.Beckmann@amd.com index = bits(machInst, 21); 4326657Snate@binkert.org } else { 4336657Snate@binkert.org return new Unknown(machInst); 4346657Snate@binkert.org } 4356657Snate@binkert.org if (index >= (32 / size)) { 4366877Ssteve.reinhardt@amd.com index -= (32 / size); 4376877Ssteve.reinhardt@amd.com vd++; 4386877Ssteve.reinhardt@amd.com } 4396877Ssteve.reinhardt@amd.com switch (size) { 4406877Ssteve.reinhardt@amd.com case 8: 4416877Ssteve.reinhardt@amd.com if (u) { 4426657Snate@binkert.org return new VmovRegCoreUB(machInst, rt, 4437542SBrad.Beckmann@amd.com (IntRegIndex)vd, index); 4446657Snate@binkert.org } else { 4457007Snate@binkert.org return new VmovRegCoreSB(machInst, rt, 4466657Snate@binkert.org (IntRegIndex)vd, index); 4476657Snate@binkert.org } 4487007Snate@binkert.org case 16: 4496657Snate@binkert.org if (u) { 4506877Ssteve.reinhardt@amd.com return new VmovRegCoreUH(machInst, rt, 4516877Ssteve.reinhardt@amd.com (IntRegIndex)vd, index); 4526657Snate@binkert.org } else { 4536877Ssteve.reinhardt@amd.com return new VmovRegCoreSH(machInst, rt, 4546877Ssteve.reinhardt@amd.com (IntRegIndex)vd, index); 4556877Ssteve.reinhardt@amd.com } 4566877Ssteve.reinhardt@amd.com case 32: 4576877Ssteve.reinhardt@amd.com return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 4586969SBrad.Beckmann@amd.com } 4598532SLisa.Hsu@amd.com } 4606657Snate@binkert.org return new Unknown(machInst); 4617567SBrad.Beckmann@amd.com } 4627567SBrad.Beckmann@amd.com ''' 4637567SBrad.Beckmann@amd.com}}; 4647567SBrad.Beckmann@amd.com 4657567SBrad.Beckmann@amd.comdef format ShortFpTransfer() {{ 4667567SBrad.Beckmann@amd.com decode_block = ''' 4676657Snate@binkert.org return decodeShortFpTransfer(machInst); 4686882SBrad.Beckmann@amd.com ''' 4696882SBrad.Beckmann@amd.com}}; 4706882SBrad.Beckmann@amd.com 4716882SBrad.Beckmann@amd.comlet {{ 4726882SBrad.Beckmann@amd.com header_output = ''' 4736882SBrad.Beckmann@amd.com StaticInstPtr 4746882SBrad.Beckmann@amd.com decodeVfpData(ExtMachInst machInst); 4758189SLisa.Hsu@amd.com ''' 4768189SLisa.Hsu@amd.com decoder_output = ''' 4776877Ssteve.reinhardt@amd.com StaticInstPtr 4788189SLisa.Hsu@amd.com decodeVfpData(ExtMachInst machInst) 4798189SLisa.Hsu@amd.com { 4808189SLisa.Hsu@amd.com const uint32_t opc1 = bits(machInst, 23, 20); 4818189SLisa.Hsu@amd.com const uint32_t opc2 = bits(machInst, 19, 16); 4826882SBrad.Beckmann@amd.com const uint32_t opc3 = bits(machInst, 7, 6); 4836882SBrad.Beckmann@amd.com //const uint32_t opc4 = bits(machInst, 3, 0); 4846882SBrad.Beckmann@amd.com switch (opc1 & 0xb /* 1011 */) { 4856882SBrad.Beckmann@amd.com case 0x0: 4866882SBrad.Beckmann@amd.com return new WarnUnimplemented("vmla, vmls", machInst); 4876882SBrad.Beckmann@amd.com case 0x2: 4886882SBrad.Beckmann@amd.com if ((opc3 & 0x1) == 0) { 4896882SBrad.Beckmann@amd.com uint32_t vd; 4906882SBrad.Beckmann@amd.com uint32_t vm; 4916882SBrad.Beckmann@amd.com uint32_t vn; 4928189SLisa.Hsu@amd.com if (bits(machInst, 8) == 0) { 4936882SBrad.Beckmann@amd.com vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 4946882SBrad.Beckmann@amd.com vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 4956882SBrad.Beckmann@amd.com vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); 4968189SLisa.Hsu@amd.com return new VmulS(machInst, (IntRegIndex)vd, 4978189SLisa.Hsu@amd.com (IntRegIndex)vn, (IntRegIndex)vm); 4988189SLisa.Hsu@amd.com } else { 4998189SLisa.Hsu@amd.com vd = (bits(machInst, 22) << 5) | 5006888SBrad.Beckmann@amd.com (bits(machInst, 15, 12) << 1); 5016888SBrad.Beckmann@amd.com vm = (bits(machInst, 5) << 5) | 5026888SBrad.Beckmann@amd.com (bits(machInst, 3, 0) << 1); 5036888SBrad.Beckmann@amd.com vn = (bits(machInst, 7) << 5) | 5046888SBrad.Beckmann@amd.com (bits(machInst, 19, 16) << 1); 5058189SLisa.Hsu@amd.com return new VmulD(machInst, (IntRegIndex)vd, 5066888SBrad.Beckmann@amd.com (IntRegIndex)vn, (IntRegIndex)vm); 5076888SBrad.Beckmann@amd.com } 5086657Snate@binkert.org } 5096888SBrad.Beckmann@amd.com case 0x1: 5106888SBrad.Beckmann@amd.com return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst); 5116888SBrad.Beckmann@amd.com case 0x3: 5126888SBrad.Beckmann@amd.com if ((opc3 & 0x1) == 0) { 5136657Snate@binkert.org return new WarnUnimplemented("vadd", machInst); 5146657Snate@binkert.org } else { 5156657Snate@binkert.org return new WarnUnimplemented("vsub", machInst); 5166657Snate@binkert.org } 5176657Snate@binkert.org case 0x8: 5186657Snate@binkert.org if ((opc3 & 0x1) == 0) { 5196657Snate@binkert.org return new WarnUnimplemented("vdiv", machInst); 5206657Snate@binkert.org } 5216657Snate@binkert.org break; 5227007Snate@binkert.org case 0xb: 5237007Snate@binkert.org if ((opc3 & 0x1) == 0) { 5246657Snate@binkert.org uint32_t vd; 5257007Snate@binkert.org const uint32_t baseImm = 5267007Snate@binkert.org bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 5277007Snate@binkert.org if (bits(machInst, 8) == 0) { 5286657Snate@binkert.org vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5296657Snate@binkert.org uint32_t imm = vfp_modified_imm(baseImm, false); 5306657Snate@binkert.org return new VmovImmS(machInst, (IntRegIndex)vd, imm); 5317007Snate@binkert.org } else { 5327542SBrad.Beckmann@amd.com vd = (bits(machInst, 22) << 5) | 5337542SBrad.Beckmann@amd.com (bits(machInst, 15, 12) << 1); 5347007Snate@binkert.org uint64_t imm = vfp_modified_imm(baseImm, true); 5356657Snate@binkert.org return new VmovImmD(machInst, (IntRegIndex)vd, imm); 5366657Snate@binkert.org } 5376657Snate@binkert.org } 5386657Snate@binkert.org switch (opc2) { 5396657Snate@binkert.org case 0x0: 5406657Snate@binkert.org if (opc3 == 1) { 5416657Snate@binkert.org uint32_t vd; 5426657Snate@binkert.org uint32_t vm; 5436657Snate@binkert.org if (bits(machInst, 8) == 0) { 5446657Snate@binkert.org vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5456657Snate@binkert.org vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5466657Snate@binkert.org return new VmovRegS(machInst, 5476657Snate@binkert.org (IntRegIndex)vd, (IntRegIndex)vm); 5486657Snate@binkert.org } else { 5496657Snate@binkert.org vd = (bits(machInst, 22) << 5) | 5506657Snate@binkert.org (bits(machInst, 15, 12) << 1); 5516657Snate@binkert.org vm = (bits(machInst, 5) << 5) | 5526657Snate@binkert.org (bits(machInst, 3, 0) << 1); 5536657Snate@binkert.org return new VmovRegD(machInst, 5546657Snate@binkert.org (IntRegIndex)vd, (IntRegIndex)vm); 5556657Snate@binkert.org } 5566657Snate@binkert.org } else { 5576657Snate@binkert.org uint32_t vd; 5586657Snate@binkert.org uint32_t vm; 5596657Snate@binkert.org if (bits(machInst, 8) == 0) { 5606657Snate@binkert.org vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5616657Snate@binkert.org vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5626657Snate@binkert.org return new VabsS(machInst, 5637007Snate@binkert.org (IntRegIndex)vd, (IntRegIndex)vm); 5646657Snate@binkert.org } else { 5656657Snate@binkert.org vd = (bits(machInst, 22) << 5) | 5666657Snate@binkert.org (bits(machInst, 15, 12) << 1); 5676657Snate@binkert.org vm = (bits(machInst, 5) << 5) | 5687007Snate@binkert.org (bits(machInst, 3, 0) << 1); 5696657Snate@binkert.org return new VabsD(machInst, 5707007Snate@binkert.org (IntRegIndex)vd, (IntRegIndex)vm); 5717007Snate@binkert.org } 5726657Snate@binkert.org } 5736657Snate@binkert.org case 0x1: 5746657Snate@binkert.org if (opc3 == 1) { 5756657Snate@binkert.org uint32_t vd; 5766657Snate@binkert.org uint32_t vm; 5776657Snate@binkert.org if (bits(machInst, 8) == 0) { 5786657Snate@binkert.org vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5796657Snate@binkert.org vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5806657Snate@binkert.org return new VnegS(machInst, 5816657Snate@binkert.org (IntRegIndex)vd, (IntRegIndex)vm); 5826657Snate@binkert.org } else { 5836657Snate@binkert.org vd = (bits(machInst, 22) << 5) | 5846657Snate@binkert.org (bits(machInst, 15, 12) << 1); 5856657Snate@binkert.org vm = (bits(machInst, 5) << 5) | 5866657Snate@binkert.org (bits(machInst, 3, 0) << 1); 5877566SBrad.Beckmann@amd.com return new VnegD(machInst, 5886657Snate@binkert.org (IntRegIndex)vd, (IntRegIndex)vm); 5896657Snate@binkert.org } 5906657Snate@binkert.org } else { 5916657Snate@binkert.org return new WarnUnimplemented("vsqrt", machInst); 5926657Snate@binkert.org } 5938308Stushar@csail.mit.edu case 0x2: 5946657Snate@binkert.org case 0x3: 5956657Snate@binkert.org // Between half and single precision. 5966657Snate@binkert.org return new WarnUnimplemented("vcvtb, vcvtt", machInst); 5977007Snate@binkert.org case 0x4: 5987007Snate@binkert.org case 0x5: 5998308Stushar@csail.mit.edu return new WarnUnimplemented("vcmp, vcmpe", machInst); 6006657Snate@binkert.org case 0x7: 6016657Snate@binkert.org if (opc3 == 0x3) { 6026657Snate@binkert.org // Between double and single precision. 6036657Snate@binkert.org return new WarnUnimplemented("vcvt", machInst); 6046657Snate@binkert.org } 6056657Snate@binkert.org break; 6066657Snate@binkert.org case 0x8: 6076657Snate@binkert.org // Between FP and int. 6086657Snate@binkert.org return new WarnUnimplemented("vcvt, vcvtr", machInst); 6096657Snate@binkert.org case 0xa: 6106657Snate@binkert.org case 0xb: 6116657Snate@binkert.org // Between FP and fixed point. 6128187SLisa.Hsu@amd.com return new WarnUnimplemented("vcvt", machInst); 6136657Snate@binkert.org case 0xc: 6146657Snate@binkert.org case 0xd: 6156657Snate@binkert.org // Between FP and int. 6166657Snate@binkert.org return new WarnUnimplemented("vcvt, vcvtr", machInst); 6176657Snate@binkert.org case 0xe: 6186657Snate@binkert.org case 0xf: 6196657Snate@binkert.org // Between FP and fixed point. 6206657Snate@binkert.org return new WarnUnimplemented("vcvt", machInst); 6216657Snate@binkert.org } 6227454Snate@binkert.org break; 6236657Snate@binkert.org } 6246657Snate@binkert.org return new Unknown(machInst); 6256657Snate@binkert.org } 6266657Snate@binkert.org ''' 6277007Snate@binkert.org}}; 6287056Snate@binkert.org 6297007Snate@binkert.orgdef format VfpData() {{ 6307007Snate@binkert.org decode_block = ''' 6316657Snate@binkert.org return decodeVfpData(machInst); 6327566SBrad.Beckmann@amd.com ''' 6337566SBrad.Beckmann@amd.com}}; 6347566SBrad.Beckmann@amd.com