fp.isa revision 7335:76f94f8ed949
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 37178Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47178Sgblack@eecs.umich.edu// All rights reserved 57178Sgblack@eecs.umich.edu// 67178Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77178Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87178Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97178Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107178Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117178Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127178Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137178Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147178Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Floating Point operate instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edudef template FPAExecute {{ 496019Shines@cs.fsu.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 506019Shines@cs.fsu.edu { 516019Shines@cs.fsu.edu Fault fault = NoFault; 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edu %(fp_enable_check)s; 546019Shines@cs.fsu.edu 556019Shines@cs.fsu.edu %(op_decl)s; 566019Shines@cs.fsu.edu %(op_rd)s; 576019Shines@cs.fsu.edu 586243Sgblack@eecs.umich.edu if (%(predicate_test)s) { 596243Sgblack@eecs.umich.edu %(code)s; 606243Sgblack@eecs.umich.edu if (fault == NoFault) { 616243Sgblack@eecs.umich.edu %(op_wb)s; 626243Sgblack@eecs.umich.edu } 636019Shines@cs.fsu.edu } 646019Shines@cs.fsu.edu 656019Shines@cs.fsu.edu return fault; 666019Shines@cs.fsu.edu } 676019Shines@cs.fsu.edu}}; 686019Shines@cs.fsu.edu 696019Shines@cs.fsu.edudef template FloatDoubleDecode {{ 706019Shines@cs.fsu.edu { 716019Shines@cs.fsu.edu ArmStaticInst *i = NULL; 726019Shines@cs.fsu.edu switch (OPCODE_19 << 1 | OPCODE_7) 736019Shines@cs.fsu.edu { 746019Shines@cs.fsu.edu case 0: 756019Shines@cs.fsu.edu i = (ArmStaticInst *)new %(class_name)sS(machInst); 766019Shines@cs.fsu.edu break; 776019Shines@cs.fsu.edu case 1: 786019Shines@cs.fsu.edu i = (ArmStaticInst *)new %(class_name)sD(machInst); 796019Shines@cs.fsu.edu break; 806019Shines@cs.fsu.edu case 2: 816019Shines@cs.fsu.edu case 3: 826019Shines@cs.fsu.edu default: 836019Shines@cs.fsu.edu panic("Cannot decode float/double nature of the instruction"); 846019Shines@cs.fsu.edu } 856019Shines@cs.fsu.edu return i; 866019Shines@cs.fsu.edu } 876019Shines@cs.fsu.edu}}; 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu// Primary format for float point operate instructions: 906019Shines@cs.fsu.edudef format FloatOp(code, *flags) {{ 916019Shines@cs.fsu.edu orig_code = code 926019Shines@cs.fsu.edu 936019Shines@cs.fsu.edu cblk = code 946252Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 956243Sgblack@eecs.umich.edu {"code": cblk, 966243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 976243Sgblack@eecs.umich.edu flags) 986019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 996019Shines@cs.fsu.edu decoder_output = BasicConstructor.subst(iop) 1006019Shines@cs.fsu.edu exec_output = FPAExecute.subst(iop) 1016019Shines@cs.fsu.edu 1026019Shines@cs.fsu.edu sng_cblk = code 1036252Sgblack@eecs.umich.edu sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1046243Sgblack@eecs.umich.edu {"code": sng_cblk, 1056243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1066243Sgblack@eecs.umich.edu flags) 1076019Shines@cs.fsu.edu header_output += BasicDeclare.subst(sng_iop) 1086019Shines@cs.fsu.edu decoder_output += BasicConstructor.subst(sng_iop) 1096019Shines@cs.fsu.edu exec_output += FPAExecute.subst(sng_iop) 1106019Shines@cs.fsu.edu 1116019Shines@cs.fsu.edu dbl_code = re.sub(r'\.sf', '.df', orig_code) 1126019Shines@cs.fsu.edu 1136019Shines@cs.fsu.edu dbl_cblk = dbl_code 1146252Sgblack@eecs.umich.edu dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1156243Sgblack@eecs.umich.edu {"code": dbl_cblk, 1166243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1176243Sgblack@eecs.umich.edu flags) 1186019Shines@cs.fsu.edu header_output += BasicDeclare.subst(dbl_iop) 1196019Shines@cs.fsu.edu decoder_output += BasicConstructor.subst(dbl_iop) 1206019Shines@cs.fsu.edu exec_output += FPAExecute.subst(dbl_iop) 1216019Shines@cs.fsu.edu 1226019Shines@cs.fsu.edu decode_block = FloatDoubleDecode.subst(iop) 1236019Shines@cs.fsu.edu}}; 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edulet {{ 1266019Shines@cs.fsu.edu calcFPCcCode = ''' 1276019Shines@cs.fsu.edu uint16_t _in, _iz, _ic, _iv; 1286019Shines@cs.fsu.edu 1296019Shines@cs.fsu.edu _in = %(fReg1)s < %(fReg2)s; 1306019Shines@cs.fsu.edu _iz = %(fReg1)s == %(fReg2)s; 1316019Shines@cs.fsu.edu _ic = %(fReg1)s >= %(fReg2)s; 1326019Shines@cs.fsu.edu _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 1336019Shines@cs.fsu.edu 1346724Sgblack@eecs.umich.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 1356724Sgblack@eecs.umich.edu (CondCodes & 0x0FFFFFFF); 1366019Shines@cs.fsu.edu ''' 1376019Shines@cs.fsu.edu}}; 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edudef format FloatCmp(fReg1, fReg2, *flags) {{ 1406019Shines@cs.fsu.edu code = calcFPCcCode % vars() 1416252Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 1426243Sgblack@eecs.umich.edu {"code": code, 1436243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1446243Sgblack@eecs.umich.edu flags) 1456019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 1466019Shines@cs.fsu.edu decoder_output = BasicConstructor.subst(iop) 1476019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 1486019Shines@cs.fsu.edu exec_output = FPAExecute.subst(iop) 1496019Shines@cs.fsu.edu}}; 1506019Shines@cs.fsu.edu 1517356Sgblack@eecs.umich.edudef format ExtensionRegLoadStore() {{ 1527356Sgblack@eecs.umich.edu decode_block = ''' 1537356Sgblack@eecs.umich.edu { 1547356Sgblack@eecs.umich.edu const uint32_t opcode = bits(machInst, 24, 20); 1557356Sgblack@eecs.umich.edu const uint32_t offset = bits(machInst, 7, 0); 1567356Sgblack@eecs.umich.edu const bool single = bits(machInst, 22); 1577356Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1587356Sgblack@eecs.umich.edu RegIndex vd; 1597178Sgblack@eecs.umich.edu if (single) { 1607178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1617178Sgblack@eecs.umich.edu bits(machInst, 22)); 1627337Sgblack@eecs.umich.edu } else { 1637178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1647178Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 1657178Sgblack@eecs.umich.edu } 1667178Sgblack@eecs.umich.edu switch (bits(opcode, 4, 3)) { 1677178Sgblack@eecs.umich.edu case 0x0: 1687178Sgblack@eecs.umich.edu if (bits(opcode, 4, 1) == 0x2 && 1697178Sgblack@eecs.umich.edu !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 1707178Sgblack@eecs.umich.edu !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 1717178Sgblack@eecs.umich.edu if ((bits(machInst, 7, 4) & 0xd) != 1) { 1727178Sgblack@eecs.umich.edu break; 1737178Sgblack@eecs.umich.edu } 1747335Sgblack@eecs.umich.edu const IntRegIndex rt = 1757335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1767335Sgblack@eecs.umich.edu const IntRegIndex rt2 = 1777335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1787335Sgblack@eecs.umich.edu const bool op = bits(machInst, 20); 1797335Sgblack@eecs.umich.edu uint32_t vm; 1807335Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 1817335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 1827335Sgblack@eecs.umich.edu } else { 1837335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | 1847335Sgblack@eecs.umich.edu (bits(machInst, 5) << 5); 1857335Sgblack@eecs.umich.edu } 1867337Sgblack@eecs.umich.edu if (op) { 1877335Sgblack@eecs.umich.edu return new Vmov2Core2Reg(machInst, rt, rt2, 1887335Sgblack@eecs.umich.edu (IntRegIndex)vm); 1897335Sgblack@eecs.umich.edu } else { 1907335Sgblack@eecs.umich.edu return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 1917335Sgblack@eecs.umich.edu rt, rt2); 1927335Sgblack@eecs.umich.edu } 1937335Sgblack@eecs.umich.edu } 1947335Sgblack@eecs.umich.edu break; 1957335Sgblack@eecs.umich.edu case 0x1: 1967335Sgblack@eecs.umich.edu switch (bits(opcode, 1, 0)) { 1977335Sgblack@eecs.umich.edu case 0x0: 1987335Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1997178Sgblack@eecs.umich.edu true, false, false, offset); 2007178Sgblack@eecs.umich.edu case 0x1: 2017178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2027178Sgblack@eecs.umich.edu true, false, true, offset); 2037178Sgblack@eecs.umich.edu case 0x2: 2047178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2057178Sgblack@eecs.umich.edu true, true, false, offset); 2067178Sgblack@eecs.umich.edu case 0x3: 2077178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpop. 2087178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2097178Sgblack@eecs.umich.edu true, true, true, offset); 2107178Sgblack@eecs.umich.edu } 2117178Sgblack@eecs.umich.edu case 0x2: 2127178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x2) { 2137178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpush. 2147178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2157178Sgblack@eecs.umich.edu false, true, false, offset); 2167178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x3) { 2177178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2187178Sgblack@eecs.umich.edu false, true, true, offset); 2197178Sgblack@eecs.umich.edu } 2207178Sgblack@eecs.umich.edu // Fall through on purpose 2217178Sgblack@eecs.umich.edu case 0x3: 2227178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x0) { 2237178Sgblack@eecs.umich.edu return new WarnUnimplemented("vstr", machInst); 2247178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x1) { 2257178Sgblack@eecs.umich.edu return new WarnUnimplemented("vldr", machInst); 2267178Sgblack@eecs.umich.edu } 2277178Sgblack@eecs.umich.edu } 2287346Sgblack@eecs.umich.edu return new Unknown(machInst); 2297346Sgblack@eecs.umich.edu } 2307346Sgblack@eecs.umich.edu ''' 2317346Sgblack@eecs.umich.edu}}; 2327346Sgblack@eecs.umich.edu 2337346Sgblack@eecs.umich.edudef format ShortFpTransfer() {{ 2347346Sgblack@eecs.umich.edu decode_block = ''' 2357346Sgblack@eecs.umich.edu { 2367346Sgblack@eecs.umich.edu const uint32_t l = bits(machInst, 20); 2377346Sgblack@eecs.umich.edu const uint32_t c = bits(machInst, 8); 2387178Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 23, 21); 2397346Sgblack@eecs.umich.edu const uint32_t b = bits(machInst, 6, 5); 2407346Sgblack@eecs.umich.edu if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 2417346Sgblack@eecs.umich.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 2427346Sgblack@eecs.umich.edu return new Unknown(machInst); 2437346Sgblack@eecs.umich.edu } 2447346Sgblack@eecs.umich.edu if (l == 0 && c == 0) { 2457346Sgblack@eecs.umich.edu if (a == 0) { 2467346Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 2477346Sgblack@eecs.umich.edu bits(machInst, 7); 2487346Sgblack@eecs.umich.edu const IntRegIndex rt = 2497346Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2507346Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 2517346Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 2527346Sgblack@eecs.umich.edu } else { 2537346Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 2547178Sgblack@eecs.umich.edu } 2557337Sgblack@eecs.umich.edu } else if (a == 0x7) { 2567337Sgblack@eecs.umich.edu const IntRegIndex rt = 2577337Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2587337Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 2597337Sgblack@eecs.umich.edu switch (specReg) { 2607337Sgblack@eecs.umich.edu case 0: 2617337Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 2627337Sgblack@eecs.umich.edu break; 2637337Sgblack@eecs.umich.edu case 1: 2647337Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 2657337Sgblack@eecs.umich.edu break; 2667337Sgblack@eecs.umich.edu case 8: 2677337Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 2687337Sgblack@eecs.umich.edu break; 2697337Sgblack@eecs.umich.edu default: 2707178Sgblack@eecs.umich.edu return new Unknown(machInst); 2717178Sgblack@eecs.umich.edu } 2727178Sgblack@eecs.umich.edu return new Vmsr(machInst, (IntRegIndex)specReg, rt); 2737178Sgblack@eecs.umich.edu } 2747337Sgblack@eecs.umich.edu } else if (l == 0 && c == 1) { 2757337Sgblack@eecs.umich.edu if (bits(a, 2) == 0) { 2767337Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 2777337Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 2787346Sgblack@eecs.umich.edu uint32_t index, size; 2797346Sgblack@eecs.umich.edu const IntRegIndex rt = 2807346Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2817346Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 2827346Sgblack@eecs.umich.edu size = 8; 2837337Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 2847178Sgblack@eecs.umich.edu bits(machInst, 6, 5); 2857321Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 2867356Sgblack@eecs.umich.edu size = 16; 2877321Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 2887356Sgblack@eecs.umich.edu bits(machInst, 6); 2897356Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0) { 2907356Sgblack@eecs.umich.edu size = 32; 2917356Sgblack@eecs.umich.edu index = bits(machInst, 21); 2927356Sgblack@eecs.umich.edu } else { 2937356Sgblack@eecs.umich.edu return new Unknown(machInst); 2947356Sgblack@eecs.umich.edu } 2957356Sgblack@eecs.umich.edu if (index >= (32 / size)) { 2967356Sgblack@eecs.umich.edu index -= (32 / size); 2977356Sgblack@eecs.umich.edu vd++; 2987356Sgblack@eecs.umich.edu } 2997356Sgblack@eecs.umich.edu switch (size) { 3007321Sgblack@eecs.umich.edu case 8: 3017321Sgblack@eecs.umich.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 3027321Sgblack@eecs.umich.edu rt, index); 3037321Sgblack@eecs.umich.edu case 16: 3047321Sgblack@eecs.umich.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 3057321Sgblack@eecs.umich.edu rt, index); 3067321Sgblack@eecs.umich.edu case 32: 3077321Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 3087321Sgblack@eecs.umich.edu } 3097321Sgblack@eecs.umich.edu } else if (bits(b, 1) == 0) { 3107321Sgblack@eecs.umich.edu // A8-594 3117335Sgblack@eecs.umich.edu return new WarnUnimplemented("vdup", machInst); 3127335Sgblack@eecs.umich.edu } 3137335Sgblack@eecs.umich.edu } else if (l == 1 && c == 0) { 3147335Sgblack@eecs.umich.edu if (a == 0) { 3157335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3167335Sgblack@eecs.umich.edu bits(machInst, 7); 3177335Sgblack@eecs.umich.edu const IntRegIndex rt = 3187335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3197335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3207321Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3217323Sgblack@eecs.umich.edu } else { 3227323Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3237323Sgblack@eecs.umich.edu } 3247323Sgblack@eecs.umich.edu } else if (a == 7) { 3257323Sgblack@eecs.umich.edu const IntRegIndex rt = 3267323Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3277323Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3287323Sgblack@eecs.umich.edu switch (specReg) { 3297323Sgblack@eecs.umich.edu case 0: 3307323Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3317323Sgblack@eecs.umich.edu break; 3327323Sgblack@eecs.umich.edu case 1: 3337323Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3347323Sgblack@eecs.umich.edu break; 3357323Sgblack@eecs.umich.edu case 6: 3367323Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 3377323Sgblack@eecs.umich.edu break; 3387321Sgblack@eecs.umich.edu case 7: 3397321Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 3407321Sgblack@eecs.umich.edu break; 3417335Sgblack@eecs.umich.edu case 8: 3427335Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 3437335Sgblack@eecs.umich.edu break; 3447335Sgblack@eecs.umich.edu default: 3457335Sgblack@eecs.umich.edu return new Unknown(machInst); 3467335Sgblack@eecs.umich.edu } 3477335Sgblack@eecs.umich.edu return new Vmrs(machInst, rt, (IntRegIndex)specReg); 3487335Sgblack@eecs.umich.edu } 3497335Sgblack@eecs.umich.edu } else { 3507335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 3517335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 3527335Sgblack@eecs.umich.edu uint32_t index, size; 3537335Sgblack@eecs.umich.edu const IntRegIndex rt = 3547335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3557335Sgblack@eecs.umich.edu const bool u = (bits(machInst, 23) == 1); 3567335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 3577335Sgblack@eecs.umich.edu size = 8; 3587335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 3597335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 3607335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 3617335Sgblack@eecs.umich.edu size = 16; 3627335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 3637335Sgblack@eecs.umich.edu bits(machInst, 6); 3647335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0 && !u) { 3657335Sgblack@eecs.umich.edu size = 32; 3667335Sgblack@eecs.umich.edu index = bits(machInst, 21); 3677335Sgblack@eecs.umich.edu } else { 3687335Sgblack@eecs.umich.edu return new Unknown(machInst); 3697335Sgblack@eecs.umich.edu } 3707335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 3717335Sgblack@eecs.umich.edu index -= (32 / size); 3727335Sgblack@eecs.umich.edu vd++; 3737335Sgblack@eecs.umich.edu } 3747321Sgblack@eecs.umich.edu switch (size) { 3757321Sgblack@eecs.umich.edu case 8: 3767321Sgblack@eecs.umich.edu if (u) { 3777321Sgblack@eecs.umich.edu return new VmovRegCoreUB(machInst, rt, 3787321Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3797321Sgblack@eecs.umich.edu } else { 3807335Sgblack@eecs.umich.edu return new VmovRegCoreSB(machInst, rt, 3817335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3827335Sgblack@eecs.umich.edu } 3837335Sgblack@eecs.umich.edu case 16: 3847335Sgblack@eecs.umich.edu if (u) { 3857335Sgblack@eecs.umich.edu return new VmovRegCoreUH(machInst, rt, 3867335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3877335Sgblack@eecs.umich.edu } else { 3887335Sgblack@eecs.umich.edu return new VmovRegCoreSH(machInst, rt, 3897321Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3907326Sgblack@eecs.umich.edu } 3917326Sgblack@eecs.umich.edu case 32: 3927326Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 3937326Sgblack@eecs.umich.edu } 3947326Sgblack@eecs.umich.edu } 3957326Sgblack@eecs.umich.edu return new Unknown(machInst); 3967326Sgblack@eecs.umich.edu } 3977326Sgblack@eecs.umich.edu ''' 3987326Sgblack@eecs.umich.edu}}; 3997326Sgblack@eecs.umich.edu