fp.isa revision 7413
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 37178Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47178Sgblack@eecs.umich.edu// All rights reserved 57178Sgblack@eecs.umich.edu// 67178Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77178Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87178Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97178Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107178Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117178Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127178Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137178Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147178Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Floating Point operate instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 487356Sgblack@eecs.umich.edulet {{ 497356Sgblack@eecs.umich.edu header_output = ''' 507356Sgblack@eecs.umich.edu StaticInstPtr 517356Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst); 527356Sgblack@eecs.umich.edu ''' 537356Sgblack@eecs.umich.edu decoder_output = ''' 547356Sgblack@eecs.umich.edu StaticInstPtr 557356Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst) 567178Sgblack@eecs.umich.edu { 577178Sgblack@eecs.umich.edu const uint32_t opcode = bits(machInst, 24, 20); 587178Sgblack@eecs.umich.edu const uint32_t offset = bits(machInst, 7, 0); 597337Sgblack@eecs.umich.edu const bool single = (bits(machInst, 8) == 0); 607178Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 617178Sgblack@eecs.umich.edu RegIndex vd; 627178Sgblack@eecs.umich.edu if (single) { 637178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 647178Sgblack@eecs.umich.edu bits(machInst, 22)); 657178Sgblack@eecs.umich.edu } else { 667178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 677178Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 687178Sgblack@eecs.umich.edu } 697178Sgblack@eecs.umich.edu switch (bits(opcode, 4, 3)) { 707178Sgblack@eecs.umich.edu case 0x0: 717335Sgblack@eecs.umich.edu if (bits(opcode, 4, 1) == 0x2 && 727335Sgblack@eecs.umich.edu !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 737335Sgblack@eecs.umich.edu !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 747335Sgblack@eecs.umich.edu if ((bits(machInst, 7, 4) & 0xd) != 1) { 757335Sgblack@eecs.umich.edu break; 767335Sgblack@eecs.umich.edu } 777335Sgblack@eecs.umich.edu const IntRegIndex rt = 787335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 797335Sgblack@eecs.umich.edu const IntRegIndex rt2 = 807335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 817335Sgblack@eecs.umich.edu const bool op = bits(machInst, 20); 827335Sgblack@eecs.umich.edu uint32_t vm; 837337Sgblack@eecs.umich.edu if (single) { 847335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 857335Sgblack@eecs.umich.edu } else { 867335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | 877335Sgblack@eecs.umich.edu (bits(machInst, 5) << 5); 887335Sgblack@eecs.umich.edu } 897335Sgblack@eecs.umich.edu if (op) { 907335Sgblack@eecs.umich.edu return new Vmov2Core2Reg(machInst, rt, rt2, 917335Sgblack@eecs.umich.edu (IntRegIndex)vm); 927335Sgblack@eecs.umich.edu } else { 937335Sgblack@eecs.umich.edu return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 947335Sgblack@eecs.umich.edu rt, rt2); 957335Sgblack@eecs.umich.edu } 967178Sgblack@eecs.umich.edu } 977178Sgblack@eecs.umich.edu break; 987178Sgblack@eecs.umich.edu case 0x1: 997413Sgblack@eecs.umich.edu { 1007413Sgblack@eecs.umich.edu if (offset == 0 || vd + offset > NumFloatArchRegs) { 1017413Sgblack@eecs.umich.edu break; 1027413Sgblack@eecs.umich.edu } 1037413Sgblack@eecs.umich.edu switch (bits(opcode, 1, 0)) { 1047413Sgblack@eecs.umich.edu case 0x0: 1057413Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1067413Sgblack@eecs.umich.edu true, false, false, offset); 1077413Sgblack@eecs.umich.edu case 0x1: 1087413Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1097413Sgblack@eecs.umich.edu true, false, true, offset); 1107413Sgblack@eecs.umich.edu case 0x2: 1117413Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1127413Sgblack@eecs.umich.edu true, true, false, offset); 1137413Sgblack@eecs.umich.edu case 0x3: 1147413Sgblack@eecs.umich.edu // If rn == sp, then this is called vpop. 1157413Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1167413Sgblack@eecs.umich.edu true, true, true, offset); 1177413Sgblack@eecs.umich.edu } 1187178Sgblack@eecs.umich.edu } 1197178Sgblack@eecs.umich.edu case 0x2: 1207178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x2) { 1217178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpush. 1227178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1237178Sgblack@eecs.umich.edu false, true, false, offset); 1247178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x3) { 1257178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 1267178Sgblack@eecs.umich.edu false, true, true, offset); 1277178Sgblack@eecs.umich.edu } 1287178Sgblack@eecs.umich.edu // Fall through on purpose 1297178Sgblack@eecs.umich.edu case 0x3: 1307346Sgblack@eecs.umich.edu const bool up = (bits(machInst, 23) == 1); 1317346Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) << 2; 1327346Sgblack@eecs.umich.edu RegIndex vd; 1337346Sgblack@eecs.umich.edu if (single) { 1347346Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1357346Sgblack@eecs.umich.edu (bits(machInst, 22))); 1367346Sgblack@eecs.umich.edu } else { 1377346Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1387346Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 1397346Sgblack@eecs.umich.edu } 1407178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x0) { 1417346Sgblack@eecs.umich.edu if (single) { 1427346Sgblack@eecs.umich.edu if (up) { 1437346Sgblack@eecs.umich.edu return new %(vstr_us)s(machInst, vd, rn, up, imm); 1447346Sgblack@eecs.umich.edu } else { 1457346Sgblack@eecs.umich.edu return new %(vstr_s)s(machInst, vd, rn, up, imm); 1467346Sgblack@eecs.umich.edu } 1477346Sgblack@eecs.umich.edu } else { 1487346Sgblack@eecs.umich.edu if (up) { 1497346Sgblack@eecs.umich.edu return new %(vstr_ud)s(machInst, vd, vd + 1, 1507346Sgblack@eecs.umich.edu rn, up, imm); 1517346Sgblack@eecs.umich.edu } else { 1527346Sgblack@eecs.umich.edu return new %(vstr_d)s(machInst, vd, vd + 1, 1537346Sgblack@eecs.umich.edu rn, up, imm); 1547346Sgblack@eecs.umich.edu } 1557346Sgblack@eecs.umich.edu } 1567178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x1) { 1577337Sgblack@eecs.umich.edu if (single) { 1587337Sgblack@eecs.umich.edu if (up) { 1597337Sgblack@eecs.umich.edu return new %(vldr_us)s(machInst, vd, rn, up, imm); 1607337Sgblack@eecs.umich.edu } else { 1617337Sgblack@eecs.umich.edu return new %(vldr_s)s(machInst, vd, rn, up, imm); 1627337Sgblack@eecs.umich.edu } 1637337Sgblack@eecs.umich.edu } else { 1647337Sgblack@eecs.umich.edu if (up) { 1657337Sgblack@eecs.umich.edu return new %(vldr_ud)s(machInst, vd, vd + 1, 1667337Sgblack@eecs.umich.edu rn, up, imm); 1677337Sgblack@eecs.umich.edu } else { 1687337Sgblack@eecs.umich.edu return new %(vldr_d)s(machInst, vd, vd + 1, 1697337Sgblack@eecs.umich.edu rn, up, imm); 1707337Sgblack@eecs.umich.edu } 1717337Sgblack@eecs.umich.edu } 1727178Sgblack@eecs.umich.edu } 1737178Sgblack@eecs.umich.edu } 1747178Sgblack@eecs.umich.edu return new Unknown(machInst); 1757178Sgblack@eecs.umich.edu } 1767337Sgblack@eecs.umich.edu ''' % { 1777337Sgblack@eecs.umich.edu "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 1787337Sgblack@eecs.umich.edu "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 1797337Sgblack@eecs.umich.edu "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 1807346Sgblack@eecs.umich.edu "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 1817346Sgblack@eecs.umich.edu "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 1827346Sgblack@eecs.umich.edu "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 1837346Sgblack@eecs.umich.edu "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 1847346Sgblack@eecs.umich.edu "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 1857337Sgblack@eecs.umich.edu } 1867178Sgblack@eecs.umich.edu}}; 1877321Sgblack@eecs.umich.edu 1887356Sgblack@eecs.umich.edudef format ExtensionRegLoadStore() {{ 1897321Sgblack@eecs.umich.edu decode_block = ''' 1907356Sgblack@eecs.umich.edu return decodeExtensionRegLoadStore(machInst); 1917356Sgblack@eecs.umich.edu ''' 1927356Sgblack@eecs.umich.edu}}; 1937356Sgblack@eecs.umich.edu 1947356Sgblack@eecs.umich.edulet {{ 1957356Sgblack@eecs.umich.edu header_output = ''' 1967356Sgblack@eecs.umich.edu StaticInstPtr 1977356Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst); 1987356Sgblack@eecs.umich.edu ''' 1997356Sgblack@eecs.umich.edu decoder_output = ''' 2007356Sgblack@eecs.umich.edu StaticInstPtr 2017356Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst) 2027321Sgblack@eecs.umich.edu { 2037321Sgblack@eecs.umich.edu const uint32_t l = bits(machInst, 20); 2047321Sgblack@eecs.umich.edu const uint32_t c = bits(machInst, 8); 2057321Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 23, 21); 2067321Sgblack@eecs.umich.edu const uint32_t b = bits(machInst, 6, 5); 2077321Sgblack@eecs.umich.edu if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 2087321Sgblack@eecs.umich.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 2097321Sgblack@eecs.umich.edu return new Unknown(machInst); 2107321Sgblack@eecs.umich.edu } 2117321Sgblack@eecs.umich.edu if (l == 0 && c == 0) { 2127321Sgblack@eecs.umich.edu if (a == 0) { 2137335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 2147335Sgblack@eecs.umich.edu bits(machInst, 7); 2157335Sgblack@eecs.umich.edu const IntRegIndex rt = 2167335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2177335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 2187335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 2197335Sgblack@eecs.umich.edu } else { 2207335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 2217335Sgblack@eecs.umich.edu } 2227321Sgblack@eecs.umich.edu } else if (a == 0x7) { 2237323Sgblack@eecs.umich.edu const IntRegIndex rt = 2247323Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2257323Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 2267323Sgblack@eecs.umich.edu switch (specReg) { 2277323Sgblack@eecs.umich.edu case 0: 2287323Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 2297323Sgblack@eecs.umich.edu break; 2307323Sgblack@eecs.umich.edu case 1: 2317323Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 2327323Sgblack@eecs.umich.edu break; 2337394Sgblack@eecs.umich.edu case 6: 2347394Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 2357394Sgblack@eecs.umich.edu break; 2367394Sgblack@eecs.umich.edu case 7: 2377394Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 2387394Sgblack@eecs.umich.edu break; 2397323Sgblack@eecs.umich.edu case 8: 2407323Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 2417323Sgblack@eecs.umich.edu break; 2427323Sgblack@eecs.umich.edu default: 2437323Sgblack@eecs.umich.edu return new Unknown(machInst); 2447323Sgblack@eecs.umich.edu } 2457323Sgblack@eecs.umich.edu return new Vmsr(machInst, (IntRegIndex)specReg, rt); 2467321Sgblack@eecs.umich.edu } 2477321Sgblack@eecs.umich.edu } else if (l == 0 && c == 1) { 2487321Sgblack@eecs.umich.edu if (bits(a, 2) == 0) { 2497335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 2507335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 2517335Sgblack@eecs.umich.edu uint32_t index, size; 2527335Sgblack@eecs.umich.edu const IntRegIndex rt = 2537335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2547335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 2557335Sgblack@eecs.umich.edu size = 8; 2567335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 2577335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 2587335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 2597335Sgblack@eecs.umich.edu size = 16; 2607335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 2617335Sgblack@eecs.umich.edu bits(machInst, 6); 2627335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0) { 2637335Sgblack@eecs.umich.edu size = 32; 2647335Sgblack@eecs.umich.edu index = bits(machInst, 21); 2657335Sgblack@eecs.umich.edu } else { 2667335Sgblack@eecs.umich.edu return new Unknown(machInst); 2677335Sgblack@eecs.umich.edu } 2687335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 2697335Sgblack@eecs.umich.edu index -= (32 / size); 2707335Sgblack@eecs.umich.edu vd++; 2717335Sgblack@eecs.umich.edu } 2727335Sgblack@eecs.umich.edu switch (size) { 2737335Sgblack@eecs.umich.edu case 8: 2747335Sgblack@eecs.umich.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 2757335Sgblack@eecs.umich.edu rt, index); 2767335Sgblack@eecs.umich.edu case 16: 2777335Sgblack@eecs.umich.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 2787335Sgblack@eecs.umich.edu rt, index); 2797335Sgblack@eecs.umich.edu case 32: 2807335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 2817335Sgblack@eecs.umich.edu } 2827321Sgblack@eecs.umich.edu } else if (bits(b, 1) == 0) { 2837321Sgblack@eecs.umich.edu // A8-594 2847321Sgblack@eecs.umich.edu return new WarnUnimplemented("vdup", machInst); 2857321Sgblack@eecs.umich.edu } 2867321Sgblack@eecs.umich.edu } else if (l == 1 && c == 0) { 2877321Sgblack@eecs.umich.edu if (a == 0) { 2887335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 2897335Sgblack@eecs.umich.edu bits(machInst, 7); 2907335Sgblack@eecs.umich.edu const IntRegIndex rt = 2917335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2927335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 2937335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 2947335Sgblack@eecs.umich.edu } else { 2957335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 2967335Sgblack@eecs.umich.edu } 2977321Sgblack@eecs.umich.edu } else if (a == 7) { 2987326Sgblack@eecs.umich.edu const IntRegIndex rt = 2997326Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3007326Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3017326Sgblack@eecs.umich.edu switch (specReg) { 3027326Sgblack@eecs.umich.edu case 0: 3037326Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3047326Sgblack@eecs.umich.edu break; 3057326Sgblack@eecs.umich.edu case 1: 3067326Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3077326Sgblack@eecs.umich.edu break; 3087326Sgblack@eecs.umich.edu case 6: 3097326Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 3107326Sgblack@eecs.umich.edu break; 3117326Sgblack@eecs.umich.edu case 7: 3127326Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 3137326Sgblack@eecs.umich.edu break; 3147326Sgblack@eecs.umich.edu case 8: 3157326Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 3167326Sgblack@eecs.umich.edu break; 3177326Sgblack@eecs.umich.edu default: 3187326Sgblack@eecs.umich.edu return new Unknown(machInst); 3197326Sgblack@eecs.umich.edu } 3207392Sgblack@eecs.umich.edu if (rt == 0xf) { 3217392Sgblack@eecs.umich.edu CPSR cpsrMask = 0; 3227392Sgblack@eecs.umich.edu cpsrMask.n = 1; 3237392Sgblack@eecs.umich.edu cpsrMask.z = 1; 3247392Sgblack@eecs.umich.edu cpsrMask.c = 1; 3257392Sgblack@eecs.umich.edu cpsrMask.v = 1; 3267392Sgblack@eecs.umich.edu return new VmrsApsr(machInst, INTREG_CONDCODES, 3277392Sgblack@eecs.umich.edu (IntRegIndex)specReg, (uint32_t)cpsrMask); 3287392Sgblack@eecs.umich.edu } else { 3297392Sgblack@eecs.umich.edu return new Vmrs(machInst, rt, (IntRegIndex)specReg); 3307392Sgblack@eecs.umich.edu } 3317321Sgblack@eecs.umich.edu } 3327321Sgblack@eecs.umich.edu } else { 3337335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 3347335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 3357335Sgblack@eecs.umich.edu uint32_t index, size; 3367335Sgblack@eecs.umich.edu const IntRegIndex rt = 3377335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3387335Sgblack@eecs.umich.edu const bool u = (bits(machInst, 23) == 1); 3397335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 3407335Sgblack@eecs.umich.edu size = 8; 3417335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 3427335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 3437335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 3447335Sgblack@eecs.umich.edu size = 16; 3457335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 3467335Sgblack@eecs.umich.edu bits(machInst, 6); 3477335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0 && !u) { 3487335Sgblack@eecs.umich.edu size = 32; 3497335Sgblack@eecs.umich.edu index = bits(machInst, 21); 3507335Sgblack@eecs.umich.edu } else { 3517335Sgblack@eecs.umich.edu return new Unknown(machInst); 3527335Sgblack@eecs.umich.edu } 3537335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 3547335Sgblack@eecs.umich.edu index -= (32 / size); 3557335Sgblack@eecs.umich.edu vd++; 3567335Sgblack@eecs.umich.edu } 3577335Sgblack@eecs.umich.edu switch (size) { 3587335Sgblack@eecs.umich.edu case 8: 3597335Sgblack@eecs.umich.edu if (u) { 3607335Sgblack@eecs.umich.edu return new VmovRegCoreUB(machInst, rt, 3617335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3627335Sgblack@eecs.umich.edu } else { 3637335Sgblack@eecs.umich.edu return new VmovRegCoreSB(machInst, rt, 3647335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3657335Sgblack@eecs.umich.edu } 3667335Sgblack@eecs.umich.edu case 16: 3677335Sgblack@eecs.umich.edu if (u) { 3687335Sgblack@eecs.umich.edu return new VmovRegCoreUH(machInst, rt, 3697335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3707335Sgblack@eecs.umich.edu } else { 3717335Sgblack@eecs.umich.edu return new VmovRegCoreSH(machInst, rt, 3727335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 3737335Sgblack@eecs.umich.edu } 3747335Sgblack@eecs.umich.edu case 32: 3757335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 3767335Sgblack@eecs.umich.edu } 3777321Sgblack@eecs.umich.edu } 3787321Sgblack@eecs.umich.edu return new Unknown(machInst); 3797321Sgblack@eecs.umich.edu } 3807321Sgblack@eecs.umich.edu ''' 3817321Sgblack@eecs.umich.edu}}; 3827356Sgblack@eecs.umich.edu 3837356Sgblack@eecs.umich.edudef format ShortFpTransfer() {{ 3847356Sgblack@eecs.umich.edu decode_block = ''' 3857356Sgblack@eecs.umich.edu return decodeShortFpTransfer(machInst); 3867356Sgblack@eecs.umich.edu ''' 3877356Sgblack@eecs.umich.edu}}; 3887363Sgblack@eecs.umich.edu 3897363Sgblack@eecs.umich.edulet {{ 3907363Sgblack@eecs.umich.edu header_output = ''' 3917363Sgblack@eecs.umich.edu StaticInstPtr 3927363Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst); 3937363Sgblack@eecs.umich.edu ''' 3947363Sgblack@eecs.umich.edu decoder_output = ''' 3957363Sgblack@eecs.umich.edu StaticInstPtr 3967363Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst) 3977363Sgblack@eecs.umich.edu { 3987363Sgblack@eecs.umich.edu const uint32_t opc1 = bits(machInst, 23, 20); 3997363Sgblack@eecs.umich.edu const uint32_t opc2 = bits(machInst, 19, 16); 4007363Sgblack@eecs.umich.edu const uint32_t opc3 = bits(machInst, 7, 6); 4017363Sgblack@eecs.umich.edu //const uint32_t opc4 = bits(machInst, 3, 0); 4027372Sgblack@eecs.umich.edu const bool single = (bits(machInst, 8) == 0); 4037389Sgblack@eecs.umich.edu // Used to select between vcmp and vcmpe. 4047389Sgblack@eecs.umich.edu const bool e = (bits(machInst, 7) == 1); 4057372Sgblack@eecs.umich.edu IntRegIndex vd; 4067372Sgblack@eecs.umich.edu IntRegIndex vm; 4077372Sgblack@eecs.umich.edu IntRegIndex vn; 4087372Sgblack@eecs.umich.edu if (single) { 4097372Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 4107372Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 4117372Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 4127372Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 4137372Sgblack@eecs.umich.edu vn = (IntRegIndex)(bits(machInst, 7) | 4147372Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1)); 4157372Sgblack@eecs.umich.edu } else { 4167372Sgblack@eecs.umich.edu vd = (IntRegIndex)((bits(machInst, 22) << 5) | 4177372Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 4187372Sgblack@eecs.umich.edu vm = (IntRegIndex)((bits(machInst, 5) << 5) | 4197372Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 4207372Sgblack@eecs.umich.edu vn = (IntRegIndex)((bits(machInst, 7) << 5) | 4217372Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1)); 4227372Sgblack@eecs.umich.edu } 4237363Sgblack@eecs.umich.edu switch (opc1 & 0xb /* 1011 */) { 4247363Sgblack@eecs.umich.edu case 0x0: 4257370Sgblack@eecs.umich.edu if (bits(machInst, 6) == 0) { 4267372Sgblack@eecs.umich.edu if (single) { 4277376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlaS>( 4287376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4297370Sgblack@eecs.umich.edu } else { 4307376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlaD>( 4317376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4327370Sgblack@eecs.umich.edu } 4337370Sgblack@eecs.umich.edu } else { 4347372Sgblack@eecs.umich.edu if (single) { 4357376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlsS>( 4367376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4377370Sgblack@eecs.umich.edu } else { 4387376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlsD>( 4397376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4407370Sgblack@eecs.umich.edu } 4417370Sgblack@eecs.umich.edu } 4427371Sgblack@eecs.umich.edu case 0x1: 4437371Sgblack@eecs.umich.edu if (bits(machInst, 6) == 1) { 4447372Sgblack@eecs.umich.edu if (single) { 4457376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlaS>( 4467376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4477371Sgblack@eecs.umich.edu } else { 4487376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlaD>( 4497376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4507371Sgblack@eecs.umich.edu } 4517371Sgblack@eecs.umich.edu } else { 4527372Sgblack@eecs.umich.edu if (single) { 4537376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlsS>( 4547376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4557371Sgblack@eecs.umich.edu } else { 4567376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlsD>( 4577376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4587371Sgblack@eecs.umich.edu } 4597371Sgblack@eecs.umich.edu } 4607363Sgblack@eecs.umich.edu case 0x2: 4617363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 4627372Sgblack@eecs.umich.edu if (single) { 4637376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmulS>( 4647376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4657364Sgblack@eecs.umich.edu } else { 4667376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmulD>( 4677376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4687364Sgblack@eecs.umich.edu } 4697371Sgblack@eecs.umich.edu } else { 4707372Sgblack@eecs.umich.edu if (single) { 4717376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmulS>( 4727376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4737371Sgblack@eecs.umich.edu } else { 4747376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmulD>( 4757376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4767371Sgblack@eecs.umich.edu } 4777363Sgblack@eecs.umich.edu } 4787363Sgblack@eecs.umich.edu case 0x3: 4797363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 4807372Sgblack@eecs.umich.edu if (single) { 4817376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VaddS>( 4827376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4837367Sgblack@eecs.umich.edu } else { 4847376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VaddD>( 4857376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4867367Sgblack@eecs.umich.edu } 4877363Sgblack@eecs.umich.edu } else { 4887372Sgblack@eecs.umich.edu if (single) { 4897376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VsubS>( 4907376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 4917368Sgblack@eecs.umich.edu } else { 4927376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VsubD>( 4937376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 4947368Sgblack@eecs.umich.edu } 4957363Sgblack@eecs.umich.edu } 4967363Sgblack@eecs.umich.edu case 0x8: 4977363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 4987372Sgblack@eecs.umich.edu if (single) { 4997376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VdivS>( 5007376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5017369Sgblack@eecs.umich.edu } else { 5027376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VdivD>( 5037376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5047369Sgblack@eecs.umich.edu } 5057363Sgblack@eecs.umich.edu } 5067363Sgblack@eecs.umich.edu break; 5077363Sgblack@eecs.umich.edu case 0xb: 5087363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5097363Sgblack@eecs.umich.edu const uint32_t baseImm = 5107363Sgblack@eecs.umich.edu bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 5117372Sgblack@eecs.umich.edu if (single) { 5127363Sgblack@eecs.umich.edu uint32_t imm = vfp_modified_imm(baseImm, false); 5137376Sgblack@eecs.umich.edu return decodeVfpRegImmOp<VmovImmS>( 5147376Sgblack@eecs.umich.edu machInst, vd, imm, false); 5157363Sgblack@eecs.umich.edu } else { 5167363Sgblack@eecs.umich.edu uint64_t imm = vfp_modified_imm(baseImm, true); 5177376Sgblack@eecs.umich.edu return decodeVfpRegImmOp<VmovImmD>( 5187376Sgblack@eecs.umich.edu machInst, vd, imm, true); 5197363Sgblack@eecs.umich.edu } 5207363Sgblack@eecs.umich.edu } 5217363Sgblack@eecs.umich.edu switch (opc2) { 5227363Sgblack@eecs.umich.edu case 0x0: 5237363Sgblack@eecs.umich.edu if (opc3 == 1) { 5247372Sgblack@eecs.umich.edu if (single) { 5257376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VmovRegS>( 5267376Sgblack@eecs.umich.edu machInst, vd, vm, false); 5277363Sgblack@eecs.umich.edu } else { 5287376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VmovRegD>( 5297376Sgblack@eecs.umich.edu machInst, vd, vm, true); 5307363Sgblack@eecs.umich.edu } 5317363Sgblack@eecs.umich.edu } else { 5327372Sgblack@eecs.umich.edu if (single) { 5337376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VabsS>( 5347376Sgblack@eecs.umich.edu machInst, vd, vm, false); 5357366Sgblack@eecs.umich.edu } else { 5367376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VabsD>( 5377376Sgblack@eecs.umich.edu machInst, vd, vm, true); 5387366Sgblack@eecs.umich.edu } 5397363Sgblack@eecs.umich.edu } 5407363Sgblack@eecs.umich.edu case 0x1: 5417363Sgblack@eecs.umich.edu if (opc3 == 1) { 5427372Sgblack@eecs.umich.edu if (single) { 5437376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VnegS>( 5447376Sgblack@eecs.umich.edu machInst, vd, vm, false); 5457365Sgblack@eecs.umich.edu } else { 5467376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VnegD>( 5477376Sgblack@eecs.umich.edu machInst, vd, vm, true); 5487365Sgblack@eecs.umich.edu } 5497363Sgblack@eecs.umich.edu } else { 5507372Sgblack@eecs.umich.edu if (single) { 5517376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VsqrtS>( 5527376Sgblack@eecs.umich.edu machInst, vd, vm, false); 5537369Sgblack@eecs.umich.edu } else { 5547376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VsqrtD>( 5557376Sgblack@eecs.umich.edu machInst, vd, vm, true); 5567369Sgblack@eecs.umich.edu } 5577363Sgblack@eecs.umich.edu } 5587363Sgblack@eecs.umich.edu case 0x2: 5597363Sgblack@eecs.umich.edu case 0x3: 5607398Sgblack@eecs.umich.edu { 5617398Sgblack@eecs.umich.edu const bool toHalf = bits(machInst, 16); 5627398Sgblack@eecs.umich.edu const bool top = bits(machInst, 7); 5637398Sgblack@eecs.umich.edu if (top) { 5647398Sgblack@eecs.umich.edu if (toHalf) { 5657398Sgblack@eecs.umich.edu return new VcvtFpSFpHT(machInst, vd, vm); 5667398Sgblack@eecs.umich.edu } else { 5677398Sgblack@eecs.umich.edu return new VcvtFpHTFpS(machInst, vd, vm); 5687398Sgblack@eecs.umich.edu } 5697398Sgblack@eecs.umich.edu } else { 5707398Sgblack@eecs.umich.edu if (toHalf) { 5717398Sgblack@eecs.umich.edu return new VcvtFpSFpHB(machInst, vd, vm); 5727398Sgblack@eecs.umich.edu } else { 5737398Sgblack@eecs.umich.edu return new VcvtFpHBFpS(machInst, vd, vm); 5747398Sgblack@eecs.umich.edu } 5757398Sgblack@eecs.umich.edu } 5767398Sgblack@eecs.umich.edu } 5777363Sgblack@eecs.umich.edu case 0x4: 5787377Sgblack@eecs.umich.edu if (single) { 5797389Sgblack@eecs.umich.edu if (e) { 5807389Sgblack@eecs.umich.edu return new VcmpeS(machInst, vd, vm); 5817389Sgblack@eecs.umich.edu } else { 5827389Sgblack@eecs.umich.edu return new VcmpS(machInst, vd, vm); 5837389Sgblack@eecs.umich.edu } 5847377Sgblack@eecs.umich.edu } else { 5857389Sgblack@eecs.umich.edu if (e) { 5867389Sgblack@eecs.umich.edu return new VcmpeD(machInst, vd, vm); 5877389Sgblack@eecs.umich.edu } else { 5887389Sgblack@eecs.umich.edu return new VcmpD(machInst, vd, vm); 5897389Sgblack@eecs.umich.edu } 5907377Sgblack@eecs.umich.edu } 5917363Sgblack@eecs.umich.edu case 0x5: 5927377Sgblack@eecs.umich.edu if (single) { 5937389Sgblack@eecs.umich.edu if (e) { 5947389Sgblack@eecs.umich.edu return new VcmpeZeroS(machInst, vd, 0); 5957389Sgblack@eecs.umich.edu } else { 5967389Sgblack@eecs.umich.edu return new VcmpZeroS(machInst, vd, 0); 5977389Sgblack@eecs.umich.edu } 5987377Sgblack@eecs.umich.edu } else { 5997389Sgblack@eecs.umich.edu if (e) { 6007389Sgblack@eecs.umich.edu return new VcmpeZeroD(machInst, vd, 0); 6017389Sgblack@eecs.umich.edu } else { 6027389Sgblack@eecs.umich.edu return new VcmpZeroD(machInst, vd, 0); 6037389Sgblack@eecs.umich.edu } 6047377Sgblack@eecs.umich.edu } 6057363Sgblack@eecs.umich.edu case 0x7: 6067363Sgblack@eecs.umich.edu if (opc3 == 0x3) { 6077374Sgblack@eecs.umich.edu if (single) { 6087374Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 6097374Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 6107374Sgblack@eecs.umich.edu return new VcvtFpSFpD(machInst, vd, vm); 6117374Sgblack@eecs.umich.edu } else { 6127374Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 6137374Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 6147374Sgblack@eecs.umich.edu return new VcvtFpDFpS(machInst, vd, vm); 6157374Sgblack@eecs.umich.edu } 6167363Sgblack@eecs.umich.edu } 6177363Sgblack@eecs.umich.edu break; 6187363Sgblack@eecs.umich.edu case 0x8: 6197373Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 6207373Sgblack@eecs.umich.edu if (single) { 6217373Sgblack@eecs.umich.edu return new VcvtUIntFpS(machInst, vd, vm); 6227373Sgblack@eecs.umich.edu } else { 6237373Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 6247373Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 6257373Sgblack@eecs.umich.edu return new VcvtUIntFpD(machInst, vd, vm); 6267373Sgblack@eecs.umich.edu } 6277373Sgblack@eecs.umich.edu } else { 6287373Sgblack@eecs.umich.edu if (single) { 6297373Sgblack@eecs.umich.edu return new VcvtSIntFpS(machInst, vd, vm); 6307373Sgblack@eecs.umich.edu } else { 6317373Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 6327373Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 6337373Sgblack@eecs.umich.edu return new VcvtSIntFpD(machInst, vd, vm); 6347373Sgblack@eecs.umich.edu } 6357373Sgblack@eecs.umich.edu } 6367363Sgblack@eecs.umich.edu case 0xa: 6377379Sgblack@eecs.umich.edu { 6387379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 6397379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 6407379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 6417379Sgblack@eecs.umich.edu const uint32_t size = 6427379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 6437379Sgblack@eecs.umich.edu if (single) { 6447379Sgblack@eecs.umich.edu if (half) { 6457379Sgblack@eecs.umich.edu return new VcvtSHFixedFpS(machInst, vd, vd, size); 6467379Sgblack@eecs.umich.edu } else { 6477379Sgblack@eecs.umich.edu return new VcvtSFixedFpS(machInst, vd, vd, size); 6487379Sgblack@eecs.umich.edu } 6497379Sgblack@eecs.umich.edu } else { 6507379Sgblack@eecs.umich.edu if (half) { 6517379Sgblack@eecs.umich.edu return new VcvtSHFixedFpD(machInst, vd, vd, size); 6527379Sgblack@eecs.umich.edu } else { 6537379Sgblack@eecs.umich.edu return new VcvtSFixedFpD(machInst, vd, vd, size); 6547379Sgblack@eecs.umich.edu } 6557379Sgblack@eecs.umich.edu } 6567379Sgblack@eecs.umich.edu } 6577363Sgblack@eecs.umich.edu case 0xb: 6587379Sgblack@eecs.umich.edu { 6597379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 6607379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 6617379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 6627379Sgblack@eecs.umich.edu const uint32_t size = 6637379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 6647379Sgblack@eecs.umich.edu if (single) { 6657379Sgblack@eecs.umich.edu if (half) { 6667379Sgblack@eecs.umich.edu return new VcvtUHFixedFpS(machInst, vd, vd, size); 6677379Sgblack@eecs.umich.edu } else { 6687379Sgblack@eecs.umich.edu return new VcvtUFixedFpS(machInst, vd, vd, size); 6697379Sgblack@eecs.umich.edu } 6707379Sgblack@eecs.umich.edu } else { 6717379Sgblack@eecs.umich.edu if (half) { 6727379Sgblack@eecs.umich.edu return new VcvtUHFixedFpD(machInst, vd, vd, size); 6737379Sgblack@eecs.umich.edu } else { 6747379Sgblack@eecs.umich.edu return new VcvtUFixedFpD(machInst, vd, vd, size); 6757379Sgblack@eecs.umich.edu } 6767379Sgblack@eecs.umich.edu } 6777379Sgblack@eecs.umich.edu } 6787363Sgblack@eecs.umich.edu case 0xc: 6797380Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 6807380Sgblack@eecs.umich.edu if (single) { 6817380Sgblack@eecs.umich.edu return new VcvtFpUIntSR(machInst, vd, vm); 6827380Sgblack@eecs.umich.edu } else { 6837380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 6847380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 6857380Sgblack@eecs.umich.edu return new VcvtFpUIntDR(machInst, vd, vm); 6867380Sgblack@eecs.umich.edu } 6877373Sgblack@eecs.umich.edu } else { 6887380Sgblack@eecs.umich.edu if (single) { 6897380Sgblack@eecs.umich.edu return new VcvtFpUIntS(machInst, vd, vm); 6907380Sgblack@eecs.umich.edu } else { 6917380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 6927380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 6937380Sgblack@eecs.umich.edu return new VcvtFpUIntD(machInst, vd, vm); 6947380Sgblack@eecs.umich.edu } 6957373Sgblack@eecs.umich.edu } 6967363Sgblack@eecs.umich.edu case 0xd: 6977380Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 6987380Sgblack@eecs.umich.edu if (single) { 6997380Sgblack@eecs.umich.edu return new VcvtFpSIntSR(machInst, vd, vm); 7007380Sgblack@eecs.umich.edu } else { 7017380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 7027380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 7037380Sgblack@eecs.umich.edu return new VcvtFpSIntDR(machInst, vd, vm); 7047380Sgblack@eecs.umich.edu } 7057373Sgblack@eecs.umich.edu } else { 7067380Sgblack@eecs.umich.edu if (single) { 7077380Sgblack@eecs.umich.edu return new VcvtFpSIntS(machInst, vd, vm); 7087380Sgblack@eecs.umich.edu } else { 7097380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 7107380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 7117380Sgblack@eecs.umich.edu return new VcvtFpSIntD(machInst, vd, vm); 7127380Sgblack@eecs.umich.edu } 7137373Sgblack@eecs.umich.edu } 7147363Sgblack@eecs.umich.edu case 0xe: 7157379Sgblack@eecs.umich.edu { 7167379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 7177379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 7187379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 7197379Sgblack@eecs.umich.edu const uint32_t size = 7207379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 7217379Sgblack@eecs.umich.edu if (single) { 7227379Sgblack@eecs.umich.edu if (half) { 7237379Sgblack@eecs.umich.edu return new VcvtFpSHFixedS(machInst, vd, vd, size); 7247379Sgblack@eecs.umich.edu } else { 7257379Sgblack@eecs.umich.edu return new VcvtFpSFixedS(machInst, vd, vd, size); 7267379Sgblack@eecs.umich.edu } 7277379Sgblack@eecs.umich.edu } else { 7287379Sgblack@eecs.umich.edu if (half) { 7297379Sgblack@eecs.umich.edu return new VcvtFpSHFixedD(machInst, vd, vd, size); 7307379Sgblack@eecs.umich.edu } else { 7317379Sgblack@eecs.umich.edu return new VcvtFpSFixedD(machInst, vd, vd, size); 7327379Sgblack@eecs.umich.edu } 7337379Sgblack@eecs.umich.edu } 7347379Sgblack@eecs.umich.edu } 7357363Sgblack@eecs.umich.edu case 0xf: 7367379Sgblack@eecs.umich.edu { 7377379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 7387379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 7397379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 7407379Sgblack@eecs.umich.edu const uint32_t size = 7417379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 7427379Sgblack@eecs.umich.edu if (single) { 7437379Sgblack@eecs.umich.edu if (half) { 7447379Sgblack@eecs.umich.edu return new VcvtFpUHFixedS(machInst, vd, vd, size); 7457379Sgblack@eecs.umich.edu } else { 7467379Sgblack@eecs.umich.edu return new VcvtFpUFixedS(machInst, vd, vd, size); 7477379Sgblack@eecs.umich.edu } 7487379Sgblack@eecs.umich.edu } else { 7497379Sgblack@eecs.umich.edu if (half) { 7507379Sgblack@eecs.umich.edu return new VcvtFpUHFixedD(machInst, vd, vd, size); 7517379Sgblack@eecs.umich.edu } else { 7527379Sgblack@eecs.umich.edu return new VcvtFpUFixedD(machInst, vd, vd, size); 7537379Sgblack@eecs.umich.edu } 7547379Sgblack@eecs.umich.edu } 7557379Sgblack@eecs.umich.edu } 7567363Sgblack@eecs.umich.edu } 7577363Sgblack@eecs.umich.edu break; 7587363Sgblack@eecs.umich.edu } 7597363Sgblack@eecs.umich.edu return new Unknown(machInst); 7607363Sgblack@eecs.umich.edu } 7617363Sgblack@eecs.umich.edu ''' 7627363Sgblack@eecs.umich.edu}}; 7637363Sgblack@eecs.umich.edu 7647363Sgblack@eecs.umich.edudef format VfpData() {{ 7657363Sgblack@eecs.umich.edu decode_block = ''' 7667363Sgblack@eecs.umich.edu return decodeVfpData(machInst); 7677363Sgblack@eecs.umich.edu ''' 7687363Sgblack@eecs.umich.edu}}; 769