fp.isa revision 7398
16657Snate@binkert.org// -*- mode:c++ -*- 26657Snate@binkert.org 36657Snate@binkert.org// Copyright (c) 2010 ARM Limited 46657Snate@binkert.org// All rights reserved 56657Snate@binkert.org// 66657Snate@binkert.org// The license below extends only to copyright in the software and shall 76657Snate@binkert.org// not be construed as granting a license to any other intellectual 86657Snate@binkert.org// property including but not limited to intellectual property relating 96657Snate@binkert.org// to a hardware implementation of the functionality of the software 106657Snate@binkert.org// licensed hereunder. You may use the software subject to the license 116657Snate@binkert.org// terms below provided that you ensure that this notice is replicated 126657Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 136657Snate@binkert.org// modified or unmodified, in source code or in binary form. 146657Snate@binkert.org// 156657Snate@binkert.org// Copyright (c) 2007-2008 The Florida State University 166657Snate@binkert.org// All rights reserved. 176657Snate@binkert.org// 186657Snate@binkert.org// Redistribution and use in source and binary forms, with or without 196657Snate@binkert.org// modification, are permitted provided that the following conditions are 206657Snate@binkert.org// met: redistributions of source code must retain the above copyright 216657Snate@binkert.org// notice, this list of conditions and the following disclaimer; 226657Snate@binkert.org// redistributions in binary form must reproduce the above copyright 236657Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 246657Snate@binkert.org// documentation and/or other materials provided with the distribution; 256657Snate@binkert.org// neither the name of the copyright holders nor the names of its 266657Snate@binkert.org// contributors may be used to endorse or promote products derived from 276657Snate@binkert.org// this software without specific prior written permission. 286999Snate@binkert.org// 296657Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306657Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316657Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326657Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 338189SLisa.Hsu@amd.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346657Snate@binkert.org// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359499Snilay@cs.wisc.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369499Snilay@cs.wisc.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379364Snilay@cs.wisc.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387055Snate@binkert.org// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396882SBrad.Beckmann@amd.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406882SBrad.Beckmann@amd.com// 418191SLisa.Hsu@amd.com// Authors: Stephen Hines 426882SBrad.Beckmann@amd.com 436882SBrad.Beckmann@amd.com//////////////////////////////////////////////////////////////////// 449102SNuwan.Jayasena@amd.com// 459366Snilay@cs.wisc.edu// Floating Point operate instructions 469499Snilay@cs.wisc.edu// 479499Snilay@cs.wisc.edu 489499Snilay@cs.wisc.edudef template FPAExecute {{ 496882SBrad.Beckmann@amd.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 506657Snate@binkert.org { 516657Snate@binkert.org Fault fault = NoFault; 526657Snate@binkert.org 536657Snate@binkert.org %(fp_enable_check)s; 546657Snate@binkert.org 559366Snilay@cs.wisc.edu %(op_decl)s; 567839Snilay@cs.wisc.edu %(op_rd)s; 576657Snate@binkert.org 586882SBrad.Beckmann@amd.com if (%(predicate_test)s) { 596882SBrad.Beckmann@amd.com %(code)s; 606882SBrad.Beckmann@amd.com if (fault == NoFault) { 616882SBrad.Beckmann@amd.com %(op_wb)s; 626882SBrad.Beckmann@amd.com } 636882SBrad.Beckmann@amd.com } 646657Snate@binkert.org 659366Snilay@cs.wisc.edu return fault; 669366Snilay@cs.wisc.edu } 676657Snate@binkert.org}}; 686657Snate@binkert.org 696657Snate@binkert.orgdef template FloatDoubleDecode {{ 706657Snate@binkert.org { 719104Shestness@cs.utexas.edu ArmStaticInst *i = NULL; 726657Snate@binkert.org switch (OPCODE_19 << 1 | OPCODE_7) 736657Snate@binkert.org { 746657Snate@binkert.org case 0: 756657Snate@binkert.org i = (ArmStaticInst *)new %(class_name)sS(machInst); 767839Snilay@cs.wisc.edu break; 777839Snilay@cs.wisc.edu case 1: 786657Snate@binkert.org i = (ArmStaticInst *)new %(class_name)sD(machInst); 796657Snate@binkert.org break; 806657Snate@binkert.org case 2: 816657Snate@binkert.org case 3: 826657Snate@binkert.org default: 836657Snate@binkert.org panic("Cannot decode float/double nature of the instruction"); 846657Snate@binkert.org } 856657Snate@binkert.org return i; 866657Snate@binkert.org } 876657Snate@binkert.org}}; 886657Snate@binkert.org 896657Snate@binkert.org// Primary format for float point operate instructions: 906657Snate@binkert.orgdef format FloatOp(code, *flags) {{ 916657Snate@binkert.org orig_code = code 926657Snate@binkert.org 936657Snate@binkert.org cblk = code 946657Snate@binkert.org iop = InstObjParams(name, Name, 'PredOp', 956657Snate@binkert.org {"code": cblk, 966779SBrad.Beckmann@amd.com "predicate_test": predicateTest}, 976657Snate@binkert.org flags) 986657Snate@binkert.org header_output = BasicDeclare.subst(iop) 996657Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 1006657Snate@binkert.org exec_output = FPAExecute.subst(iop) 1016657Snate@binkert.org 1026657Snate@binkert.org sng_cblk = code 1036657Snate@binkert.org sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1046657Snate@binkert.org {"code": sng_cblk, 1056657Snate@binkert.org "predicate_test": predicateTest}, 1069104Shestness@cs.utexas.edu flags) 1079104Shestness@cs.utexas.edu header_output += BasicDeclare.subst(sng_iop) 1089104Shestness@cs.utexas.edu decoder_output += BasicConstructor.subst(sng_iop) 1099104Shestness@cs.utexas.edu exec_output += FPAExecute.subst(sng_iop) 1106657Snate@binkert.org 1116657Snate@binkert.org dbl_code = re.sub(r'\.sf', '.df', orig_code) 1126657Snate@binkert.org 1136657Snate@binkert.org dbl_cblk = dbl_code 1146657Snate@binkert.org dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1156657Snate@binkert.org {"code": dbl_cblk, 1166657Snate@binkert.org "predicate_test": predicateTest}, 1176657Snate@binkert.org flags) 1186657Snate@binkert.org header_output += BasicDeclare.subst(dbl_iop) 1196657Snate@binkert.org decoder_output += BasicConstructor.subst(dbl_iop) 1206657Snate@binkert.org exec_output += FPAExecute.subst(dbl_iop) 1216657Snate@binkert.org 1226657Snate@binkert.org decode_block = FloatDoubleDecode.subst(iop) 1236657Snate@binkert.org}}; 1246657Snate@binkert.org 1257839Snilay@cs.wisc.edulet {{ 1267839Snilay@cs.wisc.edu calcFPCcCode = ''' 1277839Snilay@cs.wisc.edu uint16_t _in, _iz, _ic, _iv; 1287839Snilay@cs.wisc.edu 1297839Snilay@cs.wisc.edu _in = %(fReg1)s < %(fReg2)s; 1307839Snilay@cs.wisc.edu _iz = %(fReg1)s == %(fReg2)s; 1317839Snilay@cs.wisc.edu _ic = %(fReg1)s >= %(fReg2)s; 1327839Snilay@cs.wisc.edu _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 1337839Snilay@cs.wisc.edu 1347839Snilay@cs.wisc.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 1357839Snilay@cs.wisc.edu (CondCodes & 0x0FFFFFFF); 1367839Snilay@cs.wisc.edu ''' 1377839Snilay@cs.wisc.edu}}; 1387839Snilay@cs.wisc.edu 1397839Snilay@cs.wisc.edudef format FloatCmp(fReg1, fReg2, *flags) {{ 1406657Snate@binkert.org code = calcFPCcCode % vars() 1416657Snate@binkert.org iop = InstObjParams(name, Name, 'PredOp', 1426657Snate@binkert.org {"code": code, 1436657Snate@binkert.org "predicate_test": predicateTest}, 1446657Snate@binkert.org flags) 1456657Snate@binkert.org header_output = BasicDeclare.subst(iop) 1466657Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 1476657Snate@binkert.org decode_block = BasicDecode.subst(iop) 1486657Snate@binkert.org exec_output = FPAExecute.subst(iop) 1496657Snate@binkert.org}}; 1506657Snate@binkert.org 1516657Snate@binkert.orglet {{ 1526657Snate@binkert.org header_output = ''' 1536657Snate@binkert.org StaticInstPtr 1546657Snate@binkert.org decodeExtensionRegLoadStore(ExtMachInst machInst); 1556657Snate@binkert.org ''' 1566657Snate@binkert.org decoder_output = ''' 1576657Snate@binkert.org StaticInstPtr 1586657Snate@binkert.org decodeExtensionRegLoadStore(ExtMachInst machInst) 1596657Snate@binkert.org { 1606657Snate@binkert.org const uint32_t opcode = bits(machInst, 24, 20); 1616657Snate@binkert.org const uint32_t offset = bits(machInst, 7, 0); 1626657Snate@binkert.org const bool single = (bits(machInst, 8) == 0); 1636657Snate@binkert.org const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1646657Snate@binkert.org RegIndex vd; 1656657Snate@binkert.org if (single) { 1666657Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1676657Snate@binkert.org bits(machInst, 22)); 1686657Snate@binkert.org } else { 1696657Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1709219Spower.jg@gmail.com (bits(machInst, 22) << 5)); 1716877Ssteve.reinhardt@amd.com } 1726657Snate@binkert.org switch (bits(opcode, 4, 3)) { 1739219Spower.jg@gmail.com case 0x0: 1746657Snate@binkert.org if (bits(opcode, 4, 1) == 0x2 && 1759219Spower.jg@gmail.com !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 1766657Snate@binkert.org !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 1776877Ssteve.reinhardt@amd.com if ((bits(machInst, 7, 4) & 0xd) != 1) { 1786999Snate@binkert.org break; 1796877Ssteve.reinhardt@amd.com } 1806877Ssteve.reinhardt@amd.com const IntRegIndex rt = 1816877Ssteve.reinhardt@amd.com (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1826877Ssteve.reinhardt@amd.com const IntRegIndex rt2 = 1836877Ssteve.reinhardt@amd.com (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1846877Ssteve.reinhardt@amd.com const bool op = bits(machInst, 20); 1856877Ssteve.reinhardt@amd.com uint32_t vm; 1866877Ssteve.reinhardt@amd.com if (single) { 1876877Ssteve.reinhardt@amd.com vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 1886877Ssteve.reinhardt@amd.com } else { 1899338SAndreas.Sandberg@arm.com vm = (bits(machInst, 3, 0) << 1) | 1906877Ssteve.reinhardt@amd.com (bits(machInst, 5) << 5); 1916877Ssteve.reinhardt@amd.com } 1926877Ssteve.reinhardt@amd.com if (op) { 1936877Ssteve.reinhardt@amd.com return new Vmov2Core2Reg(machInst, rt, rt2, 1946877Ssteve.reinhardt@amd.com (IntRegIndex)vm); 1956877Ssteve.reinhardt@amd.com } else { 1966882SBrad.Beckmann@amd.com return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 1976882SBrad.Beckmann@amd.com rt, rt2); 1986882SBrad.Beckmann@amd.com } 1996882SBrad.Beckmann@amd.com } 2006882SBrad.Beckmann@amd.com break; 2016882SBrad.Beckmann@amd.com case 0x1: 2026882SBrad.Beckmann@amd.com switch (bits(opcode, 1, 0)) { 2036877Ssteve.reinhardt@amd.com case 0x0: 2046877Ssteve.reinhardt@amd.com return new VLdmStm(machInst, rn, vd, single, 2056877Ssteve.reinhardt@amd.com true, false, false, offset); 2066877Ssteve.reinhardt@amd.com case 0x1: 2076657Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2086657Snate@binkert.org true, false, true, offset); 2096999Snate@binkert.org case 0x2: 2106657Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2116657Snate@binkert.org true, true, false, offset); 2126657Snate@binkert.org case 0x3: 2136657Snate@binkert.org // If rn == sp, then this is called vpop. 2147007Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2156657Snate@binkert.org true, true, true, offset); 2166657Snate@binkert.org } 2176657Snate@binkert.org case 0x2: 2186657Snate@binkert.org if (bits(opcode, 1, 0) == 0x2) { 2196657Snate@binkert.org // If rn == sp, then this is called vpush. 2207007Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2217007Snate@binkert.org false, true, false, offset); 2226657Snate@binkert.org } else if (bits(opcode, 1, 0) == 0x3) { 2237002Snate@binkert.org return new VLdmStm(machInst, rn, vd, single, 2247002Snate@binkert.org false, true, true, offset); 2257002Snate@binkert.org } 2267002Snate@binkert.org // Fall through on purpose 2276657Snate@binkert.org case 0x3: 2286657Snate@binkert.org const bool up = (bits(machInst, 23) == 1); 2298229Snate@binkert.org const uint32_t imm = bits(machInst, 7, 0) << 2; 2308229Snate@binkert.org RegIndex vd; 2318229Snate@binkert.org if (single) { 2328229Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2336657Snate@binkert.org (bits(machInst, 22))); 2346657Snate@binkert.org } else { 2356657Snate@binkert.org vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2369595Snilay@cs.wisc.edu (bits(machInst, 22) << 5)); 2376657Snate@binkert.org } 2386793SBrad.Beckmann@amd.com if (bits(opcode, 1, 0) == 0x0) { 2396657Snate@binkert.org if (single) { 2409595Snilay@cs.wisc.edu if (up) { 2419595Snilay@cs.wisc.edu return new %(vstr_us)s(machInst, vd, rn, up, imm); 2426657Snate@binkert.org } else { 2436657Snate@binkert.org return new %(vstr_s)s(machInst, vd, rn, up, imm); 2446657Snate@binkert.org } 2456657Snate@binkert.org } else { 2467002Snate@binkert.org if (up) { 2476657Snate@binkert.org return new %(vstr_ud)s(machInst, vd, vd + 1, 2487007Snate@binkert.org rn, up, imm); 2497007Snate@binkert.org } else { 2509271Snilay@cs.wisc.edu return new %(vstr_d)s(machInst, vd, vd + 1, 2516877Ssteve.reinhardt@amd.com rn, up, imm); 2526877Ssteve.reinhardt@amd.com } 2536657Snate@binkert.org } 2546877Ssteve.reinhardt@amd.com } else if (bits(opcode, 1, 0) == 0x1) { 2556657Snate@binkert.org if (single) { 2567002Snate@binkert.org if (up) { 2579745Snilay@cs.wisc.edu return new %(vldr_us)s(machInst, vd, rn, up, imm); 2587002Snate@binkert.org } else { 2596657Snate@binkert.org return new %(vldr_s)s(machInst, vd, rn, up, imm); 26010012Snilay@cs.wisc.edu } 2619745Snilay@cs.wisc.edu } else { 2629745Snilay@cs.wisc.edu if (up) { 2639745Snilay@cs.wisc.edu return new %(vldr_ud)s(machInst, vd, vd + 1, 2648683Snilay@cs.wisc.edu rn, up, imm); 2658683Snilay@cs.wisc.edu } else { 2667007Snate@binkert.org return new %(vldr_d)s(machInst, vd, vd + 1, 2679302Snilay@cs.wisc.edu rn, up, imm); 2689302Snilay@cs.wisc.edu } 2699302Snilay@cs.wisc.edu } 2709745Snilay@cs.wisc.edu } 2719745Snilay@cs.wisc.edu } 2729745Snilay@cs.wisc.edu return new Unknown(machInst); 2739745Snilay@cs.wisc.edu } 2749745Snilay@cs.wisc.edu ''' % { 2759745Snilay@cs.wisc.edu "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 2766657Snate@binkert.org "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 2776657Snate@binkert.org "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 2786657Snate@binkert.org "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 2796657Snate@binkert.org "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 2806657Snate@binkert.org "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 2816657Snate@binkert.org "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 2826882SBrad.Beckmann@amd.com "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 2836882SBrad.Beckmann@amd.com } 2846882SBrad.Beckmann@amd.com}}; 2856882SBrad.Beckmann@amd.com 2866657Snate@binkert.orgdef format ExtensionRegLoadStore() {{ 2876657Snate@binkert.org decode_block = ''' 2887007Snate@binkert.org return decodeExtensionRegLoadStore(machInst); 2897839Snilay@cs.wisc.edu ''' 2907839Snilay@cs.wisc.edu}}; 2917839Snilay@cs.wisc.edu 2927839Snilay@cs.wisc.edulet {{ 2937839Snilay@cs.wisc.edu header_output = ''' 2947839Snilay@cs.wisc.edu StaticInstPtr 2957839Snilay@cs.wisc.edu decodeShortFpTransfer(ExtMachInst machInst); 2967839Snilay@cs.wisc.edu ''' 2977839Snilay@cs.wisc.edu decoder_output = ''' 2987839Snilay@cs.wisc.edu StaticInstPtr 2997839Snilay@cs.wisc.edu decodeShortFpTransfer(ExtMachInst machInst) 3007839Snilay@cs.wisc.edu { 30110010Snilay@cs.wisc.edu const uint32_t l = bits(machInst, 20); 3027007Snate@binkert.org const uint32_t c = bits(machInst, 8); 3037007Snate@binkert.org const uint32_t a = bits(machInst, 23, 21); 3047007Snate@binkert.org const uint32_t b = bits(machInst, 6, 5); 3057007Snate@binkert.org if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 3067839Snilay@cs.wisc.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 3077839Snilay@cs.wisc.edu return new Unknown(machInst); 3087839Snilay@cs.wisc.edu } 3097839Snilay@cs.wisc.edu if (l == 0 && c == 0) { 3107839Snilay@cs.wisc.edu if (a == 0) { 3117839Snilay@cs.wisc.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3127839Snilay@cs.wisc.edu bits(machInst, 7); 3137839Snilay@cs.wisc.edu const IntRegIndex rt = 3147839Snilay@cs.wisc.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3157839Snilay@cs.wisc.edu if (bits(machInst, 20) == 1) { 3167839Snilay@cs.wisc.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3177839Snilay@cs.wisc.edu } else { 3187007Snate@binkert.org return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3197007Snate@binkert.org } 3209745Snilay@cs.wisc.edu } else if (a == 0x7) { 3219745Snilay@cs.wisc.edu const IntRegIndex rt = 3229745Snilay@cs.wisc.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3239745Snilay@cs.wisc.edu uint32_t specReg = bits(machInst, 19, 16); 3249745Snilay@cs.wisc.edu switch (specReg) { 3259745Snilay@cs.wisc.edu case 0: 3266657Snate@binkert.org specReg = MISCREG_FPSID; 3277007Snate@binkert.org break; 3286657Snate@binkert.org case 1: 3296657Snate@binkert.org specReg = MISCREG_FPSCR; 3306657Snate@binkert.org break; 3316657Snate@binkert.org case 6: 3326657Snate@binkert.org specReg = MISCREG_MVFR1; 3336657Snate@binkert.org break; 3346657Snate@binkert.org case 7: 3356657Snate@binkert.org specReg = MISCREG_MVFR0; 3369595Snilay@cs.wisc.edu break; 3379595Snilay@cs.wisc.edu case 8: 3387839Snilay@cs.wisc.edu specReg = MISCREG_FPEXC; 3397839Snilay@cs.wisc.edu break; 3407839Snilay@cs.wisc.edu default: 3417839Snilay@cs.wisc.edu return new Unknown(machInst); 3427839Snilay@cs.wisc.edu } 3437839Snilay@cs.wisc.edu return new Vmsr(machInst, (IntRegIndex)specReg, rt); 3447839Snilay@cs.wisc.edu } 3457839Snilay@cs.wisc.edu } else if (l == 0 && c == 1) { 3467839Snilay@cs.wisc.edu if (bits(a, 2) == 0) { 3477839Snilay@cs.wisc.edu uint32_t vd = (bits(machInst, 7) << 5) | 3487839Snilay@cs.wisc.edu (bits(machInst, 19, 16) << 1); 3497839Snilay@cs.wisc.edu uint32_t index, size; 3507839Snilay@cs.wisc.edu const IntRegIndex rt = 3517839Snilay@cs.wisc.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3527839Snilay@cs.wisc.edu if (bits(machInst, 22) == 1) { 3537839Snilay@cs.wisc.edu size = 8; 35410121Snilay@cs.wisc.edu index = (bits(machInst, 21) << 2) | 3556657Snate@binkert.org bits(machInst, 6, 5); 3566657Snate@binkert.org } else if (bits(machInst, 5) == 1) { 3576657Snate@binkert.org size = 16; 3586657Snate@binkert.org index = (bits(machInst, 21) << 1) | 3597839Snilay@cs.wisc.edu bits(machInst, 6); 3607839Snilay@cs.wisc.edu } else if (bits(machInst, 6) == 0) { 3617839Snilay@cs.wisc.edu size = 32; 36210121Snilay@cs.wisc.edu index = bits(machInst, 21); 36310121Snilay@cs.wisc.edu } else { 36410121Snilay@cs.wisc.edu return new Unknown(machInst); 3657839Snilay@cs.wisc.edu } 3667839Snilay@cs.wisc.edu if (index >= (32 / size)) { 3677839Snilay@cs.wisc.edu index -= (32 / size); 36810121Snilay@cs.wisc.edu vd++; 36910121Snilay@cs.wisc.edu } 3707839Snilay@cs.wisc.edu switch (size) { 3717839Snilay@cs.wisc.edu case 8: 3727839Snilay@cs.wisc.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 37310121Snilay@cs.wisc.edu rt, index); 37410121Snilay@cs.wisc.edu case 16: 3757839Snilay@cs.wisc.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 3767839Snilay@cs.wisc.edu rt, index); 3777839Snilay@cs.wisc.edu case 32: 3787839Snilay@cs.wisc.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 3796657Snate@binkert.org } 3806657Snate@binkert.org } else if (bits(b, 1) == 0) { 3816657Snate@binkert.org // A8-594 3826657Snate@binkert.org return new WarnUnimplemented("vdup", machInst); 3837007Snate@binkert.org } 3846657Snate@binkert.org } else if (l == 1 && c == 0) { 3856657Snate@binkert.org if (a == 0) { 3869273Snilay@cs.wisc.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3876657Snate@binkert.org bits(machInst, 7); 3886657Snate@binkert.org const IntRegIndex rt = 3896657Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3906657Snate@binkert.org if (bits(machInst, 20) == 1) { 3917007Snate@binkert.org return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3926657Snate@binkert.org } else { 3936657Snate@binkert.org return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3949219Spower.jg@gmail.com } 3956657Snate@binkert.org } else if (a == 7) { 3966657Snate@binkert.org const IntRegIndex rt = 3976999Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3986657Snate@binkert.org uint32_t specReg = bits(machInst, 19, 16); 3996657Snate@binkert.org switch (specReg) { 4009595Snilay@cs.wisc.edu case 0: 4016657Snate@binkert.org specReg = MISCREG_FPSID; 4026657Snate@binkert.org break; 4037007Snate@binkert.org case 1: 4046657Snate@binkert.org specReg = MISCREG_FPSCR; 4056657Snate@binkert.org break; 4066657Snate@binkert.org case 6: 4076657Snate@binkert.org specReg = MISCREG_MVFR1; 4086657Snate@binkert.org break; 4098946Sandreas.hansson@arm.com case 7: 4108946Sandreas.hansson@arm.com specReg = MISCREG_MVFR0; 4118946Sandreas.hansson@arm.com break; 4127832Snate@binkert.org case 8: 4137002Snate@binkert.org specReg = MISCREG_FPEXC; 4147002Snate@binkert.org break; 4157002Snate@binkert.org default: 4168641Snate@binkert.org return new Unknown(machInst); 4177056Snate@binkert.org } 4188232Snate@binkert.org if (rt == 0xf) { 4198232Snate@binkert.org CPSR cpsrMask = 0; 4206657Snate@binkert.org cpsrMask.n = 1; 4218229Snate@binkert.org cpsrMask.z = 1; 4226657Snate@binkert.org cpsrMask.c = 1; 4236657Snate@binkert.org cpsrMask.v = 1; 4247056Snate@binkert.org return new VmrsApsr(machInst, INTREG_CONDCODES, 4256657Snate@binkert.org (IntRegIndex)specReg, (uint32_t)cpsrMask); 4269219Spower.jg@gmail.com } else { 4279219Spower.jg@gmail.com return new Vmrs(machInst, rt, (IntRegIndex)specReg); 4289219Spower.jg@gmail.com } 4299219Spower.jg@gmail.com } 4309219Spower.jg@gmail.com } else { 4317002Snate@binkert.org uint32_t vd = (bits(machInst, 7) << 5) | 4327002Snate@binkert.org (bits(machInst, 19, 16) << 1); 4336657Snate@binkert.org uint32_t index, size; 4346657Snate@binkert.org const IntRegIndex rt = 4356657Snate@binkert.org (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 4366657Snate@binkert.org const bool u = (bits(machInst, 23) == 1); 4376657Snate@binkert.org if (bits(machInst, 22) == 1) { 4386793SBrad.Beckmann@amd.com size = 8; 4396657Snate@binkert.org index = (bits(machInst, 21) << 2) | 4406657Snate@binkert.org bits(machInst, 6, 5); 4416657Snate@binkert.org } else if (bits(machInst, 5) == 1) { 44210121Snilay@cs.wisc.edu size = 16; 44310121Snilay@cs.wisc.edu index = (bits(machInst, 21) << 1) | 4446657Snate@binkert.org bits(machInst, 6); 4456877Ssteve.reinhardt@amd.com } else if (bits(machInst, 6) == 0 && !u) { 4466877Ssteve.reinhardt@amd.com size = 32; 4476877Ssteve.reinhardt@amd.com index = bits(machInst, 21); 4486877Ssteve.reinhardt@amd.com } else { 4496877Ssteve.reinhardt@amd.com return new Unknown(machInst); 4506877Ssteve.reinhardt@amd.com } 4516657Snate@binkert.org if (index >= (32 / size)) { 4529745Snilay@cs.wisc.edu index -= (32 / size); 4539745Snilay@cs.wisc.edu vd++; 4546657Snate@binkert.org } 4557007Snate@binkert.org switch (size) { 4566657Snate@binkert.org case 8: 4579801Snilay@cs.wisc.edu if (u) { 4589801Snilay@cs.wisc.edu return new VmovRegCoreUB(machInst, rt, 4596657Snate@binkert.org (IntRegIndex)vd, index); 4609801Snilay@cs.wisc.edu } else { 4619801Snilay@cs.wisc.edu return new VmovRegCoreSB(machInst, rt, 4629801Snilay@cs.wisc.edu (IntRegIndex)vd, index); 4637007Snate@binkert.org } 4646657Snate@binkert.org case 16: 4656877Ssteve.reinhardt@amd.com if (u) { 4666877Ssteve.reinhardt@amd.com return new VmovRegCoreUH(machInst, rt, 4676657Snate@binkert.org (IntRegIndex)vd, index); 46810078Snilay@cs.wisc.edu } else { 46910078Snilay@cs.wisc.edu return new VmovRegCoreSH(machInst, rt, 47010121Snilay@cs.wisc.edu (IntRegIndex)vd, index); 47110121Snilay@cs.wisc.edu } 47210121Snilay@cs.wisc.edu case 32: 4736657Snate@binkert.org return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 4746657Snate@binkert.org } 4756882SBrad.Beckmann@amd.com } 4766882SBrad.Beckmann@amd.com return new Unknown(machInst); 4776882SBrad.Beckmann@amd.com } 47810121Snilay@cs.wisc.edu ''' 47910121Snilay@cs.wisc.edu}}; 4806882SBrad.Beckmann@amd.com 4816877Ssteve.reinhardt@amd.comdef format ShortFpTransfer() {{ 4826882SBrad.Beckmann@amd.com decode_block = ''' 4836882SBrad.Beckmann@amd.com return decodeShortFpTransfer(machInst); 4846882SBrad.Beckmann@amd.com ''' 4856882SBrad.Beckmann@amd.com}}; 48610121Snilay@cs.wisc.edu 48710121Snilay@cs.wisc.edulet {{ 4886888SBrad.Beckmann@amd.com header_output = ''' 4896657Snate@binkert.org StaticInstPtr 4906657Snate@binkert.org decodeVfpData(ExtMachInst machInst); 4919508Snilay@cs.wisc.edu ''' 4929508Snilay@cs.wisc.edu decoder_output = ''' 4939508Snilay@cs.wisc.edu StaticInstPtr 4949508Snilay@cs.wisc.edu decodeVfpData(ExtMachInst machInst) 4959595Snilay@cs.wisc.edu { 4969595Snilay@cs.wisc.edu const uint32_t opc1 = bits(machInst, 23, 20); 4979595Snilay@cs.wisc.edu const uint32_t opc2 = bits(machInst, 19, 16); 4989595Snilay@cs.wisc.edu const uint32_t opc3 = bits(machInst, 7, 6); 4999595Snilay@cs.wisc.edu //const uint32_t opc4 = bits(machInst, 3, 0); 5009595Snilay@cs.wisc.edu const bool single = (bits(machInst, 8) == 0); 5019595Snilay@cs.wisc.edu // Used to select between vcmp and vcmpe. 5029595Snilay@cs.wisc.edu const bool e = (bits(machInst, 7) == 1); 5039595Snilay@cs.wisc.edu IntRegIndex vd; 5046657Snate@binkert.org IntRegIndex vm; 5059595Snilay@cs.wisc.edu IntRegIndex vn; 5069595Snilay@cs.wisc.edu if (single) { 5079595Snilay@cs.wisc.edu vd = (IntRegIndex)(bits(machInst, 22) | 5089745Snilay@cs.wisc.edu (bits(machInst, 15, 12) << 1)); 5099745Snilay@cs.wisc.edu vm = (IntRegIndex)(bits(machInst, 5) | 5109745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1)); 5119745Snilay@cs.wisc.edu vn = (IntRegIndex)(bits(machInst, 7) | 5129745Snilay@cs.wisc.edu (bits(machInst, 19, 16) << 1)); 5139745Snilay@cs.wisc.edu } else { 5149745Snilay@cs.wisc.edu vd = (IntRegIndex)((bits(machInst, 22) << 5) | 5159745Snilay@cs.wisc.edu (bits(machInst, 15, 12) << 1)); 5169745Snilay@cs.wisc.edu vm = (IntRegIndex)((bits(machInst, 5) << 5) | 5179745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1)); 5189595Snilay@cs.wisc.edu vn = (IntRegIndex)((bits(machInst, 7) << 5) | 5196657Snate@binkert.org (bits(machInst, 19, 16) << 1)); 5206657Snate@binkert.org } 5216657Snate@binkert.org switch (opc1 & 0xb /* 1011 */) { 5226657Snate@binkert.org case 0x0: 5237007Snate@binkert.org if (bits(machInst, 6) == 0) { 5247007Snate@binkert.org if (single) { 5256657Snate@binkert.org return decodeVfpRegRegRegOp<VmlaS>( 5269745Snilay@cs.wisc.edu machInst, vd, vn, vm, false); 52710008Snilay@cs.wisc.edu } else { 5287007Snate@binkert.org return decodeVfpRegRegRegOp<VmlaD>( 5297007Snate@binkert.org machInst, vd, vn, vm, true); 5307007Snate@binkert.org } 5316657Snate@binkert.org } else { 5326657Snate@binkert.org if (single) { 5336657Snate@binkert.org return decodeVfpRegRegRegOp<VmlsS>( 5346657Snate@binkert.org machInst, vd, vn, vm, false); 5356657Snate@binkert.org } else { 5366657Snate@binkert.org return decodeVfpRegRegRegOp<VmlsD>( 5376657Snate@binkert.org machInst, vd, vn, vm, true); 5386657Snate@binkert.org } 5396657Snate@binkert.org } 5406657Snate@binkert.org case 0x1: 5416657Snate@binkert.org if (bits(machInst, 6) == 1) { 5426657Snate@binkert.org if (single) { 5436657Snate@binkert.org return decodeVfpRegRegRegOp<VnmlaS>( 5446657Snate@binkert.org machInst, vd, vn, vm, false); 5459595Snilay@cs.wisc.edu } else { 5469273Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VnmlaD>( 5476657Snate@binkert.org machInst, vd, vn, vm, true); 5486657Snate@binkert.org } 5496657Snate@binkert.org } else { 5509364Snilay@cs.wisc.edu if (single) { 5517007Snate@binkert.org return decodeVfpRegRegRegOp<VnmlsS>( 5526657Snate@binkert.org machInst, vd, vn, vm, false); 5536657Snate@binkert.org } else { 5546657Snate@binkert.org return decodeVfpRegRegRegOp<VnmlsD>( 5556657Snate@binkert.org machInst, vd, vn, vm, true); 5567007Snate@binkert.org } 5576657Snate@binkert.org } 5587007Snate@binkert.org case 0x2: 5597007Snate@binkert.org if ((opc3 & 0x1) == 0) { 5606657Snate@binkert.org if (single) { 5616657Snate@binkert.org return decodeVfpRegRegRegOp<VmulS>( 5629508Snilay@cs.wisc.edu machInst, vd, vn, vm, false); 5636657Snate@binkert.org } else { 5646657Snate@binkert.org return decodeVfpRegRegRegOp<VmulD>( 5656657Snate@binkert.org machInst, vd, vn, vm, true); 5666657Snate@binkert.org } 5676657Snate@binkert.org } else { 5686657Snate@binkert.org if (single) { 5696657Snate@binkert.org return decodeVfpRegRegRegOp<VnmulS>( 5706657Snate@binkert.org machInst, vd, vn, vm, false); 5716657Snate@binkert.org } else { 5729508Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VnmulD>( 5736657Snate@binkert.org machInst, vd, vn, vm, true); 5747566SBrad.Beckmann@amd.com } 5759508Snilay@cs.wisc.edu } 5769508Snilay@cs.wisc.edu case 0x3: 5779508Snilay@cs.wisc.edu if ((opc3 & 0x1) == 0) { 5789508Snilay@cs.wisc.edu if (single) { 5799508Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VaddS>( 5809508Snilay@cs.wisc.edu machInst, vd, vn, vm, false); 5819604Snilay@cs.wisc.edu } else { 5829604Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VaddD>( 5839604Snilay@cs.wisc.edu machInst, vd, vn, vm, true); 5849508Snilay@cs.wisc.edu } 5856657Snate@binkert.org } else { 5866657Snate@binkert.org if (single) { 5876657Snate@binkert.org return decodeVfpRegRegRegOp<VsubS>( 5886657Snate@binkert.org machInst, vd, vn, vm, false); 5896657Snate@binkert.org } else { 5909595Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VsubD>( 5919595Snilay@cs.wisc.edu machInst, vd, vn, vm, true); 5929595Snilay@cs.wisc.edu } 5939595Snilay@cs.wisc.edu } 5949595Snilay@cs.wisc.edu case 0x8: 5959595Snilay@cs.wisc.edu if ((opc3 & 0x1) == 0) { 5968308Stushar@csail.mit.edu if (single) { 5979595Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VdivS>( 5986657Snate@binkert.org machInst, vd, vn, vm, false); 5996657Snate@binkert.org } else { 6009595Snilay@cs.wisc.edu return decodeVfpRegRegRegOp<VdivD>( 6019595Snilay@cs.wisc.edu machInst, vd, vn, vm, true); 6029595Snilay@cs.wisc.edu } 6039595Snilay@cs.wisc.edu } 6049595Snilay@cs.wisc.edu break; 6059508Snilay@cs.wisc.edu case 0xb: 6066657Snate@binkert.org if ((opc3 & 0x1) == 0) { 6076657Snate@binkert.org const uint32_t baseImm = 6086657Snate@binkert.org bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 6096657Snate@binkert.org if (single) { 6106657Snate@binkert.org uint32_t imm = vfp_modified_imm(baseImm, false); 6116657Snate@binkert.org return decodeVfpRegImmOp<VmovImmS>( 6126657Snate@binkert.org machInst, vd, imm, false); 6136657Snate@binkert.org } else { 6148187SLisa.Hsu@amd.com uint64_t imm = vfp_modified_imm(baseImm, true); 6156657Snate@binkert.org return decodeVfpRegImmOp<VmovImmD>( 6166657Snate@binkert.org machInst, vd, imm, true); 6176657Snate@binkert.org } 6186657Snate@binkert.org } 6196657Snate@binkert.org switch (opc2) { 6206657Snate@binkert.org case 0x0: 6216657Snate@binkert.org if (opc3 == 1) { 6226657Snate@binkert.org if (single) { 6236657Snate@binkert.org return decodeVfpRegRegOp<VmovRegS>( 6247454Snate@binkert.org machInst, vd, vm, false); 6256657Snate@binkert.org } else { 6266657Snate@binkert.org return decodeVfpRegRegOp<VmovRegD>( 6276657Snate@binkert.org machInst, vd, vm, true); 6286657Snate@binkert.org } 6297007Snate@binkert.org } else { 6307056Snate@binkert.org if (single) { 6317007Snate@binkert.org return decodeVfpRegRegOp<VabsS>( 6327007Snate@binkert.org machInst, vd, vm, false); 6336657Snate@binkert.org } else { 6347566SBrad.Beckmann@amd.com return decodeVfpRegRegOp<VabsD>( 6357566SBrad.Beckmann@amd.com machInst, vd, vm, true); 6369499Snilay@cs.wisc.edu } 6379499Snilay@cs.wisc.edu } 6387566SBrad.Beckmann@amd.com case 0x1: 6397566SBrad.Beckmann@amd.com if (opc3 == 1) { 6407566SBrad.Beckmann@amd.com if (single) { 6419366Snilay@cs.wisc.edu return decodeVfpRegRegOp<VnegS>( 6429366Snilay@cs.wisc.edu machInst, vd, vm, false); 6439366Snilay@cs.wisc.edu } else { 6449366Snilay@cs.wisc.edu return decodeVfpRegRegOp<VnegD>( 6457566SBrad.Beckmann@amd.com machInst, vd, vm, true); 6467672Snate@binkert.org } 6476657Snate@binkert.org } else { 6489465Snilay@cs.wisc.edu if (single) { 6496657Snate@binkert.org return decodeVfpRegRegOp<VsqrtS>( 6509465Snilay@cs.wisc.edu machInst, vd, vm, false); 6517056Snate@binkert.org } else { 6526657Snate@binkert.org return decodeVfpRegRegOp<VsqrtD>( 6536657Snate@binkert.org machInst, vd, vm, true); 6547672Snate@binkert.org } 6556657Snate@binkert.org } 6566657Snate@binkert.org case 0x2: 6576657Snate@binkert.org case 0x3: 6586657Snate@binkert.org { 6596657Snate@binkert.org const bool toHalf = bits(machInst, 16); 6606657Snate@binkert.org const bool top = bits(machInst, 7); 6616657Snate@binkert.org if (top) { 6626657Snate@binkert.org if (toHalf) { 6636657Snate@binkert.org return new VcvtFpSFpHT(machInst, vd, vm); 6646657Snate@binkert.org } else { 6656657Snate@binkert.org return new VcvtFpHTFpS(machInst, vd, vm); 6669745Snilay@cs.wisc.edu } 6676657Snate@binkert.org } else { 6686657Snate@binkert.org if (toHalf) { 6699496Snilay@cs.wisc.edu return new VcvtFpSFpHB(machInst, vd, vm); 6709496Snilay@cs.wisc.edu } else { 67110012Snilay@cs.wisc.edu return new VcvtFpHBFpS(machInst, vd, vm); 6729496Snilay@cs.wisc.edu } 6739496Snilay@cs.wisc.edu } 6746657Snate@binkert.org } 67510121Snilay@cs.wisc.edu case 0x4: 6766657Snate@binkert.org if (single) { 6776657Snate@binkert.org if (e) { 67810121Snilay@cs.wisc.edu return new VcmpeS(machInst, vd, vm); 6796657Snate@binkert.org } else { 6808683Snilay@cs.wisc.edu return new VcmpS(machInst, vd, vm); 6818683Snilay@cs.wisc.edu } 6828683Snilay@cs.wisc.edu } else { 6838683Snilay@cs.wisc.edu if (e) { 6848683Snilay@cs.wisc.edu return new VcmpeD(machInst, vd, vm); 6858683Snilay@cs.wisc.edu } else { 6866657Snate@binkert.org return new VcmpD(machInst, vd, vm); 6879745Snilay@cs.wisc.edu } 6889745Snilay@cs.wisc.edu } 6899745Snilay@cs.wisc.edu case 0x5: 6909745Snilay@cs.wisc.edu if (single) { 69110012Snilay@cs.wisc.edu if (e) { 69210012Snilay@cs.wisc.edu return new VcmpeZeroS(machInst, vd, 0); 6939745Snilay@cs.wisc.edu } else { 6949745Snilay@cs.wisc.edu return new VcmpZeroS(machInst, vd, 0); 6959745Snilay@cs.wisc.edu } 6969745Snilay@cs.wisc.edu } else { 6979745Snilay@cs.wisc.edu if (e) { 69810012Snilay@cs.wisc.edu return new VcmpeZeroD(machInst, vd, 0); 69910012Snilay@cs.wisc.edu } else { 7009745Snilay@cs.wisc.edu return new VcmpZeroD(machInst, vd, 0); 7019745Snilay@cs.wisc.edu } 7029745Snilay@cs.wisc.edu } 7039745Snilay@cs.wisc.edu case 0x7: 7049745Snilay@cs.wisc.edu if (opc3 == 0x3) { 7059745Snilay@cs.wisc.edu if (single) { 7069745Snilay@cs.wisc.edu vm = (IntRegIndex)(bits(machInst, 5) | 7079745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1)); 7089745Snilay@cs.wisc.edu return new VcvtFpSFpD(machInst, vd, vm); 7099745Snilay@cs.wisc.edu } else { 7109745Snilay@cs.wisc.edu vd = (IntRegIndex)(bits(machInst, 22) | 7119745Snilay@cs.wisc.edu (bits(machInst, 15, 12) << 1)); 7129745Snilay@cs.wisc.edu return new VcvtFpDFpS(machInst, vd, vm); 7139745Snilay@cs.wisc.edu } 7149745Snilay@cs.wisc.edu } 7159745Snilay@cs.wisc.edu break; 71610012Snilay@cs.wisc.edu case 0x8: 71710012Snilay@cs.wisc.edu if (bits(machInst, 7) == 0) { 7189745Snilay@cs.wisc.edu if (single) { 7199745Snilay@cs.wisc.edu return new VcvtUIntFpS(machInst, vd, vm); 7209745Snilay@cs.wisc.edu } else { 7219745Snilay@cs.wisc.edu vm = (IntRegIndex)(bits(machInst, 5) | 7229745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1)); 7239745Snilay@cs.wisc.edu return new VcvtUIntFpD(machInst, vd, vm); 7249745Snilay@cs.wisc.edu } 7259745Snilay@cs.wisc.edu } else { 7269745Snilay@cs.wisc.edu if (single) { 7279745Snilay@cs.wisc.edu return new VcvtSIntFpS(machInst, vd, vm); 7289745Snilay@cs.wisc.edu } else { 7299745Snilay@cs.wisc.edu vm = (IntRegIndex)(bits(machInst, 5) | 7309745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1)); 7319745Snilay@cs.wisc.edu return new VcvtSIntFpD(machInst, vd, vm); 7329745Snilay@cs.wisc.edu } 7339745Snilay@cs.wisc.edu } 7349745Snilay@cs.wisc.edu case 0xa: 7359745Snilay@cs.wisc.edu { 7369745Snilay@cs.wisc.edu const bool half = (bits(machInst, 7) == 0); 7379745Snilay@cs.wisc.edu const uint32_t imm = bits(machInst, 5) | 7389745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1); 7399745Snilay@cs.wisc.edu const uint32_t size = 7409745Snilay@cs.wisc.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 7419745Snilay@cs.wisc.edu if (single) { 7429745Snilay@cs.wisc.edu if (half) { 7439745Snilay@cs.wisc.edu return new VcvtSHFixedFpS(machInst, vd, vd, size); 7449745Snilay@cs.wisc.edu } else { 7459745Snilay@cs.wisc.edu return new VcvtSFixedFpS(machInst, vd, vd, size); 7469745Snilay@cs.wisc.edu } 7479745Snilay@cs.wisc.edu } else { 7489745Snilay@cs.wisc.edu if (half) { 7499745Snilay@cs.wisc.edu return new VcvtSHFixedFpD(machInst, vd, vd, size); 7509745Snilay@cs.wisc.edu } else { 7519745Snilay@cs.wisc.edu return new VcvtSFixedFpD(machInst, vd, vd, size); 7529745Snilay@cs.wisc.edu } 7539745Snilay@cs.wisc.edu } 7549745Snilay@cs.wisc.edu } 7559745Snilay@cs.wisc.edu case 0xb: 7569745Snilay@cs.wisc.edu { 7579745Snilay@cs.wisc.edu const bool half = (bits(machInst, 7) == 0); 7589745Snilay@cs.wisc.edu const uint32_t imm = bits(machInst, 5) | 7599745Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1); 7609745Snilay@cs.wisc.edu const uint32_t size = 7619745Snilay@cs.wisc.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 7629745Snilay@cs.wisc.edu if (single) { 7639745Snilay@cs.wisc.edu if (half) { 7649745Snilay@cs.wisc.edu return new VcvtUHFixedFpS(machInst, vd, vd, size); 7659745Snilay@cs.wisc.edu } else { 7669745Snilay@cs.wisc.edu return new VcvtUFixedFpS(machInst, vd, vd, size); 7679745Snilay@cs.wisc.edu } 7689745Snilay@cs.wisc.edu } else { 7699745Snilay@cs.wisc.edu if (half) { 7709745Snilay@cs.wisc.edu return new VcvtUHFixedFpD(machInst, vd, vd, size); 7719745Snilay@cs.wisc.edu } else { 7729745Snilay@cs.wisc.edu return new VcvtUFixedFpD(machInst, vd, vd, size); 7739745Snilay@cs.wisc.edu } 7749745Snilay@cs.wisc.edu } 7759745Snilay@cs.wisc.edu } 7769745Snilay@cs.wisc.edu case 0xc: 7779745Snilay@cs.wisc.edu if (bits(machInst, 7) == 0) { 7789745Snilay@cs.wisc.edu if (single) { 7799745Snilay@cs.wisc.edu return new VcvtFpUIntSR(machInst, vd, vm); 7809745Snilay@cs.wisc.edu } else { 7819745Snilay@cs.wisc.edu vd = (IntRegIndex)(bits(machInst, 22) | 7829745Snilay@cs.wisc.edu (bits(machInst, 15, 12) << 1)); 7839745Snilay@cs.wisc.edu return new VcvtFpUIntDR(machInst, vd, vm); 7849745Snilay@cs.wisc.edu } 7859745Snilay@cs.wisc.edu } else { 7869745Snilay@cs.wisc.edu if (single) { 7879745Snilay@cs.wisc.edu return new VcvtFpUIntS(machInst, vd, vm); 7889745Snilay@cs.wisc.edu } else { 7899745Snilay@cs.wisc.edu vd = (IntRegIndex)(bits(machInst, 22) | 7909745Snilay@cs.wisc.edu (bits(machInst, 15, 12) << 1)); 7919745Snilay@cs.wisc.edu return new VcvtFpUIntD(machInst, vd, vm); 7927007Snate@binkert.org } 7937007Snate@binkert.org } 7947007Snate@binkert.org case 0xd: 7956657Snate@binkert.org if (bits(machInst, 7) == 0) { 7966657Snate@binkert.org if (single) { 7976657Snate@binkert.org return new VcvtFpSIntSR(machInst, vd, vm); 7987007Snate@binkert.org } else { 7997007Snate@binkert.org vd = (IntRegIndex)(bits(machInst, 22) | 8007007Snate@binkert.org (bits(machInst, 15, 12) << 1)); 8016657Snate@binkert.org return new VcvtFpSIntDR(machInst, vd, vm); 8026657Snate@binkert.org } 8036657Snate@binkert.org } else { 8048683Snilay@cs.wisc.edu if (single) { 8058683Snilay@cs.wisc.edu return new VcvtFpSIntS(machInst, vd, vm); 8068683Snilay@cs.wisc.edu } else { 8078683Snilay@cs.wisc.edu vd = (IntRegIndex)(bits(machInst, 22) | 8088683Snilay@cs.wisc.edu (bits(machInst, 15, 12) << 1)); 8098683Snilay@cs.wisc.edu return new VcvtFpSIntD(machInst, vd, vm); 8107007Snate@binkert.org } 8117007Snate@binkert.org } 8127007Snate@binkert.org case 0xe: 8136657Snate@binkert.org { 8146657Snate@binkert.org const bool half = (bits(machInst, 7) == 0); 8156657Snate@binkert.org const uint32_t imm = bits(machInst, 5) | 8167007Snate@binkert.org (bits(machInst, 3, 0) << 1); 8177007Snate@binkert.org const uint32_t size = 8187007Snate@binkert.org (bits(machInst, 7) == 0 ? 16 : 32) - imm; 8197007Snate@binkert.org if (single) { 8207007Snate@binkert.org if (half) { 8216657Snate@binkert.org return new VcvtFpSHFixedS(machInst, vd, vd, size); 82210012Snilay@cs.wisc.edu } else { 8239745Snilay@cs.wisc.edu return new VcvtFpSFixedS(machInst, vd, vd, size); 8249745Snilay@cs.wisc.edu } 8259745Snilay@cs.wisc.edu } else { 8269745Snilay@cs.wisc.edu if (half) { 8279745Snilay@cs.wisc.edu return new VcvtFpSHFixedD(machInst, vd, vd, size); 8289745Snilay@cs.wisc.edu } else { 8296902SBrad.Beckmann@amd.com return new VcvtFpSFixedD(machInst, vd, vd, size); 8309745Snilay@cs.wisc.edu } 8319745Snilay@cs.wisc.edu } 8329745Snilay@cs.wisc.edu } 8339745Snilay@cs.wisc.edu case 0xf: 83410012Snilay@cs.wisc.edu { 8356902SBrad.Beckmann@amd.com const bool half = (bits(machInst, 7) == 0); 8367839Snilay@cs.wisc.edu const uint32_t imm = bits(machInst, 5) | 8377839Snilay@cs.wisc.edu (bits(machInst, 3, 0) << 1); 8387839Snilay@cs.wisc.edu const uint32_t size = 8397839Snilay@cs.wisc.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 8407839Snilay@cs.wisc.edu if (single) { 8417839Snilay@cs.wisc.edu if (half) { 8427839Snilay@cs.wisc.edu return new VcvtFpUHFixedS(machInst, vd, vd, size); 8437839Snilay@cs.wisc.edu } else { 8447839Snilay@cs.wisc.edu return new VcvtFpUFixedS(machInst, vd, vd, size); 8457839Snilay@cs.wisc.edu } 8467839Snilay@cs.wisc.edu } else { 8477839Snilay@cs.wisc.edu if (half) { 8487839Snilay@cs.wisc.edu return new VcvtFpUHFixedD(machInst, vd, vd, size); 8497839Snilay@cs.wisc.edu } else { 8507839Snilay@cs.wisc.edu return new VcvtFpUFixedD(machInst, vd, vd, size); 8517839Snilay@cs.wisc.edu } 8527839Snilay@cs.wisc.edu } 8537839Snilay@cs.wisc.edu } 8547839Snilay@cs.wisc.edu } 8557839Snilay@cs.wisc.edu break; 8567839Snilay@cs.wisc.edu } 8577839Snilay@cs.wisc.edu return new Unknown(machInst); 8587839Snilay@cs.wisc.edu } 8597839Snilay@cs.wisc.edu ''' 8607839Snilay@cs.wisc.edu}}; 8617839Snilay@cs.wisc.edu 8627839Snilay@cs.wisc.edudef format VfpData() {{ 8637839Snilay@cs.wisc.edu decode_block = ''' 8647839Snilay@cs.wisc.edu return decodeVfpData(machInst); 8657839Snilay@cs.wisc.edu ''' 8667839Snilay@cs.wisc.edu}}; 8677839Snilay@cs.wisc.edu