fp.isa revision 7394
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 37178Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47178Sgblack@eecs.umich.edu// All rights reserved 57178Sgblack@eecs.umich.edu// 67178Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77178Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87178Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97178Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107178Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117178Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127178Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137178Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147178Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Floating Point operate instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edudef template FPAExecute {{ 496019Shines@cs.fsu.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 506019Shines@cs.fsu.edu { 516019Shines@cs.fsu.edu Fault fault = NoFault; 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edu %(fp_enable_check)s; 546019Shines@cs.fsu.edu 556019Shines@cs.fsu.edu %(op_decl)s; 566019Shines@cs.fsu.edu %(op_rd)s; 576019Shines@cs.fsu.edu 586243Sgblack@eecs.umich.edu if (%(predicate_test)s) { 596243Sgblack@eecs.umich.edu %(code)s; 606243Sgblack@eecs.umich.edu if (fault == NoFault) { 616243Sgblack@eecs.umich.edu %(op_wb)s; 626243Sgblack@eecs.umich.edu } 636019Shines@cs.fsu.edu } 646019Shines@cs.fsu.edu 656019Shines@cs.fsu.edu return fault; 666019Shines@cs.fsu.edu } 676019Shines@cs.fsu.edu}}; 686019Shines@cs.fsu.edu 696019Shines@cs.fsu.edudef template FloatDoubleDecode {{ 706019Shines@cs.fsu.edu { 716019Shines@cs.fsu.edu ArmStaticInst *i = NULL; 726019Shines@cs.fsu.edu switch (OPCODE_19 << 1 | OPCODE_7) 736019Shines@cs.fsu.edu { 746019Shines@cs.fsu.edu case 0: 756019Shines@cs.fsu.edu i = (ArmStaticInst *)new %(class_name)sS(machInst); 766019Shines@cs.fsu.edu break; 776019Shines@cs.fsu.edu case 1: 786019Shines@cs.fsu.edu i = (ArmStaticInst *)new %(class_name)sD(machInst); 796019Shines@cs.fsu.edu break; 806019Shines@cs.fsu.edu case 2: 816019Shines@cs.fsu.edu case 3: 826019Shines@cs.fsu.edu default: 836019Shines@cs.fsu.edu panic("Cannot decode float/double nature of the instruction"); 846019Shines@cs.fsu.edu } 856019Shines@cs.fsu.edu return i; 866019Shines@cs.fsu.edu } 876019Shines@cs.fsu.edu}}; 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu// Primary format for float point operate instructions: 906019Shines@cs.fsu.edudef format FloatOp(code, *flags) {{ 916019Shines@cs.fsu.edu orig_code = code 926019Shines@cs.fsu.edu 936019Shines@cs.fsu.edu cblk = code 946252Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 956243Sgblack@eecs.umich.edu {"code": cblk, 966243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 976243Sgblack@eecs.umich.edu flags) 986019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 996019Shines@cs.fsu.edu decoder_output = BasicConstructor.subst(iop) 1006019Shines@cs.fsu.edu exec_output = FPAExecute.subst(iop) 1016019Shines@cs.fsu.edu 1026019Shines@cs.fsu.edu sng_cblk = code 1036252Sgblack@eecs.umich.edu sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1046243Sgblack@eecs.umich.edu {"code": sng_cblk, 1056243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1066243Sgblack@eecs.umich.edu flags) 1076019Shines@cs.fsu.edu header_output += BasicDeclare.subst(sng_iop) 1086019Shines@cs.fsu.edu decoder_output += BasicConstructor.subst(sng_iop) 1096019Shines@cs.fsu.edu exec_output += FPAExecute.subst(sng_iop) 1106019Shines@cs.fsu.edu 1116019Shines@cs.fsu.edu dbl_code = re.sub(r'\.sf', '.df', orig_code) 1126019Shines@cs.fsu.edu 1136019Shines@cs.fsu.edu dbl_cblk = dbl_code 1146252Sgblack@eecs.umich.edu dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1156243Sgblack@eecs.umich.edu {"code": dbl_cblk, 1166243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1176243Sgblack@eecs.umich.edu flags) 1186019Shines@cs.fsu.edu header_output += BasicDeclare.subst(dbl_iop) 1196019Shines@cs.fsu.edu decoder_output += BasicConstructor.subst(dbl_iop) 1206019Shines@cs.fsu.edu exec_output += FPAExecute.subst(dbl_iop) 1216019Shines@cs.fsu.edu 1226019Shines@cs.fsu.edu decode_block = FloatDoubleDecode.subst(iop) 1236019Shines@cs.fsu.edu}}; 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edulet {{ 1266019Shines@cs.fsu.edu calcFPCcCode = ''' 1276019Shines@cs.fsu.edu uint16_t _in, _iz, _ic, _iv; 1286019Shines@cs.fsu.edu 1296019Shines@cs.fsu.edu _in = %(fReg1)s < %(fReg2)s; 1306019Shines@cs.fsu.edu _iz = %(fReg1)s == %(fReg2)s; 1316019Shines@cs.fsu.edu _ic = %(fReg1)s >= %(fReg2)s; 1326019Shines@cs.fsu.edu _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 1336019Shines@cs.fsu.edu 1346724Sgblack@eecs.umich.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 1356724Sgblack@eecs.umich.edu (CondCodes & 0x0FFFFFFF); 1366019Shines@cs.fsu.edu ''' 1376019Shines@cs.fsu.edu}}; 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edudef format FloatCmp(fReg1, fReg2, *flags) {{ 1406019Shines@cs.fsu.edu code = calcFPCcCode % vars() 1416252Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 1426243Sgblack@eecs.umich.edu {"code": code, 1436243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1446243Sgblack@eecs.umich.edu flags) 1456019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 1466019Shines@cs.fsu.edu decoder_output = BasicConstructor.subst(iop) 1476019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 1486019Shines@cs.fsu.edu exec_output = FPAExecute.subst(iop) 1496019Shines@cs.fsu.edu}}; 1506019Shines@cs.fsu.edu 1517356Sgblack@eecs.umich.edulet {{ 1527356Sgblack@eecs.umich.edu header_output = ''' 1537356Sgblack@eecs.umich.edu StaticInstPtr 1547356Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst); 1557356Sgblack@eecs.umich.edu ''' 1567356Sgblack@eecs.umich.edu decoder_output = ''' 1577356Sgblack@eecs.umich.edu StaticInstPtr 1587356Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst) 1597178Sgblack@eecs.umich.edu { 1607178Sgblack@eecs.umich.edu const uint32_t opcode = bits(machInst, 24, 20); 1617178Sgblack@eecs.umich.edu const uint32_t offset = bits(machInst, 7, 0); 1627337Sgblack@eecs.umich.edu const bool single = (bits(machInst, 8) == 0); 1637178Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1647178Sgblack@eecs.umich.edu RegIndex vd; 1657178Sgblack@eecs.umich.edu if (single) { 1667178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1677178Sgblack@eecs.umich.edu bits(machInst, 22)); 1687178Sgblack@eecs.umich.edu } else { 1697178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1707178Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 1717178Sgblack@eecs.umich.edu } 1727178Sgblack@eecs.umich.edu switch (bits(opcode, 4, 3)) { 1737178Sgblack@eecs.umich.edu case 0x0: 1747335Sgblack@eecs.umich.edu if (bits(opcode, 4, 1) == 0x2 && 1757335Sgblack@eecs.umich.edu !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 1767335Sgblack@eecs.umich.edu !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 1777335Sgblack@eecs.umich.edu if ((bits(machInst, 7, 4) & 0xd) != 1) { 1787335Sgblack@eecs.umich.edu break; 1797335Sgblack@eecs.umich.edu } 1807335Sgblack@eecs.umich.edu const IntRegIndex rt = 1817335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1827335Sgblack@eecs.umich.edu const IntRegIndex rt2 = 1837335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1847335Sgblack@eecs.umich.edu const bool op = bits(machInst, 20); 1857335Sgblack@eecs.umich.edu uint32_t vm; 1867337Sgblack@eecs.umich.edu if (single) { 1877335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 1887335Sgblack@eecs.umich.edu } else { 1897335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | 1907335Sgblack@eecs.umich.edu (bits(machInst, 5) << 5); 1917335Sgblack@eecs.umich.edu } 1927335Sgblack@eecs.umich.edu if (op) { 1937335Sgblack@eecs.umich.edu return new Vmov2Core2Reg(machInst, rt, rt2, 1947335Sgblack@eecs.umich.edu (IntRegIndex)vm); 1957335Sgblack@eecs.umich.edu } else { 1967335Sgblack@eecs.umich.edu return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 1977335Sgblack@eecs.umich.edu rt, rt2); 1987335Sgblack@eecs.umich.edu } 1997178Sgblack@eecs.umich.edu } 2007178Sgblack@eecs.umich.edu break; 2017178Sgblack@eecs.umich.edu case 0x1: 2027178Sgblack@eecs.umich.edu switch (bits(opcode, 1, 0)) { 2037178Sgblack@eecs.umich.edu case 0x0: 2047178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2057178Sgblack@eecs.umich.edu true, false, false, offset); 2067178Sgblack@eecs.umich.edu case 0x1: 2077178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2087178Sgblack@eecs.umich.edu true, false, true, offset); 2097178Sgblack@eecs.umich.edu case 0x2: 2107178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2117178Sgblack@eecs.umich.edu true, true, false, offset); 2127178Sgblack@eecs.umich.edu case 0x3: 2137178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpop. 2147178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2157178Sgblack@eecs.umich.edu true, true, true, offset); 2167178Sgblack@eecs.umich.edu } 2177178Sgblack@eecs.umich.edu case 0x2: 2187178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x2) { 2197178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpush. 2207178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2217178Sgblack@eecs.umich.edu false, true, false, offset); 2227178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x3) { 2237178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2247178Sgblack@eecs.umich.edu false, true, true, offset); 2257178Sgblack@eecs.umich.edu } 2267178Sgblack@eecs.umich.edu // Fall through on purpose 2277178Sgblack@eecs.umich.edu case 0x3: 2287346Sgblack@eecs.umich.edu const bool up = (bits(machInst, 23) == 1); 2297346Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) << 2; 2307346Sgblack@eecs.umich.edu RegIndex vd; 2317346Sgblack@eecs.umich.edu if (single) { 2327346Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2337346Sgblack@eecs.umich.edu (bits(machInst, 22))); 2347346Sgblack@eecs.umich.edu } else { 2357346Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2367346Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 2377346Sgblack@eecs.umich.edu } 2387178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x0) { 2397346Sgblack@eecs.umich.edu if (single) { 2407346Sgblack@eecs.umich.edu if (up) { 2417346Sgblack@eecs.umich.edu return new %(vstr_us)s(machInst, vd, rn, up, imm); 2427346Sgblack@eecs.umich.edu } else { 2437346Sgblack@eecs.umich.edu return new %(vstr_s)s(machInst, vd, rn, up, imm); 2447346Sgblack@eecs.umich.edu } 2457346Sgblack@eecs.umich.edu } else { 2467346Sgblack@eecs.umich.edu if (up) { 2477346Sgblack@eecs.umich.edu return new %(vstr_ud)s(machInst, vd, vd + 1, 2487346Sgblack@eecs.umich.edu rn, up, imm); 2497346Sgblack@eecs.umich.edu } else { 2507346Sgblack@eecs.umich.edu return new %(vstr_d)s(machInst, vd, vd + 1, 2517346Sgblack@eecs.umich.edu rn, up, imm); 2527346Sgblack@eecs.umich.edu } 2537346Sgblack@eecs.umich.edu } 2547178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x1) { 2557337Sgblack@eecs.umich.edu if (single) { 2567337Sgblack@eecs.umich.edu if (up) { 2577337Sgblack@eecs.umich.edu return new %(vldr_us)s(machInst, vd, rn, up, imm); 2587337Sgblack@eecs.umich.edu } else { 2597337Sgblack@eecs.umich.edu return new %(vldr_s)s(machInst, vd, rn, up, imm); 2607337Sgblack@eecs.umich.edu } 2617337Sgblack@eecs.umich.edu } else { 2627337Sgblack@eecs.umich.edu if (up) { 2637337Sgblack@eecs.umich.edu return new %(vldr_ud)s(machInst, vd, vd + 1, 2647337Sgblack@eecs.umich.edu rn, up, imm); 2657337Sgblack@eecs.umich.edu } else { 2667337Sgblack@eecs.umich.edu return new %(vldr_d)s(machInst, vd, vd + 1, 2677337Sgblack@eecs.umich.edu rn, up, imm); 2687337Sgblack@eecs.umich.edu } 2697337Sgblack@eecs.umich.edu } 2707178Sgblack@eecs.umich.edu } 2717178Sgblack@eecs.umich.edu } 2727178Sgblack@eecs.umich.edu return new Unknown(machInst); 2737178Sgblack@eecs.umich.edu } 2747337Sgblack@eecs.umich.edu ''' % { 2757337Sgblack@eecs.umich.edu "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 2767337Sgblack@eecs.umich.edu "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 2777337Sgblack@eecs.umich.edu "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 2787346Sgblack@eecs.umich.edu "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 2797346Sgblack@eecs.umich.edu "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 2807346Sgblack@eecs.umich.edu "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 2817346Sgblack@eecs.umich.edu "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 2827346Sgblack@eecs.umich.edu "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 2837337Sgblack@eecs.umich.edu } 2847178Sgblack@eecs.umich.edu}}; 2857321Sgblack@eecs.umich.edu 2867356Sgblack@eecs.umich.edudef format ExtensionRegLoadStore() {{ 2877321Sgblack@eecs.umich.edu decode_block = ''' 2887356Sgblack@eecs.umich.edu return decodeExtensionRegLoadStore(machInst); 2897356Sgblack@eecs.umich.edu ''' 2907356Sgblack@eecs.umich.edu}}; 2917356Sgblack@eecs.umich.edu 2927356Sgblack@eecs.umich.edulet {{ 2937356Sgblack@eecs.umich.edu header_output = ''' 2947356Sgblack@eecs.umich.edu StaticInstPtr 2957356Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst); 2967356Sgblack@eecs.umich.edu ''' 2977356Sgblack@eecs.umich.edu decoder_output = ''' 2987356Sgblack@eecs.umich.edu StaticInstPtr 2997356Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst) 3007321Sgblack@eecs.umich.edu { 3017321Sgblack@eecs.umich.edu const uint32_t l = bits(machInst, 20); 3027321Sgblack@eecs.umich.edu const uint32_t c = bits(machInst, 8); 3037321Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 23, 21); 3047321Sgblack@eecs.umich.edu const uint32_t b = bits(machInst, 6, 5); 3057321Sgblack@eecs.umich.edu if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 3067321Sgblack@eecs.umich.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 3077321Sgblack@eecs.umich.edu return new Unknown(machInst); 3087321Sgblack@eecs.umich.edu } 3097321Sgblack@eecs.umich.edu if (l == 0 && c == 0) { 3107321Sgblack@eecs.umich.edu if (a == 0) { 3117335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3127335Sgblack@eecs.umich.edu bits(machInst, 7); 3137335Sgblack@eecs.umich.edu const IntRegIndex rt = 3147335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3157335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3167335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3177335Sgblack@eecs.umich.edu } else { 3187335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3197335Sgblack@eecs.umich.edu } 3207321Sgblack@eecs.umich.edu } else if (a == 0x7) { 3217323Sgblack@eecs.umich.edu const IntRegIndex rt = 3227323Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3237323Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3247323Sgblack@eecs.umich.edu switch (specReg) { 3257323Sgblack@eecs.umich.edu case 0: 3267323Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3277323Sgblack@eecs.umich.edu break; 3287323Sgblack@eecs.umich.edu case 1: 3297323Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3307323Sgblack@eecs.umich.edu break; 3317394Sgblack@eecs.umich.edu case 6: 3327394Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 3337394Sgblack@eecs.umich.edu break; 3347394Sgblack@eecs.umich.edu case 7: 3357394Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 3367394Sgblack@eecs.umich.edu break; 3377323Sgblack@eecs.umich.edu case 8: 3387323Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 3397323Sgblack@eecs.umich.edu break; 3407323Sgblack@eecs.umich.edu default: 3417323Sgblack@eecs.umich.edu return new Unknown(machInst); 3427323Sgblack@eecs.umich.edu } 3437323Sgblack@eecs.umich.edu return new Vmsr(machInst, (IntRegIndex)specReg, rt); 3447321Sgblack@eecs.umich.edu } 3457321Sgblack@eecs.umich.edu } else if (l == 0 && c == 1) { 3467321Sgblack@eecs.umich.edu if (bits(a, 2) == 0) { 3477335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 3487335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 3497335Sgblack@eecs.umich.edu uint32_t index, size; 3507335Sgblack@eecs.umich.edu const IntRegIndex rt = 3517335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3527335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 3537335Sgblack@eecs.umich.edu size = 8; 3547335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 3557335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 3567335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 3577335Sgblack@eecs.umich.edu size = 16; 3587335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 3597335Sgblack@eecs.umich.edu bits(machInst, 6); 3607335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0) { 3617335Sgblack@eecs.umich.edu size = 32; 3627335Sgblack@eecs.umich.edu index = bits(machInst, 21); 3637335Sgblack@eecs.umich.edu } else { 3647335Sgblack@eecs.umich.edu return new Unknown(machInst); 3657335Sgblack@eecs.umich.edu } 3667335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 3677335Sgblack@eecs.umich.edu index -= (32 / size); 3687335Sgblack@eecs.umich.edu vd++; 3697335Sgblack@eecs.umich.edu } 3707335Sgblack@eecs.umich.edu switch (size) { 3717335Sgblack@eecs.umich.edu case 8: 3727335Sgblack@eecs.umich.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 3737335Sgblack@eecs.umich.edu rt, index); 3747335Sgblack@eecs.umich.edu case 16: 3757335Sgblack@eecs.umich.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 3767335Sgblack@eecs.umich.edu rt, index); 3777335Sgblack@eecs.umich.edu case 32: 3787335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 3797335Sgblack@eecs.umich.edu } 3807321Sgblack@eecs.umich.edu } else if (bits(b, 1) == 0) { 3817321Sgblack@eecs.umich.edu // A8-594 3827321Sgblack@eecs.umich.edu return new WarnUnimplemented("vdup", machInst); 3837321Sgblack@eecs.umich.edu } 3847321Sgblack@eecs.umich.edu } else if (l == 1 && c == 0) { 3857321Sgblack@eecs.umich.edu if (a == 0) { 3867335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3877335Sgblack@eecs.umich.edu bits(machInst, 7); 3887335Sgblack@eecs.umich.edu const IntRegIndex rt = 3897335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3907335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3917335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3927335Sgblack@eecs.umich.edu } else { 3937335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3947335Sgblack@eecs.umich.edu } 3957321Sgblack@eecs.umich.edu } else if (a == 7) { 3967326Sgblack@eecs.umich.edu const IntRegIndex rt = 3977326Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3987326Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3997326Sgblack@eecs.umich.edu switch (specReg) { 4007326Sgblack@eecs.umich.edu case 0: 4017326Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 4027326Sgblack@eecs.umich.edu break; 4037326Sgblack@eecs.umich.edu case 1: 4047326Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 4057326Sgblack@eecs.umich.edu break; 4067326Sgblack@eecs.umich.edu case 6: 4077326Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 4087326Sgblack@eecs.umich.edu break; 4097326Sgblack@eecs.umich.edu case 7: 4107326Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 4117326Sgblack@eecs.umich.edu break; 4127326Sgblack@eecs.umich.edu case 8: 4137326Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 4147326Sgblack@eecs.umich.edu break; 4157326Sgblack@eecs.umich.edu default: 4167326Sgblack@eecs.umich.edu return new Unknown(machInst); 4177326Sgblack@eecs.umich.edu } 4187392Sgblack@eecs.umich.edu if (rt == 0xf) { 4197392Sgblack@eecs.umich.edu CPSR cpsrMask = 0; 4207392Sgblack@eecs.umich.edu cpsrMask.n = 1; 4217392Sgblack@eecs.umich.edu cpsrMask.z = 1; 4227392Sgblack@eecs.umich.edu cpsrMask.c = 1; 4237392Sgblack@eecs.umich.edu cpsrMask.v = 1; 4247392Sgblack@eecs.umich.edu return new VmrsApsr(machInst, INTREG_CONDCODES, 4257392Sgblack@eecs.umich.edu (IntRegIndex)specReg, (uint32_t)cpsrMask); 4267392Sgblack@eecs.umich.edu } else { 4277392Sgblack@eecs.umich.edu return new Vmrs(machInst, rt, (IntRegIndex)specReg); 4287392Sgblack@eecs.umich.edu } 4297321Sgblack@eecs.umich.edu } 4307321Sgblack@eecs.umich.edu } else { 4317335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 4327335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 4337335Sgblack@eecs.umich.edu uint32_t index, size; 4347335Sgblack@eecs.umich.edu const IntRegIndex rt = 4357335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 4367335Sgblack@eecs.umich.edu const bool u = (bits(machInst, 23) == 1); 4377335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 4387335Sgblack@eecs.umich.edu size = 8; 4397335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 4407335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 4417335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 4427335Sgblack@eecs.umich.edu size = 16; 4437335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 4447335Sgblack@eecs.umich.edu bits(machInst, 6); 4457335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0 && !u) { 4467335Sgblack@eecs.umich.edu size = 32; 4477335Sgblack@eecs.umich.edu index = bits(machInst, 21); 4487335Sgblack@eecs.umich.edu } else { 4497335Sgblack@eecs.umich.edu return new Unknown(machInst); 4507335Sgblack@eecs.umich.edu } 4517335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 4527335Sgblack@eecs.umich.edu index -= (32 / size); 4537335Sgblack@eecs.umich.edu vd++; 4547335Sgblack@eecs.umich.edu } 4557335Sgblack@eecs.umich.edu switch (size) { 4567335Sgblack@eecs.umich.edu case 8: 4577335Sgblack@eecs.umich.edu if (u) { 4587335Sgblack@eecs.umich.edu return new VmovRegCoreUB(machInst, rt, 4597335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4607335Sgblack@eecs.umich.edu } else { 4617335Sgblack@eecs.umich.edu return new VmovRegCoreSB(machInst, rt, 4627335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4637335Sgblack@eecs.umich.edu } 4647335Sgblack@eecs.umich.edu case 16: 4657335Sgblack@eecs.umich.edu if (u) { 4667335Sgblack@eecs.umich.edu return new VmovRegCoreUH(machInst, rt, 4677335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4687335Sgblack@eecs.umich.edu } else { 4697335Sgblack@eecs.umich.edu return new VmovRegCoreSH(machInst, rt, 4707335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4717335Sgblack@eecs.umich.edu } 4727335Sgblack@eecs.umich.edu case 32: 4737335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 4747335Sgblack@eecs.umich.edu } 4757321Sgblack@eecs.umich.edu } 4767321Sgblack@eecs.umich.edu return new Unknown(machInst); 4777321Sgblack@eecs.umich.edu } 4787321Sgblack@eecs.umich.edu ''' 4797321Sgblack@eecs.umich.edu}}; 4807356Sgblack@eecs.umich.edu 4817356Sgblack@eecs.umich.edudef format ShortFpTransfer() {{ 4827356Sgblack@eecs.umich.edu decode_block = ''' 4837356Sgblack@eecs.umich.edu return decodeShortFpTransfer(machInst); 4847356Sgblack@eecs.umich.edu ''' 4857356Sgblack@eecs.umich.edu}}; 4867363Sgblack@eecs.umich.edu 4877363Sgblack@eecs.umich.edulet {{ 4887363Sgblack@eecs.umich.edu header_output = ''' 4897363Sgblack@eecs.umich.edu StaticInstPtr 4907363Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst); 4917363Sgblack@eecs.umich.edu ''' 4927363Sgblack@eecs.umich.edu decoder_output = ''' 4937363Sgblack@eecs.umich.edu StaticInstPtr 4947363Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst) 4957363Sgblack@eecs.umich.edu { 4967363Sgblack@eecs.umich.edu const uint32_t opc1 = bits(machInst, 23, 20); 4977363Sgblack@eecs.umich.edu const uint32_t opc2 = bits(machInst, 19, 16); 4987363Sgblack@eecs.umich.edu const uint32_t opc3 = bits(machInst, 7, 6); 4997363Sgblack@eecs.umich.edu //const uint32_t opc4 = bits(machInst, 3, 0); 5007372Sgblack@eecs.umich.edu const bool single = (bits(machInst, 8) == 0); 5017389Sgblack@eecs.umich.edu // Used to select between vcmp and vcmpe. 5027389Sgblack@eecs.umich.edu const bool e = (bits(machInst, 7) == 1); 5037372Sgblack@eecs.umich.edu IntRegIndex vd; 5047372Sgblack@eecs.umich.edu IntRegIndex vm; 5057372Sgblack@eecs.umich.edu IntRegIndex vn; 5067372Sgblack@eecs.umich.edu if (single) { 5077372Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 5087372Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 5097372Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 5107372Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 5117372Sgblack@eecs.umich.edu vn = (IntRegIndex)(bits(machInst, 7) | 5127372Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1)); 5137372Sgblack@eecs.umich.edu } else { 5147372Sgblack@eecs.umich.edu vd = (IntRegIndex)((bits(machInst, 22) << 5) | 5157372Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 5167372Sgblack@eecs.umich.edu vm = (IntRegIndex)((bits(machInst, 5) << 5) | 5177372Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 5187372Sgblack@eecs.umich.edu vn = (IntRegIndex)((bits(machInst, 7) << 5) | 5197372Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1)); 5207372Sgblack@eecs.umich.edu } 5217363Sgblack@eecs.umich.edu switch (opc1 & 0xb /* 1011 */) { 5227363Sgblack@eecs.umich.edu case 0x0: 5237370Sgblack@eecs.umich.edu if (bits(machInst, 6) == 0) { 5247372Sgblack@eecs.umich.edu if (single) { 5257376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlaS>( 5267376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5277370Sgblack@eecs.umich.edu } else { 5287376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlaD>( 5297376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5307370Sgblack@eecs.umich.edu } 5317370Sgblack@eecs.umich.edu } else { 5327372Sgblack@eecs.umich.edu if (single) { 5337376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlsS>( 5347376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5357370Sgblack@eecs.umich.edu } else { 5367376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmlsD>( 5377376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5387370Sgblack@eecs.umich.edu } 5397370Sgblack@eecs.umich.edu } 5407371Sgblack@eecs.umich.edu case 0x1: 5417371Sgblack@eecs.umich.edu if (bits(machInst, 6) == 1) { 5427372Sgblack@eecs.umich.edu if (single) { 5437376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlaS>( 5447376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5457371Sgblack@eecs.umich.edu } else { 5467376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlaD>( 5477376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5487371Sgblack@eecs.umich.edu } 5497371Sgblack@eecs.umich.edu } else { 5507372Sgblack@eecs.umich.edu if (single) { 5517376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlsS>( 5527376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5537371Sgblack@eecs.umich.edu } else { 5547376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmlsD>( 5557376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5567371Sgblack@eecs.umich.edu } 5577371Sgblack@eecs.umich.edu } 5587363Sgblack@eecs.umich.edu case 0x2: 5597363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5607372Sgblack@eecs.umich.edu if (single) { 5617376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmulS>( 5627376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5637364Sgblack@eecs.umich.edu } else { 5647376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VmulD>( 5657376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5667364Sgblack@eecs.umich.edu } 5677371Sgblack@eecs.umich.edu } else { 5687372Sgblack@eecs.umich.edu if (single) { 5697376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmulS>( 5707376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5717371Sgblack@eecs.umich.edu } else { 5727376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VnmulD>( 5737376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5747371Sgblack@eecs.umich.edu } 5757363Sgblack@eecs.umich.edu } 5767363Sgblack@eecs.umich.edu case 0x3: 5777363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5787372Sgblack@eecs.umich.edu if (single) { 5797376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VaddS>( 5807376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5817367Sgblack@eecs.umich.edu } else { 5827376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VaddD>( 5837376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5847367Sgblack@eecs.umich.edu } 5857363Sgblack@eecs.umich.edu } else { 5867372Sgblack@eecs.umich.edu if (single) { 5877376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VsubS>( 5887376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5897368Sgblack@eecs.umich.edu } else { 5907376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VsubD>( 5917376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 5927368Sgblack@eecs.umich.edu } 5937363Sgblack@eecs.umich.edu } 5947363Sgblack@eecs.umich.edu case 0x8: 5957363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5967372Sgblack@eecs.umich.edu if (single) { 5977376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VdivS>( 5987376Sgblack@eecs.umich.edu machInst, vd, vn, vm, false); 5997369Sgblack@eecs.umich.edu } else { 6007376Sgblack@eecs.umich.edu return decodeVfpRegRegRegOp<VdivD>( 6017376Sgblack@eecs.umich.edu machInst, vd, vn, vm, true); 6027369Sgblack@eecs.umich.edu } 6037363Sgblack@eecs.umich.edu } 6047363Sgblack@eecs.umich.edu break; 6057363Sgblack@eecs.umich.edu case 0xb: 6067363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 6077363Sgblack@eecs.umich.edu const uint32_t baseImm = 6087363Sgblack@eecs.umich.edu bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 6097372Sgblack@eecs.umich.edu if (single) { 6107363Sgblack@eecs.umich.edu uint32_t imm = vfp_modified_imm(baseImm, false); 6117376Sgblack@eecs.umich.edu return decodeVfpRegImmOp<VmovImmS>( 6127376Sgblack@eecs.umich.edu machInst, vd, imm, false); 6137363Sgblack@eecs.umich.edu } else { 6147363Sgblack@eecs.umich.edu uint64_t imm = vfp_modified_imm(baseImm, true); 6157376Sgblack@eecs.umich.edu return decodeVfpRegImmOp<VmovImmD>( 6167376Sgblack@eecs.umich.edu machInst, vd, imm, true); 6177363Sgblack@eecs.umich.edu } 6187363Sgblack@eecs.umich.edu } 6197363Sgblack@eecs.umich.edu switch (opc2) { 6207363Sgblack@eecs.umich.edu case 0x0: 6217363Sgblack@eecs.umich.edu if (opc3 == 1) { 6227372Sgblack@eecs.umich.edu if (single) { 6237376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VmovRegS>( 6247376Sgblack@eecs.umich.edu machInst, vd, vm, false); 6257363Sgblack@eecs.umich.edu } else { 6267376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VmovRegD>( 6277376Sgblack@eecs.umich.edu machInst, vd, vm, true); 6287363Sgblack@eecs.umich.edu } 6297363Sgblack@eecs.umich.edu } else { 6307372Sgblack@eecs.umich.edu if (single) { 6317376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VabsS>( 6327376Sgblack@eecs.umich.edu machInst, vd, vm, false); 6337366Sgblack@eecs.umich.edu } else { 6347376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VabsD>( 6357376Sgblack@eecs.umich.edu machInst, vd, vm, true); 6367366Sgblack@eecs.umich.edu } 6377363Sgblack@eecs.umich.edu } 6387363Sgblack@eecs.umich.edu case 0x1: 6397363Sgblack@eecs.umich.edu if (opc3 == 1) { 6407372Sgblack@eecs.umich.edu if (single) { 6417376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VnegS>( 6427376Sgblack@eecs.umich.edu machInst, vd, vm, false); 6437365Sgblack@eecs.umich.edu } else { 6447376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VnegD>( 6457376Sgblack@eecs.umich.edu machInst, vd, vm, true); 6467365Sgblack@eecs.umich.edu } 6477363Sgblack@eecs.umich.edu } else { 6487372Sgblack@eecs.umich.edu if (single) { 6497376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VsqrtS>( 6507376Sgblack@eecs.umich.edu machInst, vd, vm, false); 6517369Sgblack@eecs.umich.edu } else { 6527376Sgblack@eecs.umich.edu return decodeVfpRegRegOp<VsqrtD>( 6537376Sgblack@eecs.umich.edu machInst, vd, vm, true); 6547369Sgblack@eecs.umich.edu } 6557363Sgblack@eecs.umich.edu } 6567363Sgblack@eecs.umich.edu case 0x2: 6577363Sgblack@eecs.umich.edu case 0x3: 6587363Sgblack@eecs.umich.edu // Between half and single precision. 6597363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvtb, vcvtt", machInst); 6607363Sgblack@eecs.umich.edu case 0x4: 6617377Sgblack@eecs.umich.edu if (single) { 6627389Sgblack@eecs.umich.edu if (e) { 6637389Sgblack@eecs.umich.edu return new VcmpeS(machInst, vd, vm); 6647389Sgblack@eecs.umich.edu } else { 6657389Sgblack@eecs.umich.edu return new VcmpS(machInst, vd, vm); 6667389Sgblack@eecs.umich.edu } 6677377Sgblack@eecs.umich.edu } else { 6687389Sgblack@eecs.umich.edu if (e) { 6697389Sgblack@eecs.umich.edu return new VcmpeD(machInst, vd, vm); 6707389Sgblack@eecs.umich.edu } else { 6717389Sgblack@eecs.umich.edu return new VcmpD(machInst, vd, vm); 6727389Sgblack@eecs.umich.edu } 6737377Sgblack@eecs.umich.edu } 6747363Sgblack@eecs.umich.edu case 0x5: 6757377Sgblack@eecs.umich.edu if (single) { 6767389Sgblack@eecs.umich.edu if (e) { 6777389Sgblack@eecs.umich.edu return new VcmpeZeroS(machInst, vd, 0); 6787389Sgblack@eecs.umich.edu } else { 6797389Sgblack@eecs.umich.edu return new VcmpZeroS(machInst, vd, 0); 6807389Sgblack@eecs.umich.edu } 6817377Sgblack@eecs.umich.edu } else { 6827389Sgblack@eecs.umich.edu if (e) { 6837389Sgblack@eecs.umich.edu return new VcmpeZeroD(machInst, vd, 0); 6847389Sgblack@eecs.umich.edu } else { 6857389Sgblack@eecs.umich.edu return new VcmpZeroD(machInst, vd, 0); 6867389Sgblack@eecs.umich.edu } 6877377Sgblack@eecs.umich.edu } 6887363Sgblack@eecs.umich.edu case 0x7: 6897363Sgblack@eecs.umich.edu if (opc3 == 0x3) { 6907374Sgblack@eecs.umich.edu if (single) { 6917374Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 6927374Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 6937374Sgblack@eecs.umich.edu return new VcvtFpSFpD(machInst, vd, vm); 6947374Sgblack@eecs.umich.edu } else { 6957374Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 6967374Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 6977374Sgblack@eecs.umich.edu return new VcvtFpDFpS(machInst, vd, vm); 6987374Sgblack@eecs.umich.edu } 6997363Sgblack@eecs.umich.edu } 7007363Sgblack@eecs.umich.edu break; 7017363Sgblack@eecs.umich.edu case 0x8: 7027373Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 7037373Sgblack@eecs.umich.edu if (single) { 7047373Sgblack@eecs.umich.edu return new VcvtUIntFpS(machInst, vd, vm); 7057373Sgblack@eecs.umich.edu } else { 7067373Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 7077373Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 7087373Sgblack@eecs.umich.edu return new VcvtUIntFpD(machInst, vd, vm); 7097373Sgblack@eecs.umich.edu } 7107373Sgblack@eecs.umich.edu } else { 7117373Sgblack@eecs.umich.edu if (single) { 7127373Sgblack@eecs.umich.edu return new VcvtSIntFpS(machInst, vd, vm); 7137373Sgblack@eecs.umich.edu } else { 7147373Sgblack@eecs.umich.edu vm = (IntRegIndex)(bits(machInst, 5) | 7157373Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1)); 7167373Sgblack@eecs.umich.edu return new VcvtSIntFpD(machInst, vd, vm); 7177373Sgblack@eecs.umich.edu } 7187373Sgblack@eecs.umich.edu } 7197363Sgblack@eecs.umich.edu case 0xa: 7207379Sgblack@eecs.umich.edu { 7217379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 7227379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 7237379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 7247379Sgblack@eecs.umich.edu const uint32_t size = 7257379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 7267379Sgblack@eecs.umich.edu if (single) { 7277379Sgblack@eecs.umich.edu if (half) { 7287379Sgblack@eecs.umich.edu return new VcvtSHFixedFpS(machInst, vd, vd, size); 7297379Sgblack@eecs.umich.edu } else { 7307379Sgblack@eecs.umich.edu return new VcvtSFixedFpS(machInst, vd, vd, size); 7317379Sgblack@eecs.umich.edu } 7327379Sgblack@eecs.umich.edu } else { 7337379Sgblack@eecs.umich.edu if (half) { 7347379Sgblack@eecs.umich.edu return new VcvtSHFixedFpD(machInst, vd, vd, size); 7357379Sgblack@eecs.umich.edu } else { 7367379Sgblack@eecs.umich.edu return new VcvtSFixedFpD(machInst, vd, vd, size); 7377379Sgblack@eecs.umich.edu } 7387379Sgblack@eecs.umich.edu } 7397379Sgblack@eecs.umich.edu } 7407363Sgblack@eecs.umich.edu case 0xb: 7417379Sgblack@eecs.umich.edu { 7427379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 7437379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 7447379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 7457379Sgblack@eecs.umich.edu const uint32_t size = 7467379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 7477379Sgblack@eecs.umich.edu if (single) { 7487379Sgblack@eecs.umich.edu if (half) { 7497379Sgblack@eecs.umich.edu return new VcvtUHFixedFpS(machInst, vd, vd, size); 7507379Sgblack@eecs.umich.edu } else { 7517379Sgblack@eecs.umich.edu return new VcvtUFixedFpS(machInst, vd, vd, size); 7527379Sgblack@eecs.umich.edu } 7537379Sgblack@eecs.umich.edu } else { 7547379Sgblack@eecs.umich.edu if (half) { 7557379Sgblack@eecs.umich.edu return new VcvtUHFixedFpD(machInst, vd, vd, size); 7567379Sgblack@eecs.umich.edu } else { 7577379Sgblack@eecs.umich.edu return new VcvtUFixedFpD(machInst, vd, vd, size); 7587379Sgblack@eecs.umich.edu } 7597379Sgblack@eecs.umich.edu } 7607379Sgblack@eecs.umich.edu } 7617363Sgblack@eecs.umich.edu case 0xc: 7627380Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 7637380Sgblack@eecs.umich.edu if (single) { 7647380Sgblack@eecs.umich.edu return new VcvtFpUIntSR(machInst, vd, vm); 7657380Sgblack@eecs.umich.edu } else { 7667380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 7677380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 7687380Sgblack@eecs.umich.edu return new VcvtFpUIntDR(machInst, vd, vm); 7697380Sgblack@eecs.umich.edu } 7707373Sgblack@eecs.umich.edu } else { 7717380Sgblack@eecs.umich.edu if (single) { 7727380Sgblack@eecs.umich.edu return new VcvtFpUIntS(machInst, vd, vm); 7737380Sgblack@eecs.umich.edu } else { 7747380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 7757380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 7767380Sgblack@eecs.umich.edu return new VcvtFpUIntD(machInst, vd, vm); 7777380Sgblack@eecs.umich.edu } 7787373Sgblack@eecs.umich.edu } 7797363Sgblack@eecs.umich.edu case 0xd: 7807380Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 7817380Sgblack@eecs.umich.edu if (single) { 7827380Sgblack@eecs.umich.edu return new VcvtFpSIntSR(machInst, vd, vm); 7837380Sgblack@eecs.umich.edu } else { 7847380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 7857380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 7867380Sgblack@eecs.umich.edu return new VcvtFpSIntDR(machInst, vd, vm); 7877380Sgblack@eecs.umich.edu } 7887373Sgblack@eecs.umich.edu } else { 7897380Sgblack@eecs.umich.edu if (single) { 7907380Sgblack@eecs.umich.edu return new VcvtFpSIntS(machInst, vd, vm); 7917380Sgblack@eecs.umich.edu } else { 7927380Sgblack@eecs.umich.edu vd = (IntRegIndex)(bits(machInst, 22) | 7937380Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1)); 7947380Sgblack@eecs.umich.edu return new VcvtFpSIntD(machInst, vd, vm); 7957380Sgblack@eecs.umich.edu } 7967373Sgblack@eecs.umich.edu } 7977363Sgblack@eecs.umich.edu case 0xe: 7987379Sgblack@eecs.umich.edu { 7997379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 8007379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 8017379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 8027379Sgblack@eecs.umich.edu const uint32_t size = 8037379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 8047379Sgblack@eecs.umich.edu if (single) { 8057379Sgblack@eecs.umich.edu if (half) { 8067379Sgblack@eecs.umich.edu return new VcvtFpSHFixedS(machInst, vd, vd, size); 8077379Sgblack@eecs.umich.edu } else { 8087379Sgblack@eecs.umich.edu return new VcvtFpSFixedS(machInst, vd, vd, size); 8097379Sgblack@eecs.umich.edu } 8107379Sgblack@eecs.umich.edu } else { 8117379Sgblack@eecs.umich.edu if (half) { 8127379Sgblack@eecs.umich.edu return new VcvtFpSHFixedD(machInst, vd, vd, size); 8137379Sgblack@eecs.umich.edu } else { 8147379Sgblack@eecs.umich.edu return new VcvtFpSFixedD(machInst, vd, vd, size); 8157379Sgblack@eecs.umich.edu } 8167379Sgblack@eecs.umich.edu } 8177379Sgblack@eecs.umich.edu } 8187363Sgblack@eecs.umich.edu case 0xf: 8197379Sgblack@eecs.umich.edu { 8207379Sgblack@eecs.umich.edu const bool half = (bits(machInst, 7) == 0); 8217379Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 5) | 8227379Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 8237379Sgblack@eecs.umich.edu const uint32_t size = 8247379Sgblack@eecs.umich.edu (bits(machInst, 7) == 0 ? 16 : 32) - imm; 8257379Sgblack@eecs.umich.edu if (single) { 8267379Sgblack@eecs.umich.edu if (half) { 8277379Sgblack@eecs.umich.edu return new VcvtFpUHFixedS(machInst, vd, vd, size); 8287379Sgblack@eecs.umich.edu } else { 8297379Sgblack@eecs.umich.edu return new VcvtFpUFixedS(machInst, vd, vd, size); 8307379Sgblack@eecs.umich.edu } 8317379Sgblack@eecs.umich.edu } else { 8327379Sgblack@eecs.umich.edu if (half) { 8337379Sgblack@eecs.umich.edu return new VcvtFpUHFixedD(machInst, vd, vd, size); 8347379Sgblack@eecs.umich.edu } else { 8357379Sgblack@eecs.umich.edu return new VcvtFpUFixedD(machInst, vd, vd, size); 8367379Sgblack@eecs.umich.edu } 8377379Sgblack@eecs.umich.edu } 8387379Sgblack@eecs.umich.edu } 8397363Sgblack@eecs.umich.edu } 8407363Sgblack@eecs.umich.edu break; 8417363Sgblack@eecs.umich.edu } 8427363Sgblack@eecs.umich.edu return new Unknown(machInst); 8437363Sgblack@eecs.umich.edu } 8447363Sgblack@eecs.umich.edu ''' 8457363Sgblack@eecs.umich.edu}}; 8467363Sgblack@eecs.umich.edu 8477363Sgblack@eecs.umich.edudef format VfpData() {{ 8487363Sgblack@eecs.umich.edu decode_block = ''' 8497363Sgblack@eecs.umich.edu return decodeVfpData(machInst); 8507363Sgblack@eecs.umich.edu ''' 8517363Sgblack@eecs.umich.edu}}; 852