fp.isa revision 7368
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 37178Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47178Sgblack@eecs.umich.edu// All rights reserved 57178Sgblack@eecs.umich.edu// 67178Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77178Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87178Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97178Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107178Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117178Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127178Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137178Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147178Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Floating Point operate instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 486019Shines@cs.fsu.edudef template FPAExecute {{ 496019Shines@cs.fsu.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 506019Shines@cs.fsu.edu { 516019Shines@cs.fsu.edu Fault fault = NoFault; 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edu %(fp_enable_check)s; 546019Shines@cs.fsu.edu 556019Shines@cs.fsu.edu %(op_decl)s; 566019Shines@cs.fsu.edu %(op_rd)s; 576019Shines@cs.fsu.edu 586243Sgblack@eecs.umich.edu if (%(predicate_test)s) { 596243Sgblack@eecs.umich.edu %(code)s; 606243Sgblack@eecs.umich.edu if (fault == NoFault) { 616243Sgblack@eecs.umich.edu %(op_wb)s; 626243Sgblack@eecs.umich.edu } 636019Shines@cs.fsu.edu } 646019Shines@cs.fsu.edu 656019Shines@cs.fsu.edu return fault; 666019Shines@cs.fsu.edu } 676019Shines@cs.fsu.edu}}; 686019Shines@cs.fsu.edu 696019Shines@cs.fsu.edudef template FloatDoubleDecode {{ 706019Shines@cs.fsu.edu { 716019Shines@cs.fsu.edu ArmStaticInst *i = NULL; 726019Shines@cs.fsu.edu switch (OPCODE_19 << 1 | OPCODE_7) 736019Shines@cs.fsu.edu { 746019Shines@cs.fsu.edu case 0: 756019Shines@cs.fsu.edu i = (ArmStaticInst *)new %(class_name)sS(machInst); 766019Shines@cs.fsu.edu break; 776019Shines@cs.fsu.edu case 1: 786019Shines@cs.fsu.edu i = (ArmStaticInst *)new %(class_name)sD(machInst); 796019Shines@cs.fsu.edu break; 806019Shines@cs.fsu.edu case 2: 816019Shines@cs.fsu.edu case 3: 826019Shines@cs.fsu.edu default: 836019Shines@cs.fsu.edu panic("Cannot decode float/double nature of the instruction"); 846019Shines@cs.fsu.edu } 856019Shines@cs.fsu.edu return i; 866019Shines@cs.fsu.edu } 876019Shines@cs.fsu.edu}}; 886019Shines@cs.fsu.edu 896019Shines@cs.fsu.edu// Primary format for float point operate instructions: 906019Shines@cs.fsu.edudef format FloatOp(code, *flags) {{ 916019Shines@cs.fsu.edu orig_code = code 926019Shines@cs.fsu.edu 936019Shines@cs.fsu.edu cblk = code 946252Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 956243Sgblack@eecs.umich.edu {"code": cblk, 966243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 976243Sgblack@eecs.umich.edu flags) 986019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 996019Shines@cs.fsu.edu decoder_output = BasicConstructor.subst(iop) 1006019Shines@cs.fsu.edu exec_output = FPAExecute.subst(iop) 1016019Shines@cs.fsu.edu 1026019Shines@cs.fsu.edu sng_cblk = code 1036252Sgblack@eecs.umich.edu sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1046243Sgblack@eecs.umich.edu {"code": sng_cblk, 1056243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1066243Sgblack@eecs.umich.edu flags) 1076019Shines@cs.fsu.edu header_output += BasicDeclare.subst(sng_iop) 1086019Shines@cs.fsu.edu decoder_output += BasicConstructor.subst(sng_iop) 1096019Shines@cs.fsu.edu exec_output += FPAExecute.subst(sng_iop) 1106019Shines@cs.fsu.edu 1116019Shines@cs.fsu.edu dbl_code = re.sub(r'\.sf', '.df', orig_code) 1126019Shines@cs.fsu.edu 1136019Shines@cs.fsu.edu dbl_cblk = dbl_code 1146252Sgblack@eecs.umich.edu dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1156243Sgblack@eecs.umich.edu {"code": dbl_cblk, 1166243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1176243Sgblack@eecs.umich.edu flags) 1186019Shines@cs.fsu.edu header_output += BasicDeclare.subst(dbl_iop) 1196019Shines@cs.fsu.edu decoder_output += BasicConstructor.subst(dbl_iop) 1206019Shines@cs.fsu.edu exec_output += FPAExecute.subst(dbl_iop) 1216019Shines@cs.fsu.edu 1226019Shines@cs.fsu.edu decode_block = FloatDoubleDecode.subst(iop) 1236019Shines@cs.fsu.edu}}; 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edulet {{ 1266019Shines@cs.fsu.edu calcFPCcCode = ''' 1276019Shines@cs.fsu.edu uint16_t _in, _iz, _ic, _iv; 1286019Shines@cs.fsu.edu 1296019Shines@cs.fsu.edu _in = %(fReg1)s < %(fReg2)s; 1306019Shines@cs.fsu.edu _iz = %(fReg1)s == %(fReg2)s; 1316019Shines@cs.fsu.edu _ic = %(fReg1)s >= %(fReg2)s; 1326019Shines@cs.fsu.edu _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 1336019Shines@cs.fsu.edu 1346724Sgblack@eecs.umich.edu CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 1356724Sgblack@eecs.umich.edu (CondCodes & 0x0FFFFFFF); 1366019Shines@cs.fsu.edu ''' 1376019Shines@cs.fsu.edu}}; 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edudef format FloatCmp(fReg1, fReg2, *flags) {{ 1406019Shines@cs.fsu.edu code = calcFPCcCode % vars() 1416252Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 1426243Sgblack@eecs.umich.edu {"code": code, 1436243Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1446243Sgblack@eecs.umich.edu flags) 1456019Shines@cs.fsu.edu header_output = BasicDeclare.subst(iop) 1466019Shines@cs.fsu.edu decoder_output = BasicConstructor.subst(iop) 1476019Shines@cs.fsu.edu decode_block = BasicDecode.subst(iop) 1486019Shines@cs.fsu.edu exec_output = FPAExecute.subst(iop) 1496019Shines@cs.fsu.edu}}; 1506019Shines@cs.fsu.edu 1517356Sgblack@eecs.umich.edulet {{ 1527356Sgblack@eecs.umich.edu header_output = ''' 1537356Sgblack@eecs.umich.edu StaticInstPtr 1547356Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst); 1557356Sgblack@eecs.umich.edu ''' 1567356Sgblack@eecs.umich.edu decoder_output = ''' 1577356Sgblack@eecs.umich.edu StaticInstPtr 1587356Sgblack@eecs.umich.edu decodeExtensionRegLoadStore(ExtMachInst machInst) 1597178Sgblack@eecs.umich.edu { 1607178Sgblack@eecs.umich.edu const uint32_t opcode = bits(machInst, 24, 20); 1617178Sgblack@eecs.umich.edu const uint32_t offset = bits(machInst, 7, 0); 1627337Sgblack@eecs.umich.edu const bool single = (bits(machInst, 8) == 0); 1637178Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1647178Sgblack@eecs.umich.edu RegIndex vd; 1657178Sgblack@eecs.umich.edu if (single) { 1667178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1677178Sgblack@eecs.umich.edu bits(machInst, 22)); 1687178Sgblack@eecs.umich.edu } else { 1697178Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 1707178Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 1717178Sgblack@eecs.umich.edu } 1727178Sgblack@eecs.umich.edu switch (bits(opcode, 4, 3)) { 1737178Sgblack@eecs.umich.edu case 0x0: 1747335Sgblack@eecs.umich.edu if (bits(opcode, 4, 1) == 0x2 && 1757335Sgblack@eecs.umich.edu !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 1767335Sgblack@eecs.umich.edu !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 1777335Sgblack@eecs.umich.edu if ((bits(machInst, 7, 4) & 0xd) != 1) { 1787335Sgblack@eecs.umich.edu break; 1797335Sgblack@eecs.umich.edu } 1807335Sgblack@eecs.umich.edu const IntRegIndex rt = 1817335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1827335Sgblack@eecs.umich.edu const IntRegIndex rt2 = 1837335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1847335Sgblack@eecs.umich.edu const bool op = bits(machInst, 20); 1857335Sgblack@eecs.umich.edu uint32_t vm; 1867337Sgblack@eecs.umich.edu if (single) { 1877335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 1887335Sgblack@eecs.umich.edu } else { 1897335Sgblack@eecs.umich.edu vm = (bits(machInst, 3, 0) << 1) | 1907335Sgblack@eecs.umich.edu (bits(machInst, 5) << 5); 1917335Sgblack@eecs.umich.edu } 1927335Sgblack@eecs.umich.edu if (op) { 1937335Sgblack@eecs.umich.edu return new Vmov2Core2Reg(machInst, rt, rt2, 1947335Sgblack@eecs.umich.edu (IntRegIndex)vm); 1957335Sgblack@eecs.umich.edu } else { 1967335Sgblack@eecs.umich.edu return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 1977335Sgblack@eecs.umich.edu rt, rt2); 1987335Sgblack@eecs.umich.edu } 1997178Sgblack@eecs.umich.edu } 2007178Sgblack@eecs.umich.edu break; 2017178Sgblack@eecs.umich.edu case 0x1: 2027178Sgblack@eecs.umich.edu switch (bits(opcode, 1, 0)) { 2037178Sgblack@eecs.umich.edu case 0x0: 2047178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2057178Sgblack@eecs.umich.edu true, false, false, offset); 2067178Sgblack@eecs.umich.edu case 0x1: 2077178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2087178Sgblack@eecs.umich.edu true, false, true, offset); 2097178Sgblack@eecs.umich.edu case 0x2: 2107178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2117178Sgblack@eecs.umich.edu true, true, false, offset); 2127178Sgblack@eecs.umich.edu case 0x3: 2137178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpop. 2147178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2157178Sgblack@eecs.umich.edu true, true, true, offset); 2167178Sgblack@eecs.umich.edu } 2177178Sgblack@eecs.umich.edu case 0x2: 2187178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x2) { 2197178Sgblack@eecs.umich.edu // If rn == sp, then this is called vpush. 2207178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2217178Sgblack@eecs.umich.edu false, true, false, offset); 2227178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x3) { 2237178Sgblack@eecs.umich.edu return new VLdmStm(machInst, rn, vd, single, 2247178Sgblack@eecs.umich.edu false, true, true, offset); 2257178Sgblack@eecs.umich.edu } 2267178Sgblack@eecs.umich.edu // Fall through on purpose 2277178Sgblack@eecs.umich.edu case 0x3: 2287346Sgblack@eecs.umich.edu const bool up = (bits(machInst, 23) == 1); 2297346Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) << 2; 2307346Sgblack@eecs.umich.edu RegIndex vd; 2317346Sgblack@eecs.umich.edu if (single) { 2327346Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2337346Sgblack@eecs.umich.edu (bits(machInst, 22))); 2347346Sgblack@eecs.umich.edu } else { 2357346Sgblack@eecs.umich.edu vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 2367346Sgblack@eecs.umich.edu (bits(machInst, 22) << 5)); 2377346Sgblack@eecs.umich.edu } 2387178Sgblack@eecs.umich.edu if (bits(opcode, 1, 0) == 0x0) { 2397346Sgblack@eecs.umich.edu if (single) { 2407346Sgblack@eecs.umich.edu if (up) { 2417346Sgblack@eecs.umich.edu return new %(vstr_us)s(machInst, vd, rn, up, imm); 2427346Sgblack@eecs.umich.edu } else { 2437346Sgblack@eecs.umich.edu return new %(vstr_s)s(machInst, vd, rn, up, imm); 2447346Sgblack@eecs.umich.edu } 2457346Sgblack@eecs.umich.edu } else { 2467346Sgblack@eecs.umich.edu if (up) { 2477346Sgblack@eecs.umich.edu return new %(vstr_ud)s(machInst, vd, vd + 1, 2487346Sgblack@eecs.umich.edu rn, up, imm); 2497346Sgblack@eecs.umich.edu } else { 2507346Sgblack@eecs.umich.edu return new %(vstr_d)s(machInst, vd, vd + 1, 2517346Sgblack@eecs.umich.edu rn, up, imm); 2527346Sgblack@eecs.umich.edu } 2537346Sgblack@eecs.umich.edu } 2547178Sgblack@eecs.umich.edu } else if (bits(opcode, 1, 0) == 0x1) { 2557337Sgblack@eecs.umich.edu if (single) { 2567337Sgblack@eecs.umich.edu if (up) { 2577337Sgblack@eecs.umich.edu return new %(vldr_us)s(machInst, vd, rn, up, imm); 2587337Sgblack@eecs.umich.edu } else { 2597337Sgblack@eecs.umich.edu return new %(vldr_s)s(machInst, vd, rn, up, imm); 2607337Sgblack@eecs.umich.edu } 2617337Sgblack@eecs.umich.edu } else { 2627337Sgblack@eecs.umich.edu if (up) { 2637337Sgblack@eecs.umich.edu return new %(vldr_ud)s(machInst, vd, vd + 1, 2647337Sgblack@eecs.umich.edu rn, up, imm); 2657337Sgblack@eecs.umich.edu } else { 2667337Sgblack@eecs.umich.edu return new %(vldr_d)s(machInst, vd, vd + 1, 2677337Sgblack@eecs.umich.edu rn, up, imm); 2687337Sgblack@eecs.umich.edu } 2697337Sgblack@eecs.umich.edu } 2707178Sgblack@eecs.umich.edu } 2717178Sgblack@eecs.umich.edu } 2727178Sgblack@eecs.umich.edu return new Unknown(machInst); 2737178Sgblack@eecs.umich.edu } 2747337Sgblack@eecs.umich.edu ''' % { 2757337Sgblack@eecs.umich.edu "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 2767337Sgblack@eecs.umich.edu "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 2777337Sgblack@eecs.umich.edu "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 2787346Sgblack@eecs.umich.edu "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 2797346Sgblack@eecs.umich.edu "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 2807346Sgblack@eecs.umich.edu "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 2817346Sgblack@eecs.umich.edu "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 2827346Sgblack@eecs.umich.edu "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 2837337Sgblack@eecs.umich.edu } 2847178Sgblack@eecs.umich.edu}}; 2857321Sgblack@eecs.umich.edu 2867356Sgblack@eecs.umich.edudef format ExtensionRegLoadStore() {{ 2877321Sgblack@eecs.umich.edu decode_block = ''' 2887356Sgblack@eecs.umich.edu return decodeExtensionRegLoadStore(machInst); 2897356Sgblack@eecs.umich.edu ''' 2907356Sgblack@eecs.umich.edu}}; 2917356Sgblack@eecs.umich.edu 2927356Sgblack@eecs.umich.edulet {{ 2937356Sgblack@eecs.umich.edu header_output = ''' 2947356Sgblack@eecs.umich.edu StaticInstPtr 2957356Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst); 2967356Sgblack@eecs.umich.edu ''' 2977356Sgblack@eecs.umich.edu decoder_output = ''' 2987356Sgblack@eecs.umich.edu StaticInstPtr 2997356Sgblack@eecs.umich.edu decodeShortFpTransfer(ExtMachInst machInst) 3007321Sgblack@eecs.umich.edu { 3017321Sgblack@eecs.umich.edu const uint32_t l = bits(machInst, 20); 3027321Sgblack@eecs.umich.edu const uint32_t c = bits(machInst, 8); 3037321Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 23, 21); 3047321Sgblack@eecs.umich.edu const uint32_t b = bits(machInst, 6, 5); 3057321Sgblack@eecs.umich.edu if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 3067321Sgblack@eecs.umich.edu (machInst.thumb == 0 && machInst.condCode == 0xf)) { 3077321Sgblack@eecs.umich.edu return new Unknown(machInst); 3087321Sgblack@eecs.umich.edu } 3097321Sgblack@eecs.umich.edu if (l == 0 && c == 0) { 3107321Sgblack@eecs.umich.edu if (a == 0) { 3117335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3127335Sgblack@eecs.umich.edu bits(machInst, 7); 3137335Sgblack@eecs.umich.edu const IntRegIndex rt = 3147335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3157335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3167335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3177335Sgblack@eecs.umich.edu } else { 3187335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3197335Sgblack@eecs.umich.edu } 3207321Sgblack@eecs.umich.edu } else if (a == 0x7) { 3217323Sgblack@eecs.umich.edu const IntRegIndex rt = 3227323Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3237323Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3247323Sgblack@eecs.umich.edu switch (specReg) { 3257323Sgblack@eecs.umich.edu case 0: 3267323Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3277323Sgblack@eecs.umich.edu break; 3287323Sgblack@eecs.umich.edu case 1: 3297323Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3307323Sgblack@eecs.umich.edu break; 3317323Sgblack@eecs.umich.edu case 8: 3327323Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 3337323Sgblack@eecs.umich.edu break; 3347323Sgblack@eecs.umich.edu default: 3357323Sgblack@eecs.umich.edu return new Unknown(machInst); 3367323Sgblack@eecs.umich.edu } 3377323Sgblack@eecs.umich.edu return new Vmsr(machInst, (IntRegIndex)specReg, rt); 3387321Sgblack@eecs.umich.edu } 3397321Sgblack@eecs.umich.edu } else if (l == 0 && c == 1) { 3407321Sgblack@eecs.umich.edu if (bits(a, 2) == 0) { 3417335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 3427335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 3437335Sgblack@eecs.umich.edu uint32_t index, size; 3447335Sgblack@eecs.umich.edu const IntRegIndex rt = 3457335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3467335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 3477335Sgblack@eecs.umich.edu size = 8; 3487335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 3497335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 3507335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 3517335Sgblack@eecs.umich.edu size = 16; 3527335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 3537335Sgblack@eecs.umich.edu bits(machInst, 6); 3547335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0) { 3557335Sgblack@eecs.umich.edu size = 32; 3567335Sgblack@eecs.umich.edu index = bits(machInst, 21); 3577335Sgblack@eecs.umich.edu } else { 3587335Sgblack@eecs.umich.edu return new Unknown(machInst); 3597335Sgblack@eecs.umich.edu } 3607335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 3617335Sgblack@eecs.umich.edu index -= (32 / size); 3627335Sgblack@eecs.umich.edu vd++; 3637335Sgblack@eecs.umich.edu } 3647335Sgblack@eecs.umich.edu switch (size) { 3657335Sgblack@eecs.umich.edu case 8: 3667335Sgblack@eecs.umich.edu return new VmovCoreRegB(machInst, (IntRegIndex)vd, 3677335Sgblack@eecs.umich.edu rt, index); 3687335Sgblack@eecs.umich.edu case 16: 3697335Sgblack@eecs.umich.edu return new VmovCoreRegH(machInst, (IntRegIndex)vd, 3707335Sgblack@eecs.umich.edu rt, index); 3717335Sgblack@eecs.umich.edu case 32: 3727335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 3737335Sgblack@eecs.umich.edu } 3747321Sgblack@eecs.umich.edu } else if (bits(b, 1) == 0) { 3757321Sgblack@eecs.umich.edu // A8-594 3767321Sgblack@eecs.umich.edu return new WarnUnimplemented("vdup", machInst); 3777321Sgblack@eecs.umich.edu } 3787321Sgblack@eecs.umich.edu } else if (l == 1 && c == 0) { 3797321Sgblack@eecs.umich.edu if (a == 0) { 3807335Sgblack@eecs.umich.edu const uint32_t vn = (bits(machInst, 19, 16) << 1) | 3817335Sgblack@eecs.umich.edu bits(machInst, 7); 3827335Sgblack@eecs.umich.edu const IntRegIndex rt = 3837335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3847335Sgblack@eecs.umich.edu if (bits(machInst, 20) == 1) { 3857335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 3867335Sgblack@eecs.umich.edu } else { 3877335Sgblack@eecs.umich.edu return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 3887335Sgblack@eecs.umich.edu } 3897321Sgblack@eecs.umich.edu } else if (a == 7) { 3907326Sgblack@eecs.umich.edu const IntRegIndex rt = 3917326Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3927326Sgblack@eecs.umich.edu uint32_t specReg = bits(machInst, 19, 16); 3937326Sgblack@eecs.umich.edu switch (specReg) { 3947326Sgblack@eecs.umich.edu case 0: 3957326Sgblack@eecs.umich.edu specReg = MISCREG_FPSID; 3967326Sgblack@eecs.umich.edu break; 3977326Sgblack@eecs.umich.edu case 1: 3987326Sgblack@eecs.umich.edu specReg = MISCREG_FPSCR; 3997326Sgblack@eecs.umich.edu break; 4007326Sgblack@eecs.umich.edu case 6: 4017326Sgblack@eecs.umich.edu specReg = MISCREG_MVFR1; 4027326Sgblack@eecs.umich.edu break; 4037326Sgblack@eecs.umich.edu case 7: 4047326Sgblack@eecs.umich.edu specReg = MISCREG_MVFR0; 4057326Sgblack@eecs.umich.edu break; 4067326Sgblack@eecs.umich.edu case 8: 4077326Sgblack@eecs.umich.edu specReg = MISCREG_FPEXC; 4087326Sgblack@eecs.umich.edu break; 4097326Sgblack@eecs.umich.edu default: 4107326Sgblack@eecs.umich.edu return new Unknown(machInst); 4117326Sgblack@eecs.umich.edu } 4127326Sgblack@eecs.umich.edu return new Vmrs(machInst, rt, (IntRegIndex)specReg); 4137321Sgblack@eecs.umich.edu } 4147321Sgblack@eecs.umich.edu } else { 4157335Sgblack@eecs.umich.edu uint32_t vd = (bits(machInst, 7) << 5) | 4167335Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 4177335Sgblack@eecs.umich.edu uint32_t index, size; 4187335Sgblack@eecs.umich.edu const IntRegIndex rt = 4197335Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 4207335Sgblack@eecs.umich.edu const bool u = (bits(machInst, 23) == 1); 4217335Sgblack@eecs.umich.edu if (bits(machInst, 22) == 1) { 4227335Sgblack@eecs.umich.edu size = 8; 4237335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 2) | 4247335Sgblack@eecs.umich.edu bits(machInst, 6, 5); 4257335Sgblack@eecs.umich.edu } else if (bits(machInst, 5) == 1) { 4267335Sgblack@eecs.umich.edu size = 16; 4277335Sgblack@eecs.umich.edu index = (bits(machInst, 21) << 1) | 4287335Sgblack@eecs.umich.edu bits(machInst, 6); 4297335Sgblack@eecs.umich.edu } else if (bits(machInst, 6) == 0 && !u) { 4307335Sgblack@eecs.umich.edu size = 32; 4317335Sgblack@eecs.umich.edu index = bits(machInst, 21); 4327335Sgblack@eecs.umich.edu } else { 4337335Sgblack@eecs.umich.edu return new Unknown(machInst); 4347335Sgblack@eecs.umich.edu } 4357335Sgblack@eecs.umich.edu if (index >= (32 / size)) { 4367335Sgblack@eecs.umich.edu index -= (32 / size); 4377335Sgblack@eecs.umich.edu vd++; 4387335Sgblack@eecs.umich.edu } 4397335Sgblack@eecs.umich.edu switch (size) { 4407335Sgblack@eecs.umich.edu case 8: 4417335Sgblack@eecs.umich.edu if (u) { 4427335Sgblack@eecs.umich.edu return new VmovRegCoreUB(machInst, rt, 4437335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4447335Sgblack@eecs.umich.edu } else { 4457335Sgblack@eecs.umich.edu return new VmovRegCoreSB(machInst, rt, 4467335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4477335Sgblack@eecs.umich.edu } 4487335Sgblack@eecs.umich.edu case 16: 4497335Sgblack@eecs.umich.edu if (u) { 4507335Sgblack@eecs.umich.edu return new VmovRegCoreUH(machInst, rt, 4517335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4527335Sgblack@eecs.umich.edu } else { 4537335Sgblack@eecs.umich.edu return new VmovRegCoreSH(machInst, rt, 4547335Sgblack@eecs.umich.edu (IntRegIndex)vd, index); 4557335Sgblack@eecs.umich.edu } 4567335Sgblack@eecs.umich.edu case 32: 4577335Sgblack@eecs.umich.edu return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 4587335Sgblack@eecs.umich.edu } 4597321Sgblack@eecs.umich.edu } 4607321Sgblack@eecs.umich.edu return new Unknown(machInst); 4617321Sgblack@eecs.umich.edu } 4627321Sgblack@eecs.umich.edu ''' 4637321Sgblack@eecs.umich.edu}}; 4647356Sgblack@eecs.umich.edu 4657356Sgblack@eecs.umich.edudef format ShortFpTransfer() {{ 4667356Sgblack@eecs.umich.edu decode_block = ''' 4677356Sgblack@eecs.umich.edu return decodeShortFpTransfer(machInst); 4687356Sgblack@eecs.umich.edu ''' 4697356Sgblack@eecs.umich.edu}}; 4707363Sgblack@eecs.umich.edu 4717363Sgblack@eecs.umich.edulet {{ 4727363Sgblack@eecs.umich.edu header_output = ''' 4737363Sgblack@eecs.umich.edu StaticInstPtr 4747363Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst); 4757363Sgblack@eecs.umich.edu ''' 4767363Sgblack@eecs.umich.edu decoder_output = ''' 4777363Sgblack@eecs.umich.edu StaticInstPtr 4787363Sgblack@eecs.umich.edu decodeVfpData(ExtMachInst machInst) 4797363Sgblack@eecs.umich.edu { 4807363Sgblack@eecs.umich.edu const uint32_t opc1 = bits(machInst, 23, 20); 4817363Sgblack@eecs.umich.edu const uint32_t opc2 = bits(machInst, 19, 16); 4827363Sgblack@eecs.umich.edu const uint32_t opc3 = bits(machInst, 7, 6); 4837363Sgblack@eecs.umich.edu //const uint32_t opc4 = bits(machInst, 3, 0); 4847363Sgblack@eecs.umich.edu switch (opc1 & 0xb /* 1011 */) { 4857363Sgblack@eecs.umich.edu case 0x0: 4867363Sgblack@eecs.umich.edu return new WarnUnimplemented("vmla, vmls", machInst); 4877363Sgblack@eecs.umich.edu case 0x2: 4887363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 4897364Sgblack@eecs.umich.edu uint32_t vd; 4907364Sgblack@eecs.umich.edu uint32_t vm; 4917364Sgblack@eecs.umich.edu uint32_t vn; 4927364Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 4937364Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 4947364Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 4957364Sgblack@eecs.umich.edu vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); 4967364Sgblack@eecs.umich.edu return new VmulS(machInst, (IntRegIndex)vd, 4977364Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 4987364Sgblack@eecs.umich.edu } else { 4997364Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5007364Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5017364Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5027364Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5037364Sgblack@eecs.umich.edu vn = (bits(machInst, 7) << 5) | 5047364Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 5057364Sgblack@eecs.umich.edu return new VmulD(machInst, (IntRegIndex)vd, 5067364Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5077364Sgblack@eecs.umich.edu } 5087363Sgblack@eecs.umich.edu } 5097363Sgblack@eecs.umich.edu case 0x1: 5107363Sgblack@eecs.umich.edu return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst); 5117363Sgblack@eecs.umich.edu case 0x3: 5127363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5137367Sgblack@eecs.umich.edu uint32_t vd; 5147367Sgblack@eecs.umich.edu uint32_t vm; 5157367Sgblack@eecs.umich.edu uint32_t vn; 5167367Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5177367Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5187367Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5197367Sgblack@eecs.umich.edu vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); 5207367Sgblack@eecs.umich.edu return new VaddS(machInst, (IntRegIndex)vd, 5217367Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5227367Sgblack@eecs.umich.edu } else { 5237367Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5247367Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5257367Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5267367Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5277367Sgblack@eecs.umich.edu vn = (bits(machInst, 7) << 5) | 5287367Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 5297367Sgblack@eecs.umich.edu return new VaddD(machInst, (IntRegIndex)vd, 5307367Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5317367Sgblack@eecs.umich.edu } 5327363Sgblack@eecs.umich.edu } else { 5337368Sgblack@eecs.umich.edu uint32_t vd; 5347368Sgblack@eecs.umich.edu uint32_t vm; 5357368Sgblack@eecs.umich.edu uint32_t vn; 5367368Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5377368Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5387368Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5397368Sgblack@eecs.umich.edu vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1); 5407368Sgblack@eecs.umich.edu return new VsubS(machInst, (IntRegIndex)vd, 5417368Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5427368Sgblack@eecs.umich.edu } else { 5437368Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5447368Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5457368Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5467368Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5477368Sgblack@eecs.umich.edu vn = (bits(machInst, 7) << 5) | 5487368Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 1); 5497368Sgblack@eecs.umich.edu return new VsubD(machInst, (IntRegIndex)vd, 5507368Sgblack@eecs.umich.edu (IntRegIndex)vn, (IntRegIndex)vm); 5517368Sgblack@eecs.umich.edu } 5527363Sgblack@eecs.umich.edu } 5537363Sgblack@eecs.umich.edu case 0x8: 5547363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5557363Sgblack@eecs.umich.edu return new WarnUnimplemented("vdiv", machInst); 5567363Sgblack@eecs.umich.edu } 5577363Sgblack@eecs.umich.edu break; 5587363Sgblack@eecs.umich.edu case 0xb: 5597363Sgblack@eecs.umich.edu if ((opc3 & 0x1) == 0) { 5607363Sgblack@eecs.umich.edu uint32_t vd; 5617363Sgblack@eecs.umich.edu const uint32_t baseImm = 5627363Sgblack@eecs.umich.edu bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4); 5637363Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5647363Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5657363Sgblack@eecs.umich.edu uint32_t imm = vfp_modified_imm(baseImm, false); 5667363Sgblack@eecs.umich.edu return new VmovImmS(machInst, (IntRegIndex)vd, imm); 5677363Sgblack@eecs.umich.edu } else { 5687363Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5697363Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5707363Sgblack@eecs.umich.edu uint64_t imm = vfp_modified_imm(baseImm, true); 5717363Sgblack@eecs.umich.edu return new VmovImmD(machInst, (IntRegIndex)vd, imm); 5727363Sgblack@eecs.umich.edu } 5737363Sgblack@eecs.umich.edu } 5747363Sgblack@eecs.umich.edu switch (opc2) { 5757363Sgblack@eecs.umich.edu case 0x0: 5767363Sgblack@eecs.umich.edu if (opc3 == 1) { 5777363Sgblack@eecs.umich.edu uint32_t vd; 5787363Sgblack@eecs.umich.edu uint32_t vm; 5797363Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5807363Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5817363Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5827363Sgblack@eecs.umich.edu return new VmovRegS(machInst, 5837363Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 5847363Sgblack@eecs.umich.edu } else { 5857363Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 5867363Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 5877363Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 5887363Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 5897363Sgblack@eecs.umich.edu return new VmovRegD(machInst, 5907363Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 5917363Sgblack@eecs.umich.edu } 5927363Sgblack@eecs.umich.edu } else { 5937366Sgblack@eecs.umich.edu uint32_t vd; 5947366Sgblack@eecs.umich.edu uint32_t vm; 5957366Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 5967366Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 5977366Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 5987366Sgblack@eecs.umich.edu return new VabsS(machInst, 5997366Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 6007366Sgblack@eecs.umich.edu } else { 6017366Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 6027366Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 6037366Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 6047366Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 6057366Sgblack@eecs.umich.edu return new VabsD(machInst, 6067366Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 6077366Sgblack@eecs.umich.edu } 6087363Sgblack@eecs.umich.edu } 6097363Sgblack@eecs.umich.edu case 0x1: 6107363Sgblack@eecs.umich.edu if (opc3 == 1) { 6117365Sgblack@eecs.umich.edu uint32_t vd; 6127365Sgblack@eecs.umich.edu uint32_t vm; 6137365Sgblack@eecs.umich.edu if (bits(machInst, 8) == 0) { 6147365Sgblack@eecs.umich.edu vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1); 6157365Sgblack@eecs.umich.edu vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1); 6167365Sgblack@eecs.umich.edu return new VnegS(machInst, 6177365Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 6187365Sgblack@eecs.umich.edu } else { 6197365Sgblack@eecs.umich.edu vd = (bits(machInst, 22) << 5) | 6207365Sgblack@eecs.umich.edu (bits(machInst, 15, 12) << 1); 6217365Sgblack@eecs.umich.edu vm = (bits(machInst, 5) << 5) | 6227365Sgblack@eecs.umich.edu (bits(machInst, 3, 0) << 1); 6237365Sgblack@eecs.umich.edu return new VnegD(machInst, 6247365Sgblack@eecs.umich.edu (IntRegIndex)vd, (IntRegIndex)vm); 6257365Sgblack@eecs.umich.edu } 6267363Sgblack@eecs.umich.edu } else { 6277363Sgblack@eecs.umich.edu return new WarnUnimplemented("vsqrt", machInst); 6287363Sgblack@eecs.umich.edu } 6297363Sgblack@eecs.umich.edu case 0x2: 6307363Sgblack@eecs.umich.edu case 0x3: 6317363Sgblack@eecs.umich.edu // Between half and single precision. 6327363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvtb, vcvtt", machInst); 6337363Sgblack@eecs.umich.edu case 0x4: 6347363Sgblack@eecs.umich.edu case 0x5: 6357363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcmp, vcmpe", machInst); 6367363Sgblack@eecs.umich.edu case 0x7: 6377363Sgblack@eecs.umich.edu if (opc3 == 0x3) { 6387363Sgblack@eecs.umich.edu // Between double and single precision. 6397363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt", machInst); 6407363Sgblack@eecs.umich.edu } 6417363Sgblack@eecs.umich.edu break; 6427363Sgblack@eecs.umich.edu case 0x8: 6437363Sgblack@eecs.umich.edu // Between FP and int. 6447363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt, vcvtr", machInst); 6457363Sgblack@eecs.umich.edu case 0xa: 6467363Sgblack@eecs.umich.edu case 0xb: 6477363Sgblack@eecs.umich.edu // Between FP and fixed point. 6487363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt", machInst); 6497363Sgblack@eecs.umich.edu case 0xc: 6507363Sgblack@eecs.umich.edu case 0xd: 6517363Sgblack@eecs.umich.edu // Between FP and int. 6527363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt, vcvtr", machInst); 6537363Sgblack@eecs.umich.edu case 0xe: 6547363Sgblack@eecs.umich.edu case 0xf: 6557363Sgblack@eecs.umich.edu // Between FP and fixed point. 6567363Sgblack@eecs.umich.edu return new WarnUnimplemented("vcvt", machInst); 6577363Sgblack@eecs.umich.edu } 6587363Sgblack@eecs.umich.edu break; 6597363Sgblack@eecs.umich.edu } 6607363Sgblack@eecs.umich.edu return new Unknown(machInst); 6617363Sgblack@eecs.umich.edu } 6627363Sgblack@eecs.umich.edu ''' 6637363Sgblack@eecs.umich.edu}}; 6647363Sgblack@eecs.umich.edu 6657363Sgblack@eecs.umich.edudef format VfpData() {{ 6667363Sgblack@eecs.umich.edu decode_block = ''' 6677363Sgblack@eecs.umich.edu return decodeVfpData(machInst); 6687363Sgblack@eecs.umich.edu ''' 6697363Sgblack@eecs.umich.edu}}; 670