fp.isa revision 7356
13536Sgblack@eecs.umich.edu// -*- mode:c++ -*- 23536Sgblack@eecs.umich.edu 33536Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 43536Sgblack@eecs.umich.edu// All rights reserved 53536Sgblack@eecs.umich.edu// 63536Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 73536Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 83536Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 93536Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 103536Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 113536Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 123536Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 133536Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 143536Sgblack@eecs.umich.edu// 153536Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 163536Sgblack@eecs.umich.edu// All rights reserved. 173536Sgblack@eecs.umich.edu// 183536Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 193536Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 203536Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 213536Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 223536Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 233536Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 243536Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 253536Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 263536Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 273536Sgblack@eecs.umich.edu// this software without specific prior written permission. 283536Sgblack@eecs.umich.edu// 293536Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303536Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313536Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323536Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333536Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343536Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353536Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363536Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373536Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383536Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393536Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403536Sgblack@eecs.umich.edu// 413536Sgblack@eecs.umich.edu// Authors: Stephen Hines 423536Sgblack@eecs.umich.edu 433536Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 443536Sgblack@eecs.umich.edu// 453536Sgblack@eecs.umich.edu// Floating Point operate instructions 463536Sgblack@eecs.umich.edu// 473536Sgblack@eecs.umich.edu 483536Sgblack@eecs.umich.edudef template FPAExecute {{ 493536Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 503536Sgblack@eecs.umich.edu { 513536Sgblack@eecs.umich.edu Fault fault = NoFault; 523536Sgblack@eecs.umich.edu 533536Sgblack@eecs.umich.edu %(fp_enable_check)s; 543536Sgblack@eecs.umich.edu 553536Sgblack@eecs.umich.edu %(op_decl)s; 563536Sgblack@eecs.umich.edu %(op_rd)s; 573536Sgblack@eecs.umich.edu 583536Sgblack@eecs.umich.edu if (%(predicate_test)s) { 593536Sgblack@eecs.umich.edu %(code)s; 603536Sgblack@eecs.umich.edu if (fault == NoFault) { 613536Sgblack@eecs.umich.edu %(op_wb)s; 623536Sgblack@eecs.umich.edu } 633536Sgblack@eecs.umich.edu } 643536Sgblack@eecs.umich.edu 653536Sgblack@eecs.umich.edu return fault; 663536Sgblack@eecs.umich.edu } 673536Sgblack@eecs.umich.edu}}; 683536Sgblack@eecs.umich.edu 693536Sgblack@eecs.umich.edudef template FloatDoubleDecode {{ 703536Sgblack@eecs.umich.edu { 713536Sgblack@eecs.umich.edu ArmStaticInst *i = NULL; 723536Sgblack@eecs.umich.edu switch (OPCODE_19 << 1 | OPCODE_7) 733536Sgblack@eecs.umich.edu { 743536Sgblack@eecs.umich.edu case 0: 753536Sgblack@eecs.umich.edu i = (ArmStaticInst *)new %(class_name)sS(machInst); 763536Sgblack@eecs.umich.edu break; 773536Sgblack@eecs.umich.edu case 1: 783536Sgblack@eecs.umich.edu i = (ArmStaticInst *)new %(class_name)sD(machInst); 793536Sgblack@eecs.umich.edu break; 803536Sgblack@eecs.umich.edu case 2: 813536Sgblack@eecs.umich.edu case 3: 823536Sgblack@eecs.umich.edu default: 833536Sgblack@eecs.umich.edu panic("Cannot decode float/double nature of the instruction"); 843536Sgblack@eecs.umich.edu } 853536Sgblack@eecs.umich.edu return i; 863536Sgblack@eecs.umich.edu } 873536Sgblack@eecs.umich.edu}}; 883536Sgblack@eecs.umich.edu 893536Sgblack@eecs.umich.edu// Primary format for float point operate instructions: 903536Sgblack@eecs.umich.edudef format FloatOp(code, *flags) {{ 913536Sgblack@eecs.umich.edu orig_code = code 923536Sgblack@eecs.umich.edu 933536Sgblack@eecs.umich.edu cblk = code 943536Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'PredOp', 953536Sgblack@eecs.umich.edu {"code": cblk, 963536Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 973536Sgblack@eecs.umich.edu flags) 983536Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(iop) 993536Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(iop) 1003536Sgblack@eecs.umich.edu exec_output = FPAExecute.subst(iop) 1013536Sgblack@eecs.umich.edu 1023536Sgblack@eecs.umich.edu sng_cblk = code 1033536Sgblack@eecs.umich.edu sng_iop = InstObjParams(name, Name+'S', 'PredOp', 1043536Sgblack@eecs.umich.edu {"code": sng_cblk, 1053536Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1063536Sgblack@eecs.umich.edu flags) 1073536Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sng_iop) 1083536Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sng_iop) 1093536Sgblack@eecs.umich.edu exec_output += FPAExecute.subst(sng_iop) 1103536Sgblack@eecs.umich.edu 1113536Sgblack@eecs.umich.edu dbl_code = re.sub(r'\.sf', '.df', orig_code) 1123536Sgblack@eecs.umich.edu 1133536Sgblack@eecs.umich.edu dbl_cblk = dbl_code 1143536Sgblack@eecs.umich.edu dbl_iop = InstObjParams(name, Name+'D', 'PredOp', 1153536Sgblack@eecs.umich.edu {"code": dbl_cblk, 1163536Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 1173536Sgblack@eecs.umich.edu flags) 1183536Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(dbl_iop) 1193536Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(dbl_iop) 1203536Sgblack@eecs.umich.edu exec_output += FPAExecute.subst(dbl_iop) 1213536Sgblack@eecs.umich.edu 1223536Sgblack@eecs.umich.edu decode_block = FloatDoubleDecode.subst(iop) 1233536Sgblack@eecs.umich.edu}}; 1243536Sgblack@eecs.umich.edu 1253536Sgblack@eecs.umich.edulet {{ 1263536Sgblack@eecs.umich.edu calcFPCcCode = ''' 1273536Sgblack@eecs.umich.edu uint16_t _in, _iz, _ic, _iv; 1283536Sgblack@eecs.umich.edu 1293536Sgblack@eecs.umich.edu _in = %(fReg1)s < %(fReg2)s; 1303536Sgblack@eecs.umich.edu _iz = %(fReg1)s == %(fReg2)s; 131 _ic = %(fReg1)s >= %(fReg2)s; 132 _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1; 133 134 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 | 135 (CondCodes & 0x0FFFFFFF); 136 ''' 137}}; 138 139def format FloatCmp(fReg1, fReg2, *flags) {{ 140 code = calcFPCcCode % vars() 141 iop = InstObjParams(name, Name, 'PredOp', 142 {"code": code, 143 "predicate_test": predicateTest}, 144 flags) 145 header_output = BasicDeclare.subst(iop) 146 decoder_output = BasicConstructor.subst(iop) 147 decode_block = BasicDecode.subst(iop) 148 exec_output = FPAExecute.subst(iop) 149}}; 150 151let {{ 152 header_output = ''' 153 StaticInstPtr 154 decodeExtensionRegLoadStore(ExtMachInst machInst); 155 ''' 156 decoder_output = ''' 157 StaticInstPtr 158 decodeExtensionRegLoadStore(ExtMachInst machInst) 159 { 160 const uint32_t opcode = bits(machInst, 24, 20); 161 const uint32_t offset = bits(machInst, 7, 0); 162 const bool single = (bits(machInst, 8) == 0); 163 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 164 RegIndex vd; 165 if (single) { 166 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 167 bits(machInst, 22)); 168 } else { 169 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 170 (bits(machInst, 22) << 5)); 171 } 172 switch (bits(opcode, 4, 3)) { 173 case 0x0: 174 if (bits(opcode, 4, 1) == 0x2 && 175 !(machInst.thumb == 1 && bits(machInst, 28) == 1) && 176 !(machInst.thumb == 0 && machInst.condCode == 0xf)) { 177 if ((bits(machInst, 7, 4) & 0xd) != 1) { 178 break; 179 } 180 const IntRegIndex rt = 181 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 182 const IntRegIndex rt2 = 183 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 184 const bool op = bits(machInst, 20); 185 uint32_t vm; 186 if (single) { 187 vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5); 188 } else { 189 vm = (bits(machInst, 3, 0) << 1) | 190 (bits(machInst, 5) << 5); 191 } 192 if (op) { 193 return new Vmov2Core2Reg(machInst, rt, rt2, 194 (IntRegIndex)vm); 195 } else { 196 return new Vmov2Reg2Core(machInst, (IntRegIndex)vm, 197 rt, rt2); 198 } 199 } 200 break; 201 case 0x1: 202 switch (bits(opcode, 1, 0)) { 203 case 0x0: 204 return new VLdmStm(machInst, rn, vd, single, 205 true, false, false, offset); 206 case 0x1: 207 return new VLdmStm(machInst, rn, vd, single, 208 true, false, true, offset); 209 case 0x2: 210 return new VLdmStm(machInst, rn, vd, single, 211 true, true, false, offset); 212 case 0x3: 213 // If rn == sp, then this is called vpop. 214 return new VLdmStm(machInst, rn, vd, single, 215 true, true, true, offset); 216 } 217 case 0x2: 218 if (bits(opcode, 1, 0) == 0x2) { 219 // If rn == sp, then this is called vpush. 220 return new VLdmStm(machInst, rn, vd, single, 221 false, true, false, offset); 222 } else if (bits(opcode, 1, 0) == 0x3) { 223 return new VLdmStm(machInst, rn, vd, single, 224 false, true, true, offset); 225 } 226 // Fall through on purpose 227 case 0x3: 228 const bool up = (bits(machInst, 23) == 1); 229 const uint32_t imm = bits(machInst, 7, 0) << 2; 230 RegIndex vd; 231 if (single) { 232 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 233 (bits(machInst, 22))); 234 } else { 235 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) | 236 (bits(machInst, 22) << 5)); 237 } 238 if (bits(opcode, 1, 0) == 0x0) { 239 if (single) { 240 if (up) { 241 return new %(vstr_us)s(machInst, vd, rn, up, imm); 242 } else { 243 return new %(vstr_s)s(machInst, vd, rn, up, imm); 244 } 245 } else { 246 if (up) { 247 return new %(vstr_ud)s(machInst, vd, vd + 1, 248 rn, up, imm); 249 } else { 250 return new %(vstr_d)s(machInst, vd, vd + 1, 251 rn, up, imm); 252 } 253 } 254 } else if (bits(opcode, 1, 0) == 0x1) { 255 if (single) { 256 if (up) { 257 return new %(vldr_us)s(machInst, vd, rn, up, imm); 258 } else { 259 return new %(vldr_s)s(machInst, vd, rn, up, imm); 260 } 261 } else { 262 if (up) { 263 return new %(vldr_ud)s(machInst, vd, vd + 1, 264 rn, up, imm); 265 } else { 266 return new %(vldr_d)s(machInst, vd, vd + 1, 267 rn, up, imm); 268 } 269 } 270 } 271 } 272 return new Unknown(machInst); 273 } 274 ''' % { 275 "vldr_us" : "VLDR_" + loadImmClassName(False, True, False), 276 "vldr_s" : "VLDR_" + loadImmClassName(False, False, False), 277 "vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False), 278 "vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False), 279 "vstr_us" : "VSTR_" + storeImmClassName(False, True, False), 280 "vstr_s" : "VSTR_" + storeImmClassName(False, False, False), 281 "vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False), 282 "vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False) 283 } 284}}; 285 286def format ExtensionRegLoadStore() {{ 287 decode_block = ''' 288 return decodeExtensionRegLoadStore(machInst); 289 ''' 290}}; 291 292let {{ 293 header_output = ''' 294 StaticInstPtr 295 decodeShortFpTransfer(ExtMachInst machInst); 296 ''' 297 decoder_output = ''' 298 StaticInstPtr 299 decodeShortFpTransfer(ExtMachInst machInst) 300 { 301 const uint32_t l = bits(machInst, 20); 302 const uint32_t c = bits(machInst, 8); 303 const uint32_t a = bits(machInst, 23, 21); 304 const uint32_t b = bits(machInst, 6, 5); 305 if ((machInst.thumb == 1 && bits(machInst, 28) == 1) || 306 (machInst.thumb == 0 && machInst.condCode == 0xf)) { 307 return new Unknown(machInst); 308 } 309 if (l == 0 && c == 0) { 310 if (a == 0) { 311 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 312 bits(machInst, 7); 313 const IntRegIndex rt = 314 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 315 if (bits(machInst, 20) == 1) { 316 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 317 } else { 318 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 319 } 320 } else if (a == 0x7) { 321 const IntRegIndex rt = 322 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 323 uint32_t specReg = bits(machInst, 19, 16); 324 switch (specReg) { 325 case 0: 326 specReg = MISCREG_FPSID; 327 break; 328 case 1: 329 specReg = MISCREG_FPSCR; 330 break; 331 case 8: 332 specReg = MISCREG_FPEXC; 333 break; 334 default: 335 return new Unknown(machInst); 336 } 337 return new Vmsr(machInst, (IntRegIndex)specReg, rt); 338 } 339 } else if (l == 0 && c == 1) { 340 if (bits(a, 2) == 0) { 341 uint32_t vd = (bits(machInst, 7) << 5) | 342 (bits(machInst, 19, 16) << 1); 343 uint32_t index, size; 344 const IntRegIndex rt = 345 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 346 if (bits(machInst, 22) == 1) { 347 size = 8; 348 index = (bits(machInst, 21) << 2) | 349 bits(machInst, 6, 5); 350 } else if (bits(machInst, 5) == 1) { 351 size = 16; 352 index = (bits(machInst, 21) << 1) | 353 bits(machInst, 6); 354 } else if (bits(machInst, 6) == 0) { 355 size = 32; 356 index = bits(machInst, 21); 357 } else { 358 return new Unknown(machInst); 359 } 360 if (index >= (32 / size)) { 361 index -= (32 / size); 362 vd++; 363 } 364 switch (size) { 365 case 8: 366 return new VmovCoreRegB(machInst, (IntRegIndex)vd, 367 rt, index); 368 case 16: 369 return new VmovCoreRegH(machInst, (IntRegIndex)vd, 370 rt, index); 371 case 32: 372 return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt); 373 } 374 } else if (bits(b, 1) == 0) { 375 // A8-594 376 return new WarnUnimplemented("vdup", machInst); 377 } 378 } else if (l == 1 && c == 0) { 379 if (a == 0) { 380 const uint32_t vn = (bits(machInst, 19, 16) << 1) | 381 bits(machInst, 7); 382 const IntRegIndex rt = 383 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 384 if (bits(machInst, 20) == 1) { 385 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn); 386 } else { 387 return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt); 388 } 389 } else if (a == 7) { 390 const IntRegIndex rt = 391 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 392 uint32_t specReg = bits(machInst, 19, 16); 393 switch (specReg) { 394 case 0: 395 specReg = MISCREG_FPSID; 396 break; 397 case 1: 398 specReg = MISCREG_FPSCR; 399 break; 400 case 6: 401 specReg = MISCREG_MVFR1; 402 break; 403 case 7: 404 specReg = MISCREG_MVFR0; 405 break; 406 case 8: 407 specReg = MISCREG_FPEXC; 408 break; 409 default: 410 return new Unknown(machInst); 411 } 412 return new Vmrs(machInst, rt, (IntRegIndex)specReg); 413 } 414 } else { 415 uint32_t vd = (bits(machInst, 7) << 5) | 416 (bits(machInst, 19, 16) << 1); 417 uint32_t index, size; 418 const IntRegIndex rt = 419 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 420 const bool u = (bits(machInst, 23) == 1); 421 if (bits(machInst, 22) == 1) { 422 size = 8; 423 index = (bits(machInst, 21) << 2) | 424 bits(machInst, 6, 5); 425 } else if (bits(machInst, 5) == 1) { 426 size = 16; 427 index = (bits(machInst, 21) << 1) | 428 bits(machInst, 6); 429 } else if (bits(machInst, 6) == 0 && !u) { 430 size = 32; 431 index = bits(machInst, 21); 432 } else { 433 return new Unknown(machInst); 434 } 435 if (index >= (32 / size)) { 436 index -= (32 / size); 437 vd++; 438 } 439 switch (size) { 440 case 8: 441 if (u) { 442 return new VmovRegCoreUB(machInst, rt, 443 (IntRegIndex)vd, index); 444 } else { 445 return new VmovRegCoreSB(machInst, rt, 446 (IntRegIndex)vd, index); 447 } 448 case 16: 449 if (u) { 450 return new VmovRegCoreUH(machInst, rt, 451 (IntRegIndex)vd, index); 452 } else { 453 return new VmovRegCoreSH(machInst, rt, 454 (IntRegIndex)vd, index); 455 } 456 case 32: 457 return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd); 458 } 459 } 460 return new Unknown(machInst); 461 } 462 ''' 463}}; 464 465def format ShortFpTransfer() {{ 466 decode_block = ''' 467 return decodeShortFpTransfer(machInst); 468 ''' 469}}; 470