xref: /gem5/src/arch/arm/isa/formats/fp.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
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// neither the name of the copyright holders nor the names of its
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
//

def template FPAExecute {{
        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
        {
                Fault fault = NoFault;

                %(fp_enable_check)s;

                %(op_decl)s;
                %(op_rd)s;

                if (%(predicate_test)s) {
                    %(code)s;
                    if (fault == NoFault) {
                        %(op_wb)s;
                    }
                }

                return fault;
        }
}};

def template FloatDoubleDecode {{
    {
        ArmStaticInst *i = NULL;
        switch (OPCODE_19 << 1 | OPCODE_7)
        {
            case 0:
                i = (ArmStaticInst *)new %(class_name)sS(machInst);
                break;
            case 1:
                i = (ArmStaticInst *)new %(class_name)sD(machInst);
                break;
            case 2:
            case 3:
            default:
                panic("Cannot decode float/double nature of the instruction");
        }
        return i;
    }
}};

// Primary format for float point operate instructions:
def format FloatOp(code, *flags) {{
        orig_code = code

        cblk = code
        iop = InstObjParams(name, Name, 'PredOp',
                            {"code": cblk,
                             "predicate_test": predicateTest},
                            flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        exec_output = FPAExecute.subst(iop)

        sng_cblk = code
        sng_iop = InstObjParams(name, Name+'S', 'PredOp',
                                {"code": sng_cblk,
                                 "predicate_test": predicateTest},
                                flags)
        header_output += BasicDeclare.subst(sng_iop)
        decoder_output += BasicConstructor.subst(sng_iop)
        exec_output += FPAExecute.subst(sng_iop)

        dbl_code = re.sub(r'\.sf', '.df', orig_code)

        dbl_cblk = dbl_code
        dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
                                {"code": dbl_cblk,
                                 "predicate_test": predicateTest},
                                flags)
        header_output += BasicDeclare.subst(dbl_iop)
        decoder_output += BasicConstructor.subst(dbl_iop)
        exec_output += FPAExecute.subst(dbl_iop)

        decode_block = FloatDoubleDecode.subst(iop)
}};

let {{
        calcFPCcCode = '''
        uint16_t _in, _iz, _ic, _iv;

        _in = %(fReg1)s < %(fReg2)s;
        _iz = %(fReg1)s == %(fReg2)s;
        _ic = %(fReg1)s >= %(fReg2)s;
        _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;

        CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
            (CondCodes & 0x0FFFFFFF);
        '''
}};

def format FloatCmp(fReg1, fReg2, *flags) {{
        code = calcFPCcCode % vars()
        iop = InstObjParams(name, Name, 'PredOp',
                            {"code": code,
                             "predicate_test": predicateTest},
                             flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = FPAExecute.subst(iop)
}};

def format ExtensionRegLoadStore() {{
    decode_block = '''
    {
        const uint32_t opcode = bits(machInst, 24, 20);
        const uint32_t offset = bits(machInst, 7, 0);
        const bool single = bits(machInst, 22);
        const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
        RegIndex vd;
        if (single) {
            vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
                                      bits(machInst, 22));
        } else {
            vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
                                      (bits(machInst, 22) << 5));
        }
        switch (bits(opcode, 4, 3)) {
          case 0x0:
            if (bits(opcode, 4, 1) == 0x2 &&
                    !(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
                    !(machInst.thumb == 0 && machInst.condCode == 0xf)) {
                if ((bits(machInst, 7, 4) & 0xd) != 1) {
                    break;
                }
                const IntRegIndex rt =
                    (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
                const IntRegIndex rt2 =
                    (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
                const bool op = bits(machInst, 20);
                uint32_t vm;
                if (bits(machInst, 8) == 0) {
                    vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
                } else {
                    vm = (bits(machInst, 3, 0) << 1) |
                         (bits(machInst, 5) << 5);
                }
                if (op) {
                    return new Vmov2Core2Reg(machInst, rt, rt2,
                                             (IntRegIndex)vm);
                } else {
                    return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
                                             rt, rt2);
                }
            }
            break;
          case 0x1:
            switch (bits(opcode, 1, 0)) {
              case 0x0:
                return new VLdmStm(machInst, rn, vd, single,
                                   true, false, false, offset);
              case 0x1:
                return new VLdmStm(machInst, rn, vd, single,
                                   true, false, true, offset);
              case 0x2:
                return new VLdmStm(machInst, rn, vd, single,
                                   true, true, false, offset);
              case 0x3:
                // If rn == sp, then this is called vpop.
                return new VLdmStm(machInst, rn, vd, single,
                                   true, true, true, offset);
            }
          case 0x2:
            if (bits(opcode, 1, 0) == 0x2) {
                // If rn == sp, then this is called vpush.
                return new VLdmStm(machInst, rn, vd, single,
                                   false, true, false, offset);
            } else if (bits(opcode, 1, 0) == 0x3) {
                return new VLdmStm(machInst, rn, vd, single,
                                   false, true, true, offset);
            }
            // Fall through on purpose
          case 0x3:
            if (bits(opcode, 1, 0) == 0x0) {
                return new WarnUnimplemented("vstr", machInst);
            } else if (bits(opcode, 1, 0) == 0x1) {
                return new WarnUnimplemented("vldr", machInst);
            }
        }
        return new Unknown(machInst);
    }
    '''
}};

def format ShortFpTransfer() {{
    decode_block = '''
    {
        const uint32_t l = bits(machInst, 20);
        const uint32_t c = bits(machInst, 8);
        const uint32_t a = bits(machInst, 23, 21);
        const uint32_t b = bits(machInst, 6, 5);
        if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
            (machInst.thumb == 0 && machInst.condCode == 0xf)) {
            return new Unknown(machInst);
        }
        if (l == 0 && c == 0) {
            if (a == 0) {
                const uint32_t vn = (bits(machInst, 19, 16) << 1) |
                                    bits(machInst, 7);
                const IntRegIndex rt =
                    (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
                if (bits(machInst, 20) == 1) {
                    return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
                } else {
                    return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
                }
            } else if (a == 0x7) {
                const IntRegIndex rt =
                    (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
                uint32_t specReg = bits(machInst, 19, 16);
                switch (specReg) {
                  case 0:
                    specReg = MISCREG_FPSID;
                    break;
                  case 1:
                    specReg = MISCREG_FPSCR;
                    break;
                  case 8:
                    specReg = MISCREG_FPEXC;
                    break;
                  default:
                    return new Unknown(machInst);
                }
                return new Vmsr(machInst, (IntRegIndex)specReg, rt);
            }
        } else if (l == 0 && c == 1) {
            if (bits(a, 2) == 0) {
                uint32_t vd = (bits(machInst, 7) << 5) |
                              (bits(machInst, 19, 16) << 1);
                uint32_t index, size;
                const IntRegIndex rt =
                    (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
                if (bits(machInst, 22) == 1) {
                    size = 8;
                    index = (bits(machInst, 21) << 2) |
                            bits(machInst, 6, 5);
                } else if (bits(machInst, 5) == 1) {
                    size = 16;
                    index = (bits(machInst, 21) << 1) |
                            bits(machInst, 6);
                } else if (bits(machInst, 6) == 0) {
                    size = 32;
                    index = bits(machInst, 21);
                } else {
                    return new Unknown(machInst);
                }
                if (index >= (32 / size)) {
                    index -= (32 / size);
                    vd++;
                }
                switch (size) {
                  case 8:
                    return new VmovCoreRegB(machInst, (IntRegIndex)vd,
                                            rt, index);
                  case 16:
                    return new VmovCoreRegH(machInst, (IntRegIndex)vd,
                                            rt, index);
                  case 32:
                    return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
                }
            } else if (bits(b, 1) == 0) {
                // A8-594
                return new WarnUnimplemented("vdup", machInst);
            }
        } else if (l == 1 && c == 0) {
            if (a == 0) {
                const uint32_t vn = (bits(machInst, 19, 16) << 1) |
                                    bits(machInst, 7);
                const IntRegIndex rt =
                    (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
                if (bits(machInst, 20) == 1) {
                    return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
                } else {
                    return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
                }
            } else if (a == 7) {
                const IntRegIndex rt =
                    (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
                uint32_t specReg = bits(machInst, 19, 16);
                switch (specReg) {
                  case 0:
                    specReg = MISCREG_FPSID;
                    break;
                  case 1:
                    specReg = MISCREG_FPSCR;
                    break;
                  case 6:
                    specReg = MISCREG_MVFR1;
                    break;
                  case 7:
                    specReg = MISCREG_MVFR0;
                    break;
                  case 8:
                    specReg = MISCREG_FPEXC;
                    break;
                  default:
                    return new Unknown(machInst);
                }
                return new Vmrs(machInst, rt, (IntRegIndex)specReg);
            }
        } else {
            uint32_t vd = (bits(machInst, 7) << 5) |
                          (bits(machInst, 19, 16) << 1);
            uint32_t index, size;
            const IntRegIndex rt =
                (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
            const bool u = (bits(machInst, 23) == 1);
            if (bits(machInst, 22) == 1) {
                size = 8;
                index = (bits(machInst, 21) << 2) |
                        bits(machInst, 6, 5);
            } else if (bits(machInst, 5) == 1) {
                size = 16;
                index = (bits(machInst, 21) << 1) |
                        bits(machInst, 6);
            } else if (bits(machInst, 6) == 0 && !u) {
                size = 32;
                index = bits(machInst, 21);
            } else {
                return new Unknown(machInst);
            }
            if (index >= (32 / size)) {
                index -= (32 / size);
                vd++;
            }
            switch (size) {
              case 8:
                if (u) {
                    return new VmovRegCoreUB(machInst, rt,
                                             (IntRegIndex)vd, index);
                } else {
                    return new VmovRegCoreSB(machInst, rt,
                                             (IntRegIndex)vd, index);
                }
              case 16:
                if (u) {
                    return new VmovRegCoreUH(machInst, rt,
                                             (IntRegIndex)vd, index);
                } else {
                    return new VmovRegCoreSH(machInst, rt,
                                             (IntRegIndex)vd, index);
                }
              case 32:
                return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
            }
        }
        return new Unknown(machInst);
    }
    '''
}};