data.isa revision 7258
17139Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387255Sgblack@eecs.umich.edudef format ArmMiscMedia() {{ 397243Sgblack@eecs.umich.edu decode_block = ''' 407243Sgblack@eecs.umich.edu { 417255Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 427255Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 437243Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 447243Sgblack@eecs.umich.edu const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 457255Sgblack@eecs.umich.edu if (op1 == 0 && op2 == 0) { 467255Sgblack@eecs.umich.edu const IntRegIndex rd = 477255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 487255Sgblack@eecs.umich.edu const IntRegIndex rm = 497255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 507255Sgblack@eecs.umich.edu if (ra == 0xf) { 517255Sgblack@eecs.umich.edu return new Usad8(machInst, rd, rn, rm); 527255Sgblack@eecs.umich.edu } else { 537255Sgblack@eecs.umich.edu return new Usada8(machInst, rd, rn, rm, ra); 547255Sgblack@eecs.umich.edu } 557255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x2) { 567256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 11, 7); 577256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 20, 16); 587255Sgblack@eecs.umich.edu if (bits(op1, 2, 1) == 0x3) { 597256Sgblack@eecs.umich.edu return new Ubfx(machInst, ra, rn, lsb, msb); 607255Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 0x1) { 617256Sgblack@eecs.umich.edu return new Sbfx(machInst, ra, rn, lsb, msb); 627255Sgblack@eecs.umich.edu } 637255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 647258Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 11, 7); 657258Sgblack@eecs.umich.edu const uint32_t msb = bits(machInst, 20, 16); 667255Sgblack@eecs.umich.edu if (rn == 0xf) { 677258Sgblack@eecs.umich.edu return new Bfc(machInst, ra, ra, lsb, msb); 687255Sgblack@eecs.umich.edu } else { 697258Sgblack@eecs.umich.edu return new Bfi(machInst, ra, rn, lsb, msb); 707255Sgblack@eecs.umich.edu } 717243Sgblack@eecs.umich.edu } 727255Sgblack@eecs.umich.edu return new Unknown(machInst); 737243Sgblack@eecs.umich.edu } 747243Sgblack@eecs.umich.edu ''' 757243Sgblack@eecs.umich.edu}}; 767243Sgblack@eecs.umich.edu 777139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 787188Sgblack@eecs.umich.edu pclr = ''' 797188Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 807188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 817188Sgblack@eecs.umich.edu type); 827188Sgblack@eecs.umich.edu ''' 837139Sgblack@eecs.umich.edu instDecode = ''' 847139Sgblack@eecs.umich.edu case %(opcode)#x: 857139Sgblack@eecs.umich.edu if (immShift) { 867139Sgblack@eecs.umich.edu if (setCc) { 877188Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 887188Sgblack@eecs.umich.edu %(pclr)s 897188Sgblack@eecs.umich.edu } else { 907188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 917188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 927188Sgblack@eecs.umich.edu } 937139Sgblack@eecs.umich.edu } else { 947146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 957141Sgblack@eecs.umich.edu rm, imm5, type); 967139Sgblack@eecs.umich.edu } 977139Sgblack@eecs.umich.edu } else { 987139Sgblack@eecs.umich.edu if (setCc) { 997146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 1007141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1017139Sgblack@eecs.umich.edu } else { 1027146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 1037141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1047139Sgblack@eecs.umich.edu } 1057139Sgblack@eecs.umich.edu } 1067139Sgblack@eecs.umich.edu break; 1077139Sgblack@eecs.umich.edu ''' 1087139Sgblack@eecs.umich.edu 1097188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 1107188Sgblack@eecs.umich.edu global pclr 1117188Sgblack@eecs.umich.edu if useDest: 1127188Sgblack@eecs.umich.edu dest = "rd" 1137188Sgblack@eecs.umich.edu else: 1147188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 1157188Sgblack@eecs.umich.edu if useOp1: 1167188Sgblack@eecs.umich.edu op1 = "rn" 1177188Sgblack@eecs.umich.edu else: 1187188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 1197188Sgblack@eecs.umich.edu global instDecode, pclrCode 1207188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1217188Sgblack@eecs.umich.edu "opcode": opcode, 1227188Sgblack@eecs.umich.edu "dest": dest, 1237188Sgblack@eecs.umich.edu "op1": op1 } 1247188Sgblack@eecs.umich.edu if useDest: 1257188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1267188Sgblack@eecs.umich.edu else: 1277188Sgblack@eecs.umich.edu substDict["pclr"] = "" 1287188Sgblack@eecs.umich.edu return instDecode % substDict 1297139Sgblack@eecs.umich.edu 1307139Sgblack@eecs.umich.edu decode_block = ''' 1317139Sgblack@eecs.umich.edu { 1327139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 1337139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 1347139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 1357139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1367139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 1377139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 1387139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1397139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1407139Sgblack@eecs.umich.edu switch (OPCODE) { 1417139Sgblack@eecs.umich.edu ''' 1427139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1437139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1447139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1457139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1467139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1477139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1487139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1497139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1507188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1517188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1527188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1537188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1547139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1557188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1567139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1577188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1587139Sgblack@eecs.umich.edu decode_block += ''' 1597139Sgblack@eecs.umich.edu default: 1607139Sgblack@eecs.umich.edu return new Unknown(machInst); 1617139Sgblack@eecs.umich.edu } 1627139Sgblack@eecs.umich.edu } 1637139Sgblack@eecs.umich.edu ''' 1647139Sgblack@eecs.umich.edu}}; 1657139Sgblack@eecs.umich.edu 1667210Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1677210Sgblack@eecs.umich.edu decode_block = ''' 1687210Sgblack@eecs.umich.edu { 1697210Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1707210Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1717210Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1727210Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1737227Sgblack@eecs.umich.edu const IntRegIndex rn = 1747227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1757227Sgblack@eecs.umich.edu const IntRegIndex rd = 1767227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1777227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1787227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 11, 7); 1797227Sgblack@eecs.umich.edu const ArmShiftType type = 1807227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1817210Sgblack@eecs.umich.edu if (op1 == 0) { 1827237Sgblack@eecs.umich.edu if (type) { 1837237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, (IntRegIndex)a, 1847237Sgblack@eecs.umich.edu rn, imm, type); 1857237Sgblack@eecs.umich.edu } else { 1867237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, (IntRegIndex)a, 1877237Sgblack@eecs.umich.edu rn, imm, type); 1887237Sgblack@eecs.umich.edu } 1897210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1907227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1917210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1927227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 1937210Sgblack@eecs.umich.edu } 1947210Sgblack@eecs.umich.edu return new Unknown(machInst); 1957210Sgblack@eecs.umich.edu } 1967210Sgblack@eecs.umich.edu switch (op1) { 1977210Sgblack@eecs.umich.edu case 0x0: 1987240Sgblack@eecs.umich.edu { 1997235Sgblack@eecs.umich.edu const IntRegIndex rn = 2007235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2017235Sgblack@eecs.umich.edu const IntRegIndex rd = 2027235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2037235Sgblack@eecs.umich.edu const IntRegIndex rm = 2047235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2057240Sgblack@eecs.umich.edu if (op2 == 0x3) { 2067240Sgblack@eecs.umich.edu const uint32_t rotation = 2077240Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2087240Sgblack@eecs.umich.edu if (a == 0xf) { 2097240Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 2107240Sgblack@eecs.umich.edu } else { 2117240Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 2127240Sgblack@eecs.umich.edu } 2137240Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2147240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 2157210Sgblack@eecs.umich.edu } 2167210Sgblack@eecs.umich.edu } 2177210Sgblack@eecs.umich.edu break; 2187210Sgblack@eecs.umich.edu case 0x2: 2197210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2207227Sgblack@eecs.umich.edu const IntRegIndex rn = 2217227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2227227Sgblack@eecs.umich.edu const IntRegIndex rd = 2237227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2247227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2257227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 2267210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2277235Sgblack@eecs.umich.edu const IntRegIndex rn = 2287235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2297235Sgblack@eecs.umich.edu const IntRegIndex rd = 2307235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2317235Sgblack@eecs.umich.edu const IntRegIndex rm = 2327235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2337235Sgblack@eecs.umich.edu const uint32_t rotation = 2347235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2357210Sgblack@eecs.umich.edu if (a == 0xf) { 2367235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 2377210Sgblack@eecs.umich.edu } else { 2387235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 2397210Sgblack@eecs.umich.edu } 2407210Sgblack@eecs.umich.edu } 2417210Sgblack@eecs.umich.edu break; 2427210Sgblack@eecs.umich.edu case 0x3: 2437210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2447211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2457211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2467211Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 2477210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2487235Sgblack@eecs.umich.edu const IntRegIndex rn = 2497235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2507235Sgblack@eecs.umich.edu const IntRegIndex rd = 2517235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2527235Sgblack@eecs.umich.edu const IntRegIndex rm = 2537235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2547235Sgblack@eecs.umich.edu const uint32_t rotation = 2557235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2567210Sgblack@eecs.umich.edu if (a == 0xf) { 2577235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 2587210Sgblack@eecs.umich.edu } else { 2597235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 2607210Sgblack@eecs.umich.edu } 2617210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2627211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2637211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2647211Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 2657210Sgblack@eecs.umich.edu } 2667210Sgblack@eecs.umich.edu break; 2677210Sgblack@eecs.umich.edu case 0x4: 2687210Sgblack@eecs.umich.edu if (op2 == 0x3) { 2697235Sgblack@eecs.umich.edu const IntRegIndex rn = 2707235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2717235Sgblack@eecs.umich.edu const IntRegIndex rd = 2727235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2737235Sgblack@eecs.umich.edu const IntRegIndex rm = 2747235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2757235Sgblack@eecs.umich.edu const uint32_t rotation = 2767235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2777210Sgblack@eecs.umich.edu if (a == 0xf) { 2787235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 2797210Sgblack@eecs.umich.edu } else { 2807235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 2817210Sgblack@eecs.umich.edu } 2827210Sgblack@eecs.umich.edu } 2837210Sgblack@eecs.umich.edu break; 2847210Sgblack@eecs.umich.edu case 0x6: 2857210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2867227Sgblack@eecs.umich.edu const IntRegIndex rn = 2877227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2887227Sgblack@eecs.umich.edu const IntRegIndex rd = 2897227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2907227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2917227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 2927210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2937235Sgblack@eecs.umich.edu const IntRegIndex rn = 2947235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2957235Sgblack@eecs.umich.edu const IntRegIndex rd = 2967235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2977235Sgblack@eecs.umich.edu const IntRegIndex rm = 2987235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2997235Sgblack@eecs.umich.edu const uint32_t rotation = 3007235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3017210Sgblack@eecs.umich.edu if (a == 0xf) { 3027235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 3037210Sgblack@eecs.umich.edu } else { 3047235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 3057210Sgblack@eecs.umich.edu } 3067210Sgblack@eecs.umich.edu } 3077210Sgblack@eecs.umich.edu break; 3087210Sgblack@eecs.umich.edu case 0x7: 3097250Sgblack@eecs.umich.edu { 3107235Sgblack@eecs.umich.edu const IntRegIndex rn = 3117235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3127235Sgblack@eecs.umich.edu const IntRegIndex rd = 3137235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3147235Sgblack@eecs.umich.edu const IntRegIndex rm = 3157235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3167250Sgblack@eecs.umich.edu if (op2 == 0x1) { 3177250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 3187250Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 3197250Sgblack@eecs.umich.edu const uint32_t rotation = 3207250Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3217250Sgblack@eecs.umich.edu if (a == 0xf) { 3227250Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 3237250Sgblack@eecs.umich.edu } else { 3247250Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 3257250Sgblack@eecs.umich.edu } 3267250Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 3277250Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 3287210Sgblack@eecs.umich.edu } 3297210Sgblack@eecs.umich.edu } 3307210Sgblack@eecs.umich.edu break; 3317210Sgblack@eecs.umich.edu } 3327210Sgblack@eecs.umich.edu return new Unknown(machInst); 3337210Sgblack@eecs.umich.edu } 3347210Sgblack@eecs.umich.edu ''' 3357210Sgblack@eecs.umich.edu}}; 3367210Sgblack@eecs.umich.edu 3377194Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 3387194Sgblack@eecs.umich.edu decode_block=''' 3397194Sgblack@eecs.umich.edu { 3407194Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 3417194Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 3427194Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3437194Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3447194Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3457194Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 3467194Sgblack@eecs.umich.edu switch (op1) { 3477194Sgblack@eecs.umich.edu case 0x1: 3487194Sgblack@eecs.umich.edu switch (op2) { 3497194Sgblack@eecs.umich.edu case 0x0: 3507216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3517194Sgblack@eecs.umich.edu case 0x1: 3527224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 3537194Sgblack@eecs.umich.edu case 0x2: 3547224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3557194Sgblack@eecs.umich.edu case 0x3: 3567218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 3577194Sgblack@eecs.umich.edu case 0x4: 3587216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3597194Sgblack@eecs.umich.edu case 0x7: 3607218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 3617194Sgblack@eecs.umich.edu } 3627194Sgblack@eecs.umich.edu break; 3637194Sgblack@eecs.umich.edu case 0x2: 3647194Sgblack@eecs.umich.edu switch (op2) { 3657194Sgblack@eecs.umich.edu case 0x0: 3667194Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 3677194Sgblack@eecs.umich.edu case 0x1: 3687194Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 3697194Sgblack@eecs.umich.edu case 0x2: 3707194Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 3717194Sgblack@eecs.umich.edu case 0x3: 3727194Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 3737194Sgblack@eecs.umich.edu case 0x4: 3747194Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 3757194Sgblack@eecs.umich.edu case 0x7: 3767194Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 3777194Sgblack@eecs.umich.edu } 3787194Sgblack@eecs.umich.edu break; 3797194Sgblack@eecs.umich.edu case 0x3: 3807194Sgblack@eecs.umich.edu switch (op2) { 3817194Sgblack@eecs.umich.edu case 0x0: 3827231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 3837194Sgblack@eecs.umich.edu case 0x1: 3847231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 3857194Sgblack@eecs.umich.edu case 0x2: 3867231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 3877194Sgblack@eecs.umich.edu case 0x3: 3887231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 3897194Sgblack@eecs.umich.edu case 0x4: 3907231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 3917194Sgblack@eecs.umich.edu case 0x7: 3927231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 3937194Sgblack@eecs.umich.edu } 3947194Sgblack@eecs.umich.edu break; 3957194Sgblack@eecs.umich.edu } 3967194Sgblack@eecs.umich.edu } else { 3977194Sgblack@eecs.umich.edu switch (op1) { 3987194Sgblack@eecs.umich.edu case 0x1: 3997194Sgblack@eecs.umich.edu switch (op2) { 4007194Sgblack@eecs.umich.edu case 0x0: 4017222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 4027194Sgblack@eecs.umich.edu case 0x1: 4037222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 4047194Sgblack@eecs.umich.edu case 0x2: 4057222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 4067194Sgblack@eecs.umich.edu case 0x3: 4077222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 4087194Sgblack@eecs.umich.edu case 0x4: 4097222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 4107194Sgblack@eecs.umich.edu case 0x7: 4117222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 4127194Sgblack@eecs.umich.edu } 4137194Sgblack@eecs.umich.edu break; 4147194Sgblack@eecs.umich.edu case 0x2: 4157194Sgblack@eecs.umich.edu switch (op2) { 4167194Sgblack@eecs.umich.edu case 0x0: 4177220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 4187194Sgblack@eecs.umich.edu case 0x1: 4197220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 4207194Sgblack@eecs.umich.edu case 0x2: 4217220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 4227194Sgblack@eecs.umich.edu case 0x3: 4237220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 4247194Sgblack@eecs.umich.edu case 0x4: 4257220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 4267194Sgblack@eecs.umich.edu case 0x7: 4277220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 4287194Sgblack@eecs.umich.edu } 4297194Sgblack@eecs.umich.edu break; 4307194Sgblack@eecs.umich.edu case 0x3: 4317194Sgblack@eecs.umich.edu switch (op2) { 4327194Sgblack@eecs.umich.edu case 0x0: 4337231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 4347194Sgblack@eecs.umich.edu case 0x1: 4357231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 4367194Sgblack@eecs.umich.edu case 0x2: 4377231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 4387194Sgblack@eecs.umich.edu case 0x3: 4397231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 4407194Sgblack@eecs.umich.edu case 0x4: 4417231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 4427194Sgblack@eecs.umich.edu case 0x7: 4437231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 4447194Sgblack@eecs.umich.edu } 4457194Sgblack@eecs.umich.edu break; 4467194Sgblack@eecs.umich.edu } 4477194Sgblack@eecs.umich.edu } 4487194Sgblack@eecs.umich.edu return new Unknown(machInst); 4497194Sgblack@eecs.umich.edu } 4507194Sgblack@eecs.umich.edu ''' 4517194Sgblack@eecs.umich.edu}}; 4527194Sgblack@eecs.umich.edu 4537139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 4547188Sgblack@eecs.umich.edu pclr = ''' 4557188Sgblack@eecs.umich.edu return new %(className)ssImmPclr(machInst, %(dest)s, 4567188Sgblack@eecs.umich.edu %(op1)s, imm, false); 4577188Sgblack@eecs.umich.edu ''' 4587188Sgblack@eecs.umich.edu adr = ''' 4597188Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 4607188Sgblack@eecs.umich.edu imm, false); 4617188Sgblack@eecs.umich.edu ''' 4627139Sgblack@eecs.umich.edu instDecode = ''' 4637188Sgblack@eecs.umich.edu case %(opcode)#x: 4647139Sgblack@eecs.umich.edu if (setCc) { 4657188Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 4667188Sgblack@eecs.umich.edu %(pclr)s 4677188Sgblack@eecs.umich.edu } else { 4687188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 4697188Sgblack@eecs.umich.edu imm, rotC); 4707188Sgblack@eecs.umich.edu } 4717139Sgblack@eecs.umich.edu } else { 4727188Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 4737188Sgblack@eecs.umich.edu %(adr)s 4747188Sgblack@eecs.umich.edu } else { 4757188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 4767188Sgblack@eecs.umich.edu imm, rotC); 4777188Sgblack@eecs.umich.edu } 4787139Sgblack@eecs.umich.edu } 4797139Sgblack@eecs.umich.edu break; 4807139Sgblack@eecs.umich.edu ''' 4817139Sgblack@eecs.umich.edu 4827188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 4837188Sgblack@eecs.umich.edu global instDecode, pclr, adr 4847188Sgblack@eecs.umich.edu if useDest: 4857188Sgblack@eecs.umich.edu dest = "rd" 4867188Sgblack@eecs.umich.edu else: 4877188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 4887188Sgblack@eecs.umich.edu if useOp1: 4897188Sgblack@eecs.umich.edu op1 = "rn" 4907188Sgblack@eecs.umich.edu else: 4917188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 4927188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4937188Sgblack@eecs.umich.edu "opcode": opcode, 4947188Sgblack@eecs.umich.edu "dest": dest, 4957188Sgblack@eecs.umich.edu "op1": op1, 4967188Sgblack@eecs.umich.edu "adr": "", 4977188Sgblack@eecs.umich.edu "adrInst": "false" } 4987188Sgblack@eecs.umich.edu if useDest: 4997188Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 5007188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5017188Sgblack@eecs.umich.edu else: 5027188Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 5037188Sgblack@eecs.umich.edu substDict["pclr"] = "" 5047188Sgblack@eecs.umich.edu return instDecode % substDict 5057185Sgblack@eecs.umich.edu 5067188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 5077188Sgblack@eecs.umich.edu global instDecode, pclr, adr 5087188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 5097188Sgblack@eecs.umich.edu "opcode": opcode, 5107188Sgblack@eecs.umich.edu "dest": "rd", 5117188Sgblack@eecs.umich.edu "op1": "rn", 5127188Sgblack@eecs.umich.edu "add": add, 5137188Sgblack@eecs.umich.edu "pclrInst": "true", 5147188Sgblack@eecs.umich.edu "adrInst": "true" } 5157188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5167188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 5177188Sgblack@eecs.umich.edu return instDecode % substDict 5187139Sgblack@eecs.umich.edu 5197139Sgblack@eecs.umich.edu decode_block = ''' 5207139Sgblack@eecs.umich.edu { 5217139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 5227139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 5237139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 5247139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 5257139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 5267139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 5277139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 5287139Sgblack@eecs.umich.edu switch (OPCODE) { 5297139Sgblack@eecs.umich.edu ''' 5307139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 5317139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 5327185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 5337139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 5347185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 5357139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 5367139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 5377139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 5387188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 5397188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 5407188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 5417188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 5427139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 5437188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 5447139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 5457188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 5467139Sgblack@eecs.umich.edu decode_block += ''' 5477139Sgblack@eecs.umich.edu default: 5487139Sgblack@eecs.umich.edu return new Unknown(machInst); 5497139Sgblack@eecs.umich.edu } 5507139Sgblack@eecs.umich.edu } 5517139Sgblack@eecs.umich.edu ''' 5527139Sgblack@eecs.umich.edu}}; 5537141Sgblack@eecs.umich.edu 5547195Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 5557195Sgblack@eecs.umich.edu decode_block = ''' 5567195Sgblack@eecs.umich.edu { 5577195Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5587195Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 5597195Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5607195Sgblack@eecs.umich.edu switch (OPCODE) { 5617195Sgblack@eecs.umich.edu case 0x8: 5627195Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 5637195Sgblack@eecs.umich.edu case 0x9: 5647195Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 5657195Sgblack@eecs.umich.edu case 0xa: 5667195Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 5677195Sgblack@eecs.umich.edu case 0xb: 5687195Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 5697195Sgblack@eecs.umich.edu default: 5707195Sgblack@eecs.umich.edu return new Unknown(machInst); 5717195Sgblack@eecs.umich.edu } 5727195Sgblack@eecs.umich.edu } 5737195Sgblack@eecs.umich.edu ''' 5747195Sgblack@eecs.umich.edu}}; 5757195Sgblack@eecs.umich.edu 5767213Sgblack@eecs.umich.edudef format Thumb32DataProcReg() {{ 5777213Sgblack@eecs.umich.edu decode_block = ''' 5787213Sgblack@eecs.umich.edu { 5797213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 23, 20); 5807213Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5817213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 5827213Sgblack@eecs.umich.edu if (bits(op1, 3) != 1) { 5837213Sgblack@eecs.umich.edu if (op2 == 0) { 5847213Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5857213Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5867213Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5877213Sgblack@eecs.umich.edu case 0x0: 5887213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5897213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5907213Sgblack@eecs.umich.edu case 0x1: 5917213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5927213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5937213Sgblack@eecs.umich.edu case 0x2: 5947213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5957213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5967213Sgblack@eecs.umich.edu case 0x3: 5977213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5987213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5997213Sgblack@eecs.umich.edu case 0x4: 6007213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6017213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6027213Sgblack@eecs.umich.edu case 0x5: 6037213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6047213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6057213Sgblack@eecs.umich.edu case 0x6: 6067213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6077213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6087213Sgblack@eecs.umich.edu case 0x7: 6097213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6107213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6117213Sgblack@eecs.umich.edu } 6127213Sgblack@eecs.umich.edu } 6137235Sgblack@eecs.umich.edu { 6147235Sgblack@eecs.umich.edu const IntRegIndex rd = 6157235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6167235Sgblack@eecs.umich.edu const IntRegIndex rm = 6177235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6187235Sgblack@eecs.umich.edu const uint32_t rotation = 6197235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 5, 4) << 3; 6207235Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 6217235Sgblack@eecs.umich.edu case 0x0: 6227235Sgblack@eecs.umich.edu if (rn == 0xf) { 6237235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 6247235Sgblack@eecs.umich.edu } else { 6257235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 6267235Sgblack@eecs.umich.edu } 6277235Sgblack@eecs.umich.edu case 0x1: 6287235Sgblack@eecs.umich.edu if (rn == 0xf) { 6297235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 6307235Sgblack@eecs.umich.edu } else { 6317235Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 6327235Sgblack@eecs.umich.edu } 6337235Sgblack@eecs.umich.edu case 0x2: 6347235Sgblack@eecs.umich.edu if (rn == 0xf) { 6357235Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 6367235Sgblack@eecs.umich.edu } else { 6377235Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 6387235Sgblack@eecs.umich.edu } 6397235Sgblack@eecs.umich.edu case 0x3: 6407235Sgblack@eecs.umich.edu if (rn == 0xf) { 6417235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 6427235Sgblack@eecs.umich.edu } else { 6437235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 6447235Sgblack@eecs.umich.edu } 6457235Sgblack@eecs.umich.edu case 0x4: 6467235Sgblack@eecs.umich.edu if (rn == 0xf) { 6477235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 6487235Sgblack@eecs.umich.edu } else { 6497235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 6507235Sgblack@eecs.umich.edu } 6517235Sgblack@eecs.umich.edu case 0x5: 6527235Sgblack@eecs.umich.edu if (rn == 0xf) { 6537235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 6547235Sgblack@eecs.umich.edu } else { 6557235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 6567235Sgblack@eecs.umich.edu } 6577235Sgblack@eecs.umich.edu default: 6587235Sgblack@eecs.umich.edu return new Unknown(machInst); 6597213Sgblack@eecs.umich.edu } 6607213Sgblack@eecs.umich.edu } 6617213Sgblack@eecs.umich.edu } else { 6627213Sgblack@eecs.umich.edu if (bits(op2, 3) == 0) { 6637220Sgblack@eecs.umich.edu const IntRegIndex rd = 6647220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6657220Sgblack@eecs.umich.edu const IntRegIndex rm = 6667220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6677213Sgblack@eecs.umich.edu if (bits(op2, 2) == 0x0) { 6687213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6697213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6707213Sgblack@eecs.umich.edu switch (op2) { 6717213Sgblack@eecs.umich.edu case 0x0: 6727213Sgblack@eecs.umich.edu switch (op1) { 6737213Sgblack@eecs.umich.edu case 0x1: 6747216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, 6757216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6767213Sgblack@eecs.umich.edu case 0x2: 6777224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, 6787224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6797213Sgblack@eecs.umich.edu case 0x6: 6807224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, 6817224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6827213Sgblack@eecs.umich.edu case 0x5: 6837218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, 6847218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6857213Sgblack@eecs.umich.edu case 0x0: 6867216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, 6877216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6887213Sgblack@eecs.umich.edu case 0x4: 6897218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, 6907218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6917213Sgblack@eecs.umich.edu } 6927213Sgblack@eecs.umich.edu break; 6937213Sgblack@eecs.umich.edu case 0x1: 6947216Sgblack@eecs.umich.edu switch (op1) { 6957216Sgblack@eecs.umich.edu case 0x1: 6967216Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 6977216Sgblack@eecs.umich.edu case 0x2: 6987216Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 6997216Sgblack@eecs.umich.edu case 0x6: 7007216Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 7017216Sgblack@eecs.umich.edu case 0x5: 7027216Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 7037216Sgblack@eecs.umich.edu case 0x0: 7047216Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 7057216Sgblack@eecs.umich.edu case 0x4: 7067216Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 7077213Sgblack@eecs.umich.edu } 7087213Sgblack@eecs.umich.edu break; 7097213Sgblack@eecs.umich.edu case 0x2: 7107213Sgblack@eecs.umich.edu switch (op1) { 7117213Sgblack@eecs.umich.edu case 0x1: 7127231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 7137213Sgblack@eecs.umich.edu case 0x2: 7147231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 7157213Sgblack@eecs.umich.edu case 0x6: 7167231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 7177213Sgblack@eecs.umich.edu case 0x5: 7187231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 7197213Sgblack@eecs.umich.edu case 0x0: 7207231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 7217213Sgblack@eecs.umich.edu case 0x4: 7227231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 7237213Sgblack@eecs.umich.edu } 7247213Sgblack@eecs.umich.edu break; 7257213Sgblack@eecs.umich.edu } 7267213Sgblack@eecs.umich.edu } else { 7277213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 7287213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7297213Sgblack@eecs.umich.edu switch (op2) { 7307213Sgblack@eecs.umich.edu case 0x0: 7317213Sgblack@eecs.umich.edu switch (op1) { 7327213Sgblack@eecs.umich.edu case 0x1: 7337222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, 7347222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7357213Sgblack@eecs.umich.edu case 0x2: 7367222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, 7377222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7387213Sgblack@eecs.umich.edu case 0x6: 7397222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, 7407222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7417213Sgblack@eecs.umich.edu case 0x5: 7427222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, 7437222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7447213Sgblack@eecs.umich.edu case 0x0: 7457222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, 7467222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7477213Sgblack@eecs.umich.edu case 0x4: 7487222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, 7497222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7507213Sgblack@eecs.umich.edu } 7517213Sgblack@eecs.umich.edu break; 7527213Sgblack@eecs.umich.edu case 0x1: 7537213Sgblack@eecs.umich.edu switch (op1) { 7547213Sgblack@eecs.umich.edu case 0x1: 7557220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 7567213Sgblack@eecs.umich.edu case 0x2: 7577220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 7587213Sgblack@eecs.umich.edu case 0x6: 7597220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 7607213Sgblack@eecs.umich.edu case 0x5: 7617220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 7627213Sgblack@eecs.umich.edu case 0x0: 7637220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 7647213Sgblack@eecs.umich.edu case 0x4: 7657220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 7667213Sgblack@eecs.umich.edu } 7677213Sgblack@eecs.umich.edu break; 7687213Sgblack@eecs.umich.edu case 0x2: 7697213Sgblack@eecs.umich.edu switch (op1) { 7707213Sgblack@eecs.umich.edu case 0x1: 7717231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 7727213Sgblack@eecs.umich.edu case 0x2: 7737231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 7747213Sgblack@eecs.umich.edu case 0x6: 7757231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 7767213Sgblack@eecs.umich.edu case 0x5: 7777231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 7787213Sgblack@eecs.umich.edu case 0x0: 7797231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 7807213Sgblack@eecs.umich.edu case 0x4: 7817231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 7827213Sgblack@eecs.umich.edu } 7837213Sgblack@eecs.umich.edu break; 7847213Sgblack@eecs.umich.edu } 7857213Sgblack@eecs.umich.edu } 7867213Sgblack@eecs.umich.edu } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 7877213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 7887213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7897240Sgblack@eecs.umich.edu const IntRegIndex rd = 7907240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7917240Sgblack@eecs.umich.edu const IntRegIndex rm = 7927240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 7937213Sgblack@eecs.umich.edu switch (op1) { 7947213Sgblack@eecs.umich.edu case 0x0: 7957240Sgblack@eecs.umich.edu switch (op2) { 7967240Sgblack@eecs.umich.edu case 0x0: 7977240Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, 7987240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7997240Sgblack@eecs.umich.edu case 0x1: 8007240Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, 8017240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8027240Sgblack@eecs.umich.edu case 0x2: 8037240Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, 8047240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8057240Sgblack@eecs.umich.edu case 0x3: 8067240Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, 8077240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8087213Sgblack@eecs.umich.edu } 8097213Sgblack@eecs.umich.edu break; 8107213Sgblack@eecs.umich.edu case 0x1: 8117240Sgblack@eecs.umich.edu switch (op2) { 8127240Sgblack@eecs.umich.edu case 0x0: 8137240Sgblack@eecs.umich.edu return new Rev(machInst, rd, rn); 8147240Sgblack@eecs.umich.edu case 0x1: 8157240Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rn); 8167240Sgblack@eecs.umich.edu case 0x2: 8177250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 8187240Sgblack@eecs.umich.edu case 0x3: 8197240Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rn); 8207213Sgblack@eecs.umich.edu } 8217213Sgblack@eecs.umich.edu break; 8227213Sgblack@eecs.umich.edu case 0x2: 8237213Sgblack@eecs.umich.edu if (op2 == 0) { 8247240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 8257213Sgblack@eecs.umich.edu } 8267213Sgblack@eecs.umich.edu break; 8277213Sgblack@eecs.umich.edu case 0x3: 8287213Sgblack@eecs.umich.edu if (op2 == 0) { 8297252Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 8307213Sgblack@eecs.umich.edu } 8317213Sgblack@eecs.umich.edu } 8327213Sgblack@eecs.umich.edu } 8337213Sgblack@eecs.umich.edu return new Unknown(machInst); 8347213Sgblack@eecs.umich.edu } 8357213Sgblack@eecs.umich.edu } 8367213Sgblack@eecs.umich.edu ''' 8377213Sgblack@eecs.umich.edu}}; 8387213Sgblack@eecs.umich.edu 8397141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 8407141Sgblack@eecs.umich.edu decode_block = ''' 8417141Sgblack@eecs.umich.edu { 8427141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 8437141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 8447141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 8457141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8467141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 8477141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8487141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 8497141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 8507141Sgblack@eecs.umich.edu case 0x0: // lsl 8517183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8527141Sgblack@eecs.umich.edu case 0x1: // lsr 8537183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8547141Sgblack@eecs.umich.edu case 0x2: // asr 8557183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8567141Sgblack@eecs.umich.edu case 0x3: 8577141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 8587141Sgblack@eecs.umich.edu case 0x0: 8597183Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 8607141Sgblack@eecs.umich.edu case 0x1: 8617183Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 8627141Sgblack@eecs.umich.edu case 0x2: 8637183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 8647141Sgblack@eecs.umich.edu case 0x3: 8657183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 8667141Sgblack@eecs.umich.edu } 8677141Sgblack@eecs.umich.edu case 0x4: 8687183Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 8697141Sgblack@eecs.umich.edu case 0x5: 8707146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 8717141Sgblack@eecs.umich.edu case 0x6: 8727183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 8737141Sgblack@eecs.umich.edu case 0x7: 8747183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 8757141Sgblack@eecs.umich.edu } 8767141Sgblack@eecs.umich.edu } 8777141Sgblack@eecs.umich.edu ''' 8787141Sgblack@eecs.umich.edu}}; 8797141Sgblack@eecs.umich.edu 8807141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 8817141Sgblack@eecs.umich.edu decode_block = ''' 8827141Sgblack@eecs.umich.edu { 8837141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8847141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8857141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 8867141Sgblack@eecs.umich.edu case 0x0: 8877183Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 8887141Sgblack@eecs.umich.edu case 0x1: 8897183Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 8907141Sgblack@eecs.umich.edu case 0x2: //lsl 8917183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 8927141Sgblack@eecs.umich.edu case 0x3: //lsr 8937183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 8947141Sgblack@eecs.umich.edu case 0x4: //asr 8957183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 8967141Sgblack@eecs.umich.edu case 0x5: 8977183Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8987141Sgblack@eecs.umich.edu case 0x6: 8997183Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 9007141Sgblack@eecs.umich.edu case 0x7: // ror 9017183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 9027141Sgblack@eecs.umich.edu case 0x8: 9037183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9047141Sgblack@eecs.umich.edu case 0x9: 9057183Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 9067141Sgblack@eecs.umich.edu case 0xa: 9077183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9087141Sgblack@eecs.umich.edu case 0xb: 9097183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9107141Sgblack@eecs.umich.edu case 0xc: 9117183Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 9127141Sgblack@eecs.umich.edu case 0xd: 9137183Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 9147141Sgblack@eecs.umich.edu case 0xe: 9157183Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 9167141Sgblack@eecs.umich.edu case 0xf: 9177183Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 9187141Sgblack@eecs.umich.edu } 9197141Sgblack@eecs.umich.edu } 9207141Sgblack@eecs.umich.edu ''' 9217141Sgblack@eecs.umich.edu}}; 9227141Sgblack@eecs.umich.edu 9237141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 9247141Sgblack@eecs.umich.edu decode_block = ''' 9257141Sgblack@eecs.umich.edu { 9267141Sgblack@eecs.umich.edu const IntRegIndex rdn = 9277141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 9287141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 9297141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 9307141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 9317141Sgblack@eecs.umich.edu case 0x0: 9327146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 9337141Sgblack@eecs.umich.edu case 0x1: 9347183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9357141Sgblack@eecs.umich.edu case 0x2: 9367146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 9377141Sgblack@eecs.umich.edu case 0x3: 9387154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 9397154Sgblack@eecs.umich.edu return new BxReg(machInst, 9407154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9417154Sgblack@eecs.umich.edu COND_UC); 9427154Sgblack@eecs.umich.edu } else { 9437154Sgblack@eecs.umich.edu return new BlxReg(machInst, 9447154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9457154Sgblack@eecs.umich.edu COND_UC); 9467154Sgblack@eecs.umich.edu } 9477141Sgblack@eecs.umich.edu } 9487141Sgblack@eecs.umich.edu } 9497141Sgblack@eecs.umich.edu ''' 9507141Sgblack@eecs.umich.edu}}; 9517141Sgblack@eecs.umich.edu 9527141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 9537141Sgblack@eecs.umich.edu decode_block = ''' 9547141Sgblack@eecs.umich.edu { 9557141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9567141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9577185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 9587141Sgblack@eecs.umich.edu } 9597141Sgblack@eecs.umich.edu ''' 9607141Sgblack@eecs.umich.edu}}; 9617141Sgblack@eecs.umich.edu 9627141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 9637141Sgblack@eecs.umich.edu decode_block = ''' 9647141Sgblack@eecs.umich.edu { 9657141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9667141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9677146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 9687141Sgblack@eecs.umich.edu } 9697141Sgblack@eecs.umich.edu ''' 9707141Sgblack@eecs.umich.edu}}; 9717141Sgblack@eecs.umich.edu 9727141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 9737141Sgblack@eecs.umich.edu decode_block = ''' 9747141Sgblack@eecs.umich.edu { 9757141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 9767141Sgblack@eecs.umich.edu case 0x0: 9777141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 9787146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 9797141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9807141Sgblack@eecs.umich.edu } else { 9817146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 9827141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9837141Sgblack@eecs.umich.edu } 9847141Sgblack@eecs.umich.edu case 0x1: 9857154Sgblack@eecs.umich.edu return new Cbz(machInst, 9867154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 9877154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 9887154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 9897141Sgblack@eecs.umich.edu case 0x2: 9907235Sgblack@eecs.umich.edu { 9917235Sgblack@eecs.umich.edu const IntRegIndex rd = 9927235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9937235Sgblack@eecs.umich.edu const IntRegIndex rm = 9947235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9957235Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 9967235Sgblack@eecs.umich.edu case 0x0: 9977235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, 0, rm); 9987235Sgblack@eecs.umich.edu case 0x1: 9997235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, 0, rm); 10007235Sgblack@eecs.umich.edu case 0x2: 10017235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, 0, rm); 10027235Sgblack@eecs.umich.edu case 0x3: 10037235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, 0, rm); 10047235Sgblack@eecs.umich.edu } 10057141Sgblack@eecs.umich.edu } 10067141Sgblack@eecs.umich.edu case 0x3: 10077154Sgblack@eecs.umich.edu return new Cbz(machInst, 10087154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10097154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10107154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10117141Sgblack@eecs.umich.edu case 0x4: 10127141Sgblack@eecs.umich.edu case 0x5: 10137201Sgblack@eecs.umich.edu { 10147201Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 10157201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 10167201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 10177201Sgblack@eecs.umich.edu true, false, regList); 10187201Sgblack@eecs.umich.edu } 10197141Sgblack@eecs.umich.edu case 0x6: 10207141Sgblack@eecs.umich.edu { 10217141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 10227141Sgblack@eecs.umich.edu if (opBits == 2) { 10237141Sgblack@eecs.umich.edu return new WarnUnimplemented("setend", machInst); 10247141Sgblack@eecs.umich.edu } else if (opBits == 3) { 10257141Sgblack@eecs.umich.edu return new WarnUnimplemented("cps", machInst); 10267141Sgblack@eecs.umich.edu } 10277141Sgblack@eecs.umich.edu } 10287141Sgblack@eecs.umich.edu case 0x9: 10297154Sgblack@eecs.umich.edu return new Cbnz(machInst, 10307154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10317154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10327154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10337141Sgblack@eecs.umich.edu case 0xa: 10347212Sgblack@eecs.umich.edu { 10357212Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 10367212Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 10377212Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 10387212Sgblack@eecs.umich.edu case 0x0: 10397212Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 10407212Sgblack@eecs.umich.edu case 0x1: 10417212Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 10427212Sgblack@eecs.umich.edu case 0x3: 10437212Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 10447212Sgblack@eecs.umich.edu default: 10457212Sgblack@eecs.umich.edu break; 10467212Sgblack@eecs.umich.edu } 10477141Sgblack@eecs.umich.edu } 10487141Sgblack@eecs.umich.edu break; 10497141Sgblack@eecs.umich.edu case 0xb: 10507154Sgblack@eecs.umich.edu return new Cbnz(machInst, 10517154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10527154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10537154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10547141Sgblack@eecs.umich.edu case 0xc: 10557141Sgblack@eecs.umich.edu case 0xd: 10567201Sgblack@eecs.umich.edu { 10577201Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 10587201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 10597201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 10607201Sgblack@eecs.umich.edu true, true, regList); 10617201Sgblack@eecs.umich.edu } 10627141Sgblack@eecs.umich.edu case 0xe: 10637141Sgblack@eecs.umich.edu return new WarnUnimplemented("bkpt", machInst); 10647141Sgblack@eecs.umich.edu case 0xf: 10657141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 10667141Sgblack@eecs.umich.edu return new WarnUnimplemented("it", machInst); 10677141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 10687141Sgblack@eecs.umich.edu case 0x0: 10697248Sgblack@eecs.umich.edu return new NopInst(machInst); 10707141Sgblack@eecs.umich.edu case 0x1: 10717141Sgblack@eecs.umich.edu return new WarnUnimplemented("yield", machInst); 10727141Sgblack@eecs.umich.edu case 0x2: 10737141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfe", machInst); 10747141Sgblack@eecs.umich.edu case 0x3: 10757141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfi", machInst); 10767141Sgblack@eecs.umich.edu case 0x4: 10777141Sgblack@eecs.umich.edu return new WarnUnimplemented("sev", machInst); 10787141Sgblack@eecs.umich.edu default: 10797141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 10807141Sgblack@eecs.umich.edu } 10817141Sgblack@eecs.umich.edu default: 10827141Sgblack@eecs.umich.edu break; 10837141Sgblack@eecs.umich.edu } 10847141Sgblack@eecs.umich.edu return new Unknown(machInst); 10857141Sgblack@eecs.umich.edu } 10867141Sgblack@eecs.umich.edu ''' 10877141Sgblack@eecs.umich.edu}}; 10887141Sgblack@eecs.umich.edu 10897141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 10907141Sgblack@eecs.umich.edu 10917141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 10927141Sgblack@eecs.umich.edu return ''' 10937141Sgblack@eecs.umich.edu if (s) { 10947146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 10957183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10967141Sgblack@eecs.umich.edu } else { 10977146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 10987183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10997141Sgblack@eecs.umich.edu } 11007141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 11017141Sgblack@eecs.umich.edu 11027141Sgblack@eecs.umich.edu decode_block = ''' 11037141Sgblack@eecs.umich.edu { 11047141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 11057141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 11067141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11077141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11087141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 11097141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 11107183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 11117141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 11127141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 11137141Sgblack@eecs.umich.edu switch (op) { 11147141Sgblack@eecs.umich.edu case 0x0: 11157141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11167141Sgblack@eecs.umich.edu %(tst)s 11177141Sgblack@eecs.umich.edu } else { 11187141Sgblack@eecs.umich.edu %(and)s 11197141Sgblack@eecs.umich.edu } 11207141Sgblack@eecs.umich.edu case 0x1: 11217141Sgblack@eecs.umich.edu %(bic)s 11227141Sgblack@eecs.umich.edu case 0x2: 11237141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 11247141Sgblack@eecs.umich.edu %(mov)s 11257141Sgblack@eecs.umich.edu } else { 11267141Sgblack@eecs.umich.edu %(orr)s 11277141Sgblack@eecs.umich.edu } 11287141Sgblack@eecs.umich.edu case 0x3: 11297141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 11307141Sgblack@eecs.umich.edu %(mvn)s 11317141Sgblack@eecs.umich.edu } else { 11327141Sgblack@eecs.umich.edu %(orn)s 11337141Sgblack@eecs.umich.edu } 11347141Sgblack@eecs.umich.edu case 0x4: 11357141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11367141Sgblack@eecs.umich.edu %(teq)s 11377141Sgblack@eecs.umich.edu } else { 11387141Sgblack@eecs.umich.edu %(eor)s 11397141Sgblack@eecs.umich.edu } 11407141Sgblack@eecs.umich.edu case 0x8: 11417141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11427141Sgblack@eecs.umich.edu %(cmn)s 11437141Sgblack@eecs.umich.edu } else { 11447141Sgblack@eecs.umich.edu %(add)s 11457141Sgblack@eecs.umich.edu } 11467141Sgblack@eecs.umich.edu case 0xa: 11477141Sgblack@eecs.umich.edu %(adc)s 11487141Sgblack@eecs.umich.edu case 0xb: 11497141Sgblack@eecs.umich.edu %(sbc)s 11507141Sgblack@eecs.umich.edu case 0xd: 11517141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11527141Sgblack@eecs.umich.edu %(cmp)s 11537141Sgblack@eecs.umich.edu } else { 11547141Sgblack@eecs.umich.edu %(sub)s 11557141Sgblack@eecs.umich.edu } 11567141Sgblack@eecs.umich.edu case 0xe: 11577141Sgblack@eecs.umich.edu %(rsb)s 11587141Sgblack@eecs.umich.edu default: 11597141Sgblack@eecs.umich.edu return new Unknown(machInst); 11607141Sgblack@eecs.umich.edu } 11617141Sgblack@eecs.umich.edu } 11627141Sgblack@eecs.umich.edu ''' % { 11637141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 11647141Sgblack@eecs.umich.edu "and" : decInst("And"), 11657141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 11667141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 11677141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 11687141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 11697141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 11707141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 11717141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 11727141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 11737141Sgblack@eecs.umich.edu "add" : decInst("Add"), 11747141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 11757141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 11767141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 11777141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 11787141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 11797141Sgblack@eecs.umich.edu } 11807141Sgblack@eecs.umich.edu}}; 11817141Sgblack@eecs.umich.edu 11827157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 11837157Sgblack@eecs.umich.edu decode_block = ''' 11847157Sgblack@eecs.umich.edu { 11857157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 11867157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11877157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11887157Sgblack@eecs.umich.edu switch (op) { 11897157Sgblack@eecs.umich.edu case 0x0: 11907157Sgblack@eecs.umich.edu { 11917157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11927157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11937157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 11947185Sgblack@eecs.umich.edu if (rn == 0xf) { 11957185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 11967185Sgblack@eecs.umich.edu imm, false); 11977185Sgblack@eecs.umich.edu } else { 11987185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 11997185Sgblack@eecs.umich.edu } 12007157Sgblack@eecs.umich.edu } 12017157Sgblack@eecs.umich.edu case 0x4: 12027157Sgblack@eecs.umich.edu { 12037157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12047157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12057157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 12067157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 12077157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 12087157Sgblack@eecs.umich.edu } 12097157Sgblack@eecs.umich.edu case 0xa: 12107157Sgblack@eecs.umich.edu { 12117157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12127157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12137157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 12147185Sgblack@eecs.umich.edu if (rn == 0xf) { 12157185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 12167185Sgblack@eecs.umich.edu imm, false); 12177185Sgblack@eecs.umich.edu } else { 12187185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 12197185Sgblack@eecs.umich.edu } 12207157Sgblack@eecs.umich.edu } 12217157Sgblack@eecs.umich.edu case 0xc: 12227157Sgblack@eecs.umich.edu { 12237157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12247157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12257157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 12267157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 12277157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 12287157Sgblack@eecs.umich.edu } 12297157Sgblack@eecs.umich.edu case 0x12: 12307157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12317227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12327227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 12337157Sgblack@eecs.umich.edu } 12347157Sgblack@eecs.umich.edu // Fall through on purpose... 12357157Sgblack@eecs.umich.edu case 0x10: 12367227Sgblack@eecs.umich.edu { 12377227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12387227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12397227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12407227Sgblack@eecs.umich.edu const ArmShiftType type = 12417227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12427227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 12437227Sgblack@eecs.umich.edu } 12447157Sgblack@eecs.umich.edu case 0x14: 12457256Sgblack@eecs.umich.edu { 12467256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 12477256Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12487256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 4, 0); 12497256Sgblack@eecs.umich.edu return new Sbfx(machInst, rd, rn, lsb, msb); 12507256Sgblack@eecs.umich.edu } 12517157Sgblack@eecs.umich.edu case 0x16: 12527258Sgblack@eecs.umich.edu { 12537258Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 12547258Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12557258Sgblack@eecs.umich.edu const uint32_t msb = bits(machInst, 4, 0); 12567258Sgblack@eecs.umich.edu if (rn == 0xf) { 12577258Sgblack@eecs.umich.edu return new Bfc(machInst, rd, rd, lsb, msb); 12587258Sgblack@eecs.umich.edu } else { 12597258Sgblack@eecs.umich.edu return new Bfi(machInst, rd, rn, lsb, msb); 12607258Sgblack@eecs.umich.edu } 12617157Sgblack@eecs.umich.edu } 12627157Sgblack@eecs.umich.edu case 0x1a: 12637157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12647227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12657227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 12667157Sgblack@eecs.umich.edu } 12677157Sgblack@eecs.umich.edu // Fall through on purpose... 12687157Sgblack@eecs.umich.edu case 0x18: 12697227Sgblack@eecs.umich.edu { 12707227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12717227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12727227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12737227Sgblack@eecs.umich.edu const ArmShiftType type = 12747227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12757227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 12767227Sgblack@eecs.umich.edu } 12777157Sgblack@eecs.umich.edu case 0x1c: 12787256Sgblack@eecs.umich.edu { 12797256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 12807256Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12817256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 4, 0); 12827256Sgblack@eecs.umich.edu return new Ubfx(machInst, rd, rn, lsb, msb); 12837256Sgblack@eecs.umich.edu } 12847157Sgblack@eecs.umich.edu default: 12857157Sgblack@eecs.umich.edu return new Unknown(machInst); 12867157Sgblack@eecs.umich.edu } 12877157Sgblack@eecs.umich.edu } 12887157Sgblack@eecs.umich.edu ''' 12897157Sgblack@eecs.umich.edu}}; 12907157Sgblack@eecs.umich.edu 12917141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 12927141Sgblack@eecs.umich.edu 12937141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 12947141Sgblack@eecs.umich.edu return ''' 12957141Sgblack@eecs.umich.edu if (s) { 12967146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 12977141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12987141Sgblack@eecs.umich.edu } else { 12997146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 13007141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 13017141Sgblack@eecs.umich.edu } 13027141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 13037141Sgblack@eecs.umich.edu 13047141Sgblack@eecs.umich.edu decode_block = ''' 13057141Sgblack@eecs.umich.edu { 13067141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 13077141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 13087141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 13097141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 13107141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 13117141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 13127141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 13137141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 13147141Sgblack@eecs.umich.edu switch (op) { 13157141Sgblack@eecs.umich.edu case 0x0: 13167141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13177141Sgblack@eecs.umich.edu %(tst)s 13187141Sgblack@eecs.umich.edu } else { 13197141Sgblack@eecs.umich.edu %(and)s 13207141Sgblack@eecs.umich.edu } 13217141Sgblack@eecs.umich.edu case 0x1: 13227141Sgblack@eecs.umich.edu %(bic)s 13237141Sgblack@eecs.umich.edu case 0x2: 13247141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13257141Sgblack@eecs.umich.edu %(mov)s 13267141Sgblack@eecs.umich.edu } else { 13277141Sgblack@eecs.umich.edu %(orr)s 13287141Sgblack@eecs.umich.edu } 13297141Sgblack@eecs.umich.edu case 0x3: 13307141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13317141Sgblack@eecs.umich.edu %(mvn)s 13327141Sgblack@eecs.umich.edu } else { 13337141Sgblack@eecs.umich.edu %(orn)s 13347141Sgblack@eecs.umich.edu } 13357141Sgblack@eecs.umich.edu case 0x4: 13367141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13377141Sgblack@eecs.umich.edu %(teq)s 13387141Sgblack@eecs.umich.edu } else { 13397141Sgblack@eecs.umich.edu %(eor)s 13407141Sgblack@eecs.umich.edu } 13417141Sgblack@eecs.umich.edu case 0x6: 13427237Sgblack@eecs.umich.edu if (type) { 13437237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, rn, rm, amt, type); 13447237Sgblack@eecs.umich.edu } else { 13457237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, rn, rm, amt, type); 13467237Sgblack@eecs.umich.edu } 13477141Sgblack@eecs.umich.edu case 0x8: 13487141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13497141Sgblack@eecs.umich.edu %(cmn)s 13507141Sgblack@eecs.umich.edu } else { 13517141Sgblack@eecs.umich.edu %(add)s 13527141Sgblack@eecs.umich.edu } 13537141Sgblack@eecs.umich.edu case 0xa: 13547141Sgblack@eecs.umich.edu %(adc)s 13557141Sgblack@eecs.umich.edu case 0xb: 13567141Sgblack@eecs.umich.edu %(sbc)s 13577141Sgblack@eecs.umich.edu case 0xd: 13587141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13597141Sgblack@eecs.umich.edu %(cmp)s 13607141Sgblack@eecs.umich.edu } else { 13617141Sgblack@eecs.umich.edu %(sub)s 13627141Sgblack@eecs.umich.edu } 13637141Sgblack@eecs.umich.edu case 0xe: 13647141Sgblack@eecs.umich.edu %(rsb)s 13657141Sgblack@eecs.umich.edu default: 13667141Sgblack@eecs.umich.edu return new Unknown(machInst); 13677141Sgblack@eecs.umich.edu } 13687141Sgblack@eecs.umich.edu } 13697141Sgblack@eecs.umich.edu ''' % { 13707141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 13717141Sgblack@eecs.umich.edu "and" : decInst("And"), 13727141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 13737141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 13747141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 13757141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 13767141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 13777141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 13787141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 13797141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 13807141Sgblack@eecs.umich.edu "add" : decInst("Add"), 13817141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 13827141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 13837141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 13847141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 13857141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 13867141Sgblack@eecs.umich.edu } 13877141Sgblack@eecs.umich.edu}}; 1388