data.isa revision 7255
17139Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387255Sgblack@eecs.umich.edudef format ArmMiscMedia() {{ 397243Sgblack@eecs.umich.edu decode_block = ''' 407243Sgblack@eecs.umich.edu { 417255Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 427255Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 437243Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 447243Sgblack@eecs.umich.edu const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 457255Sgblack@eecs.umich.edu if (op1 == 0 && op2 == 0) { 467255Sgblack@eecs.umich.edu const IntRegIndex rd = 477255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 487255Sgblack@eecs.umich.edu const IntRegIndex rm = 497255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 507255Sgblack@eecs.umich.edu if (ra == 0xf) { 517255Sgblack@eecs.umich.edu return new Usad8(machInst, rd, rn, rm); 527255Sgblack@eecs.umich.edu } else { 537255Sgblack@eecs.umich.edu return new Usada8(machInst, rd, rn, rm, ra); 547255Sgblack@eecs.umich.edu } 557255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x2) { 567255Sgblack@eecs.umich.edu if (bits(op1, 2, 1) == 0x3) { 577255Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 587255Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 0x1) { 597255Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 607255Sgblack@eecs.umich.edu } 617255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 627255Sgblack@eecs.umich.edu if (rn == 0xf) { 637255Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 647255Sgblack@eecs.umich.edu } else { 657255Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 667255Sgblack@eecs.umich.edu } 677243Sgblack@eecs.umich.edu } 687255Sgblack@eecs.umich.edu return new Unknown(machInst); 697243Sgblack@eecs.umich.edu } 707243Sgblack@eecs.umich.edu ''' 717243Sgblack@eecs.umich.edu}}; 727243Sgblack@eecs.umich.edu 737139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 747188Sgblack@eecs.umich.edu pclr = ''' 757188Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 767188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 777188Sgblack@eecs.umich.edu type); 787188Sgblack@eecs.umich.edu ''' 797139Sgblack@eecs.umich.edu instDecode = ''' 807139Sgblack@eecs.umich.edu case %(opcode)#x: 817139Sgblack@eecs.umich.edu if (immShift) { 827139Sgblack@eecs.umich.edu if (setCc) { 837188Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 847188Sgblack@eecs.umich.edu %(pclr)s 857188Sgblack@eecs.umich.edu } else { 867188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 877188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 887188Sgblack@eecs.umich.edu } 897139Sgblack@eecs.umich.edu } else { 907146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 917141Sgblack@eecs.umich.edu rm, imm5, type); 927139Sgblack@eecs.umich.edu } 937139Sgblack@eecs.umich.edu } else { 947139Sgblack@eecs.umich.edu if (setCc) { 957146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 967141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 977139Sgblack@eecs.umich.edu } else { 987146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 997141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1007139Sgblack@eecs.umich.edu } 1017139Sgblack@eecs.umich.edu } 1027139Sgblack@eecs.umich.edu break; 1037139Sgblack@eecs.umich.edu ''' 1047139Sgblack@eecs.umich.edu 1057188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 1067188Sgblack@eecs.umich.edu global pclr 1077188Sgblack@eecs.umich.edu if useDest: 1087188Sgblack@eecs.umich.edu dest = "rd" 1097188Sgblack@eecs.umich.edu else: 1107188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 1117188Sgblack@eecs.umich.edu if useOp1: 1127188Sgblack@eecs.umich.edu op1 = "rn" 1137188Sgblack@eecs.umich.edu else: 1147188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 1157188Sgblack@eecs.umich.edu global instDecode, pclrCode 1167188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1177188Sgblack@eecs.umich.edu "opcode": opcode, 1187188Sgblack@eecs.umich.edu "dest": dest, 1197188Sgblack@eecs.umich.edu "op1": op1 } 1207188Sgblack@eecs.umich.edu if useDest: 1217188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1227188Sgblack@eecs.umich.edu else: 1237188Sgblack@eecs.umich.edu substDict["pclr"] = "" 1247188Sgblack@eecs.umich.edu return instDecode % substDict 1257139Sgblack@eecs.umich.edu 1267139Sgblack@eecs.umich.edu decode_block = ''' 1277139Sgblack@eecs.umich.edu { 1287139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 1297139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 1307139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 1317139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1327139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 1337139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 1347139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1357139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1367139Sgblack@eecs.umich.edu switch (OPCODE) { 1377139Sgblack@eecs.umich.edu ''' 1387139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1397139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1407139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1417139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1427139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1437139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1447139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1457139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1467188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1477188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1487188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1497188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1507139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1517188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1527139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1537188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1547139Sgblack@eecs.umich.edu decode_block += ''' 1557139Sgblack@eecs.umich.edu default: 1567139Sgblack@eecs.umich.edu return new Unknown(machInst); 1577139Sgblack@eecs.umich.edu } 1587139Sgblack@eecs.umich.edu } 1597139Sgblack@eecs.umich.edu ''' 1607139Sgblack@eecs.umich.edu}}; 1617139Sgblack@eecs.umich.edu 1627210Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1637210Sgblack@eecs.umich.edu decode_block = ''' 1647210Sgblack@eecs.umich.edu { 1657210Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1667210Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1677210Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1687210Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1697227Sgblack@eecs.umich.edu const IntRegIndex rn = 1707227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1717227Sgblack@eecs.umich.edu const IntRegIndex rd = 1727227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1737227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1747227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 11, 7); 1757227Sgblack@eecs.umich.edu const ArmShiftType type = 1767227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1777210Sgblack@eecs.umich.edu if (op1 == 0) { 1787237Sgblack@eecs.umich.edu if (type) { 1797237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, (IntRegIndex)a, 1807237Sgblack@eecs.umich.edu rn, imm, type); 1817237Sgblack@eecs.umich.edu } else { 1827237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, (IntRegIndex)a, 1837237Sgblack@eecs.umich.edu rn, imm, type); 1847237Sgblack@eecs.umich.edu } 1857210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1867227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1877210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1887227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 1897210Sgblack@eecs.umich.edu } 1907210Sgblack@eecs.umich.edu return new Unknown(machInst); 1917210Sgblack@eecs.umich.edu } 1927210Sgblack@eecs.umich.edu switch (op1) { 1937210Sgblack@eecs.umich.edu case 0x0: 1947240Sgblack@eecs.umich.edu { 1957235Sgblack@eecs.umich.edu const IntRegIndex rn = 1967235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1977235Sgblack@eecs.umich.edu const IntRegIndex rd = 1987235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1997235Sgblack@eecs.umich.edu const IntRegIndex rm = 2007235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2017240Sgblack@eecs.umich.edu if (op2 == 0x3) { 2027240Sgblack@eecs.umich.edu const uint32_t rotation = 2037240Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2047240Sgblack@eecs.umich.edu if (a == 0xf) { 2057240Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 2067240Sgblack@eecs.umich.edu } else { 2077240Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 2087240Sgblack@eecs.umich.edu } 2097240Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2107240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 2117210Sgblack@eecs.umich.edu } 2127210Sgblack@eecs.umich.edu } 2137210Sgblack@eecs.umich.edu break; 2147210Sgblack@eecs.umich.edu case 0x2: 2157210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2167227Sgblack@eecs.umich.edu const IntRegIndex rn = 2177227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2187227Sgblack@eecs.umich.edu const IntRegIndex rd = 2197227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2207227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2217227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 2227210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2237235Sgblack@eecs.umich.edu const IntRegIndex rn = 2247235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2257235Sgblack@eecs.umich.edu const IntRegIndex rd = 2267235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2277235Sgblack@eecs.umich.edu const IntRegIndex rm = 2287235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2297235Sgblack@eecs.umich.edu const uint32_t rotation = 2307235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2317210Sgblack@eecs.umich.edu if (a == 0xf) { 2327235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 2337210Sgblack@eecs.umich.edu } else { 2347235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 2357210Sgblack@eecs.umich.edu } 2367210Sgblack@eecs.umich.edu } 2377210Sgblack@eecs.umich.edu break; 2387210Sgblack@eecs.umich.edu case 0x3: 2397210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2407211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2417211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2427211Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 2437210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2447235Sgblack@eecs.umich.edu const IntRegIndex rn = 2457235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2467235Sgblack@eecs.umich.edu const IntRegIndex rd = 2477235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2487235Sgblack@eecs.umich.edu const IntRegIndex rm = 2497235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2507235Sgblack@eecs.umich.edu const uint32_t rotation = 2517235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2527210Sgblack@eecs.umich.edu if (a == 0xf) { 2537235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 2547210Sgblack@eecs.umich.edu } else { 2557235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 2567210Sgblack@eecs.umich.edu } 2577210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2587211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2597211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2607211Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 2617210Sgblack@eecs.umich.edu } 2627210Sgblack@eecs.umich.edu break; 2637210Sgblack@eecs.umich.edu case 0x4: 2647210Sgblack@eecs.umich.edu if (op2 == 0x3) { 2657235Sgblack@eecs.umich.edu const IntRegIndex rn = 2667235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2677235Sgblack@eecs.umich.edu const IntRegIndex rd = 2687235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2697235Sgblack@eecs.umich.edu const IntRegIndex rm = 2707235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2717235Sgblack@eecs.umich.edu const uint32_t rotation = 2727235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2737210Sgblack@eecs.umich.edu if (a == 0xf) { 2747235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 2757210Sgblack@eecs.umich.edu } else { 2767235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 2777210Sgblack@eecs.umich.edu } 2787210Sgblack@eecs.umich.edu } 2797210Sgblack@eecs.umich.edu break; 2807210Sgblack@eecs.umich.edu case 0x6: 2817210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2827227Sgblack@eecs.umich.edu const IntRegIndex rn = 2837227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2847227Sgblack@eecs.umich.edu const IntRegIndex rd = 2857227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2867227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2877227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 2887210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2897235Sgblack@eecs.umich.edu const IntRegIndex rn = 2907235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2917235Sgblack@eecs.umich.edu const IntRegIndex rd = 2927235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2937235Sgblack@eecs.umich.edu const IntRegIndex rm = 2947235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2957235Sgblack@eecs.umich.edu const uint32_t rotation = 2967235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2977210Sgblack@eecs.umich.edu if (a == 0xf) { 2987235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 2997210Sgblack@eecs.umich.edu } else { 3007235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 3017210Sgblack@eecs.umich.edu } 3027210Sgblack@eecs.umich.edu } 3037210Sgblack@eecs.umich.edu break; 3047210Sgblack@eecs.umich.edu case 0x7: 3057250Sgblack@eecs.umich.edu { 3067235Sgblack@eecs.umich.edu const IntRegIndex rn = 3077235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3087235Sgblack@eecs.umich.edu const IntRegIndex rd = 3097235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3107235Sgblack@eecs.umich.edu const IntRegIndex rm = 3117235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3127250Sgblack@eecs.umich.edu if (op2 == 0x1) { 3137250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 3147250Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 3157250Sgblack@eecs.umich.edu const uint32_t rotation = 3167250Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3177250Sgblack@eecs.umich.edu if (a == 0xf) { 3187250Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 3197250Sgblack@eecs.umich.edu } else { 3207250Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 3217250Sgblack@eecs.umich.edu } 3227250Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 3237250Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 3247210Sgblack@eecs.umich.edu } 3257210Sgblack@eecs.umich.edu } 3267210Sgblack@eecs.umich.edu break; 3277210Sgblack@eecs.umich.edu } 3287210Sgblack@eecs.umich.edu return new Unknown(machInst); 3297210Sgblack@eecs.umich.edu } 3307210Sgblack@eecs.umich.edu ''' 3317210Sgblack@eecs.umich.edu}}; 3327210Sgblack@eecs.umich.edu 3337194Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 3347194Sgblack@eecs.umich.edu decode_block=''' 3357194Sgblack@eecs.umich.edu { 3367194Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 3377194Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 3387194Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3397194Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3407194Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3417194Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 3427194Sgblack@eecs.umich.edu switch (op1) { 3437194Sgblack@eecs.umich.edu case 0x1: 3447194Sgblack@eecs.umich.edu switch (op2) { 3457194Sgblack@eecs.umich.edu case 0x0: 3467216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3477194Sgblack@eecs.umich.edu case 0x1: 3487224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 3497194Sgblack@eecs.umich.edu case 0x2: 3507224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3517194Sgblack@eecs.umich.edu case 0x3: 3527218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 3537194Sgblack@eecs.umich.edu case 0x4: 3547216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3557194Sgblack@eecs.umich.edu case 0x7: 3567218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 3577194Sgblack@eecs.umich.edu } 3587194Sgblack@eecs.umich.edu break; 3597194Sgblack@eecs.umich.edu case 0x2: 3607194Sgblack@eecs.umich.edu switch (op2) { 3617194Sgblack@eecs.umich.edu case 0x0: 3627194Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 3637194Sgblack@eecs.umich.edu case 0x1: 3647194Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 3657194Sgblack@eecs.umich.edu case 0x2: 3667194Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 3677194Sgblack@eecs.umich.edu case 0x3: 3687194Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 3697194Sgblack@eecs.umich.edu case 0x4: 3707194Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 3717194Sgblack@eecs.umich.edu case 0x7: 3727194Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 3737194Sgblack@eecs.umich.edu } 3747194Sgblack@eecs.umich.edu break; 3757194Sgblack@eecs.umich.edu case 0x3: 3767194Sgblack@eecs.umich.edu switch (op2) { 3777194Sgblack@eecs.umich.edu case 0x0: 3787231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 3797194Sgblack@eecs.umich.edu case 0x1: 3807231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 3817194Sgblack@eecs.umich.edu case 0x2: 3827231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 3837194Sgblack@eecs.umich.edu case 0x3: 3847231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 3857194Sgblack@eecs.umich.edu case 0x4: 3867231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 3877194Sgblack@eecs.umich.edu case 0x7: 3887231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 3897194Sgblack@eecs.umich.edu } 3907194Sgblack@eecs.umich.edu break; 3917194Sgblack@eecs.umich.edu } 3927194Sgblack@eecs.umich.edu } else { 3937194Sgblack@eecs.umich.edu switch (op1) { 3947194Sgblack@eecs.umich.edu case 0x1: 3957194Sgblack@eecs.umich.edu switch (op2) { 3967194Sgblack@eecs.umich.edu case 0x0: 3977222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3987194Sgblack@eecs.umich.edu case 0x1: 3997222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 4007194Sgblack@eecs.umich.edu case 0x2: 4017222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 4027194Sgblack@eecs.umich.edu case 0x3: 4037222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 4047194Sgblack@eecs.umich.edu case 0x4: 4057222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 4067194Sgblack@eecs.umich.edu case 0x7: 4077222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 4087194Sgblack@eecs.umich.edu } 4097194Sgblack@eecs.umich.edu break; 4107194Sgblack@eecs.umich.edu case 0x2: 4117194Sgblack@eecs.umich.edu switch (op2) { 4127194Sgblack@eecs.umich.edu case 0x0: 4137220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 4147194Sgblack@eecs.umich.edu case 0x1: 4157220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 4167194Sgblack@eecs.umich.edu case 0x2: 4177220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 4187194Sgblack@eecs.umich.edu case 0x3: 4197220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 4207194Sgblack@eecs.umich.edu case 0x4: 4217220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 4227194Sgblack@eecs.umich.edu case 0x7: 4237220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 4247194Sgblack@eecs.umich.edu } 4257194Sgblack@eecs.umich.edu break; 4267194Sgblack@eecs.umich.edu case 0x3: 4277194Sgblack@eecs.umich.edu switch (op2) { 4287194Sgblack@eecs.umich.edu case 0x0: 4297231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 4307194Sgblack@eecs.umich.edu case 0x1: 4317231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 4327194Sgblack@eecs.umich.edu case 0x2: 4337231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 4347194Sgblack@eecs.umich.edu case 0x3: 4357231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 4367194Sgblack@eecs.umich.edu case 0x4: 4377231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 4387194Sgblack@eecs.umich.edu case 0x7: 4397231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 4407194Sgblack@eecs.umich.edu } 4417194Sgblack@eecs.umich.edu break; 4427194Sgblack@eecs.umich.edu } 4437194Sgblack@eecs.umich.edu } 4447194Sgblack@eecs.umich.edu return new Unknown(machInst); 4457194Sgblack@eecs.umich.edu } 4467194Sgblack@eecs.umich.edu ''' 4477194Sgblack@eecs.umich.edu}}; 4487194Sgblack@eecs.umich.edu 4497139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 4507188Sgblack@eecs.umich.edu pclr = ''' 4517188Sgblack@eecs.umich.edu return new %(className)ssImmPclr(machInst, %(dest)s, 4527188Sgblack@eecs.umich.edu %(op1)s, imm, false); 4537188Sgblack@eecs.umich.edu ''' 4547188Sgblack@eecs.umich.edu adr = ''' 4557188Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 4567188Sgblack@eecs.umich.edu imm, false); 4577188Sgblack@eecs.umich.edu ''' 4587139Sgblack@eecs.umich.edu instDecode = ''' 4597188Sgblack@eecs.umich.edu case %(opcode)#x: 4607139Sgblack@eecs.umich.edu if (setCc) { 4617188Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 4627188Sgblack@eecs.umich.edu %(pclr)s 4637188Sgblack@eecs.umich.edu } else { 4647188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 4657188Sgblack@eecs.umich.edu imm, rotC); 4667188Sgblack@eecs.umich.edu } 4677139Sgblack@eecs.umich.edu } else { 4687188Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 4697188Sgblack@eecs.umich.edu %(adr)s 4707188Sgblack@eecs.umich.edu } else { 4717188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 4727188Sgblack@eecs.umich.edu imm, rotC); 4737188Sgblack@eecs.umich.edu } 4747139Sgblack@eecs.umich.edu } 4757139Sgblack@eecs.umich.edu break; 4767139Sgblack@eecs.umich.edu ''' 4777139Sgblack@eecs.umich.edu 4787188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 4797188Sgblack@eecs.umich.edu global instDecode, pclr, adr 4807188Sgblack@eecs.umich.edu if useDest: 4817188Sgblack@eecs.umich.edu dest = "rd" 4827188Sgblack@eecs.umich.edu else: 4837188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 4847188Sgblack@eecs.umich.edu if useOp1: 4857188Sgblack@eecs.umich.edu op1 = "rn" 4867188Sgblack@eecs.umich.edu else: 4877188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 4887188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4897188Sgblack@eecs.umich.edu "opcode": opcode, 4907188Sgblack@eecs.umich.edu "dest": dest, 4917188Sgblack@eecs.umich.edu "op1": op1, 4927188Sgblack@eecs.umich.edu "adr": "", 4937188Sgblack@eecs.umich.edu "adrInst": "false" } 4947188Sgblack@eecs.umich.edu if useDest: 4957188Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 4967188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 4977188Sgblack@eecs.umich.edu else: 4987188Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 4997188Sgblack@eecs.umich.edu substDict["pclr"] = "" 5007188Sgblack@eecs.umich.edu return instDecode % substDict 5017185Sgblack@eecs.umich.edu 5027188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 5037188Sgblack@eecs.umich.edu global instDecode, pclr, adr 5047188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 5057188Sgblack@eecs.umich.edu "opcode": opcode, 5067188Sgblack@eecs.umich.edu "dest": "rd", 5077188Sgblack@eecs.umich.edu "op1": "rn", 5087188Sgblack@eecs.umich.edu "add": add, 5097188Sgblack@eecs.umich.edu "pclrInst": "true", 5107188Sgblack@eecs.umich.edu "adrInst": "true" } 5117188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5127188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 5137188Sgblack@eecs.umich.edu return instDecode % substDict 5147139Sgblack@eecs.umich.edu 5157139Sgblack@eecs.umich.edu decode_block = ''' 5167139Sgblack@eecs.umich.edu { 5177139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 5187139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 5197139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 5207139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 5217139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 5227139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 5237139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 5247139Sgblack@eecs.umich.edu switch (OPCODE) { 5257139Sgblack@eecs.umich.edu ''' 5267139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 5277139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 5287185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 5297139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 5307185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 5317139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 5327139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 5337139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 5347188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 5357188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 5367188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 5377188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 5387139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 5397188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 5407139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 5417188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 5427139Sgblack@eecs.umich.edu decode_block += ''' 5437139Sgblack@eecs.umich.edu default: 5447139Sgblack@eecs.umich.edu return new Unknown(machInst); 5457139Sgblack@eecs.umich.edu } 5467139Sgblack@eecs.umich.edu } 5477139Sgblack@eecs.umich.edu ''' 5487139Sgblack@eecs.umich.edu}}; 5497141Sgblack@eecs.umich.edu 5507195Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 5517195Sgblack@eecs.umich.edu decode_block = ''' 5527195Sgblack@eecs.umich.edu { 5537195Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5547195Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 5557195Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5567195Sgblack@eecs.umich.edu switch (OPCODE) { 5577195Sgblack@eecs.umich.edu case 0x8: 5587195Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 5597195Sgblack@eecs.umich.edu case 0x9: 5607195Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 5617195Sgblack@eecs.umich.edu case 0xa: 5627195Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 5637195Sgblack@eecs.umich.edu case 0xb: 5647195Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 5657195Sgblack@eecs.umich.edu default: 5667195Sgblack@eecs.umich.edu return new Unknown(machInst); 5677195Sgblack@eecs.umich.edu } 5687195Sgblack@eecs.umich.edu } 5697195Sgblack@eecs.umich.edu ''' 5707195Sgblack@eecs.umich.edu}}; 5717195Sgblack@eecs.umich.edu 5727213Sgblack@eecs.umich.edudef format Thumb32DataProcReg() {{ 5737213Sgblack@eecs.umich.edu decode_block = ''' 5747213Sgblack@eecs.umich.edu { 5757213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 23, 20); 5767213Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5777213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 5787213Sgblack@eecs.umich.edu if (bits(op1, 3) != 1) { 5797213Sgblack@eecs.umich.edu if (op2 == 0) { 5807213Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5817213Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5827213Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5837213Sgblack@eecs.umich.edu case 0x0: 5847213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5857213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5867213Sgblack@eecs.umich.edu case 0x1: 5877213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5887213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5897213Sgblack@eecs.umich.edu case 0x2: 5907213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5917213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5927213Sgblack@eecs.umich.edu case 0x3: 5937213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5947213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5957213Sgblack@eecs.umich.edu case 0x4: 5967213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5977213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 5987213Sgblack@eecs.umich.edu case 0x5: 5997213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6007213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6017213Sgblack@eecs.umich.edu case 0x6: 6027213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6037213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6047213Sgblack@eecs.umich.edu case 0x7: 6057213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6067213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6077213Sgblack@eecs.umich.edu } 6087213Sgblack@eecs.umich.edu } 6097235Sgblack@eecs.umich.edu { 6107235Sgblack@eecs.umich.edu const IntRegIndex rd = 6117235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6127235Sgblack@eecs.umich.edu const IntRegIndex rm = 6137235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6147235Sgblack@eecs.umich.edu const uint32_t rotation = 6157235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 5, 4) << 3; 6167235Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 6177235Sgblack@eecs.umich.edu case 0x0: 6187235Sgblack@eecs.umich.edu if (rn == 0xf) { 6197235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 6207235Sgblack@eecs.umich.edu } else { 6217235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 6227235Sgblack@eecs.umich.edu } 6237235Sgblack@eecs.umich.edu case 0x1: 6247235Sgblack@eecs.umich.edu if (rn == 0xf) { 6257235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 6267235Sgblack@eecs.umich.edu } else { 6277235Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 6287235Sgblack@eecs.umich.edu } 6297235Sgblack@eecs.umich.edu case 0x2: 6307235Sgblack@eecs.umich.edu if (rn == 0xf) { 6317235Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 6327235Sgblack@eecs.umich.edu } else { 6337235Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 6347235Sgblack@eecs.umich.edu } 6357235Sgblack@eecs.umich.edu case 0x3: 6367235Sgblack@eecs.umich.edu if (rn == 0xf) { 6377235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 6387235Sgblack@eecs.umich.edu } else { 6397235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 6407235Sgblack@eecs.umich.edu } 6417235Sgblack@eecs.umich.edu case 0x4: 6427235Sgblack@eecs.umich.edu if (rn == 0xf) { 6437235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 6447235Sgblack@eecs.umich.edu } else { 6457235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 6467235Sgblack@eecs.umich.edu } 6477235Sgblack@eecs.umich.edu case 0x5: 6487235Sgblack@eecs.umich.edu if (rn == 0xf) { 6497235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 6507235Sgblack@eecs.umich.edu } else { 6517235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 6527235Sgblack@eecs.umich.edu } 6537235Sgblack@eecs.umich.edu default: 6547235Sgblack@eecs.umich.edu return new Unknown(machInst); 6557213Sgblack@eecs.umich.edu } 6567213Sgblack@eecs.umich.edu } 6577213Sgblack@eecs.umich.edu } else { 6587213Sgblack@eecs.umich.edu if (bits(op2, 3) == 0) { 6597220Sgblack@eecs.umich.edu const IntRegIndex rd = 6607220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6617220Sgblack@eecs.umich.edu const IntRegIndex rm = 6627220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6637213Sgblack@eecs.umich.edu if (bits(op2, 2) == 0x0) { 6647213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6657213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6667213Sgblack@eecs.umich.edu switch (op2) { 6677213Sgblack@eecs.umich.edu case 0x0: 6687213Sgblack@eecs.umich.edu switch (op1) { 6697213Sgblack@eecs.umich.edu case 0x1: 6707216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, 6717216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6727213Sgblack@eecs.umich.edu case 0x2: 6737224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, 6747224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6757213Sgblack@eecs.umich.edu case 0x6: 6767224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, 6777224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6787213Sgblack@eecs.umich.edu case 0x5: 6797218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, 6807218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6817213Sgblack@eecs.umich.edu case 0x0: 6827216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, 6837216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6847213Sgblack@eecs.umich.edu case 0x4: 6857218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, 6867218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6877213Sgblack@eecs.umich.edu } 6887213Sgblack@eecs.umich.edu break; 6897213Sgblack@eecs.umich.edu case 0x1: 6907216Sgblack@eecs.umich.edu switch (op1) { 6917216Sgblack@eecs.umich.edu case 0x1: 6927216Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 6937216Sgblack@eecs.umich.edu case 0x2: 6947216Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 6957216Sgblack@eecs.umich.edu case 0x6: 6967216Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 6977216Sgblack@eecs.umich.edu case 0x5: 6987216Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 6997216Sgblack@eecs.umich.edu case 0x0: 7007216Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 7017216Sgblack@eecs.umich.edu case 0x4: 7027216Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 7037213Sgblack@eecs.umich.edu } 7047213Sgblack@eecs.umich.edu break; 7057213Sgblack@eecs.umich.edu case 0x2: 7067213Sgblack@eecs.umich.edu switch (op1) { 7077213Sgblack@eecs.umich.edu case 0x1: 7087231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 7097213Sgblack@eecs.umich.edu case 0x2: 7107231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 7117213Sgblack@eecs.umich.edu case 0x6: 7127231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 7137213Sgblack@eecs.umich.edu case 0x5: 7147231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 7157213Sgblack@eecs.umich.edu case 0x0: 7167231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 7177213Sgblack@eecs.umich.edu case 0x4: 7187231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 7197213Sgblack@eecs.umich.edu } 7207213Sgblack@eecs.umich.edu break; 7217213Sgblack@eecs.umich.edu } 7227213Sgblack@eecs.umich.edu } else { 7237213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 7247213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7257213Sgblack@eecs.umich.edu switch (op2) { 7267213Sgblack@eecs.umich.edu case 0x0: 7277213Sgblack@eecs.umich.edu switch (op1) { 7287213Sgblack@eecs.umich.edu case 0x1: 7297222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, 7307222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7317213Sgblack@eecs.umich.edu case 0x2: 7327222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, 7337222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7347213Sgblack@eecs.umich.edu case 0x6: 7357222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, 7367222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7377213Sgblack@eecs.umich.edu case 0x5: 7387222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, 7397222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7407213Sgblack@eecs.umich.edu case 0x0: 7417222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, 7427222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7437213Sgblack@eecs.umich.edu case 0x4: 7447222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, 7457222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7467213Sgblack@eecs.umich.edu } 7477213Sgblack@eecs.umich.edu break; 7487213Sgblack@eecs.umich.edu case 0x1: 7497213Sgblack@eecs.umich.edu switch (op1) { 7507213Sgblack@eecs.umich.edu case 0x1: 7517220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 7527213Sgblack@eecs.umich.edu case 0x2: 7537220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 7547213Sgblack@eecs.umich.edu case 0x6: 7557220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 7567213Sgblack@eecs.umich.edu case 0x5: 7577220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 7587213Sgblack@eecs.umich.edu case 0x0: 7597220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 7607213Sgblack@eecs.umich.edu case 0x4: 7617220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 7627213Sgblack@eecs.umich.edu } 7637213Sgblack@eecs.umich.edu break; 7647213Sgblack@eecs.umich.edu case 0x2: 7657213Sgblack@eecs.umich.edu switch (op1) { 7667213Sgblack@eecs.umich.edu case 0x1: 7677231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 7687213Sgblack@eecs.umich.edu case 0x2: 7697231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 7707213Sgblack@eecs.umich.edu case 0x6: 7717231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 7727213Sgblack@eecs.umich.edu case 0x5: 7737231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 7747213Sgblack@eecs.umich.edu case 0x0: 7757231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 7767213Sgblack@eecs.umich.edu case 0x4: 7777231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 7787213Sgblack@eecs.umich.edu } 7797213Sgblack@eecs.umich.edu break; 7807213Sgblack@eecs.umich.edu } 7817213Sgblack@eecs.umich.edu } 7827213Sgblack@eecs.umich.edu } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 7837213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 7847213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7857240Sgblack@eecs.umich.edu const IntRegIndex rd = 7867240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7877240Sgblack@eecs.umich.edu const IntRegIndex rm = 7887240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 7897213Sgblack@eecs.umich.edu switch (op1) { 7907213Sgblack@eecs.umich.edu case 0x0: 7917240Sgblack@eecs.umich.edu switch (op2) { 7927240Sgblack@eecs.umich.edu case 0x0: 7937240Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, 7947240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7957240Sgblack@eecs.umich.edu case 0x1: 7967240Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, 7977240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 7987240Sgblack@eecs.umich.edu case 0x2: 7997240Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, 8007240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8017240Sgblack@eecs.umich.edu case 0x3: 8027240Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, 8037240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8047213Sgblack@eecs.umich.edu } 8057213Sgblack@eecs.umich.edu break; 8067213Sgblack@eecs.umich.edu case 0x1: 8077240Sgblack@eecs.umich.edu switch (op2) { 8087240Sgblack@eecs.umich.edu case 0x0: 8097240Sgblack@eecs.umich.edu return new Rev(machInst, rd, rn); 8107240Sgblack@eecs.umich.edu case 0x1: 8117240Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rn); 8127240Sgblack@eecs.umich.edu case 0x2: 8137250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 8147240Sgblack@eecs.umich.edu case 0x3: 8157240Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rn); 8167213Sgblack@eecs.umich.edu } 8177213Sgblack@eecs.umich.edu break; 8187213Sgblack@eecs.umich.edu case 0x2: 8197213Sgblack@eecs.umich.edu if (op2 == 0) { 8207240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 8217213Sgblack@eecs.umich.edu } 8227213Sgblack@eecs.umich.edu break; 8237213Sgblack@eecs.umich.edu case 0x3: 8247213Sgblack@eecs.umich.edu if (op2 == 0) { 8257252Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 8267213Sgblack@eecs.umich.edu } 8277213Sgblack@eecs.umich.edu } 8287213Sgblack@eecs.umich.edu } 8297213Sgblack@eecs.umich.edu return new Unknown(machInst); 8307213Sgblack@eecs.umich.edu } 8317213Sgblack@eecs.umich.edu } 8327213Sgblack@eecs.umich.edu ''' 8337213Sgblack@eecs.umich.edu}}; 8347213Sgblack@eecs.umich.edu 8357141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 8367141Sgblack@eecs.umich.edu decode_block = ''' 8377141Sgblack@eecs.umich.edu { 8387141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 8397141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 8407141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 8417141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8427141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 8437141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8447141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 8457141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 8467141Sgblack@eecs.umich.edu case 0x0: // lsl 8477183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8487141Sgblack@eecs.umich.edu case 0x1: // lsr 8497183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8507141Sgblack@eecs.umich.edu case 0x2: // asr 8517183Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8527141Sgblack@eecs.umich.edu case 0x3: 8537141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 8547141Sgblack@eecs.umich.edu case 0x0: 8557183Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 8567141Sgblack@eecs.umich.edu case 0x1: 8577183Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 8587141Sgblack@eecs.umich.edu case 0x2: 8597183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 8607141Sgblack@eecs.umich.edu case 0x3: 8617183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 8627141Sgblack@eecs.umich.edu } 8637141Sgblack@eecs.umich.edu case 0x4: 8647183Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 8657141Sgblack@eecs.umich.edu case 0x5: 8667146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 8677141Sgblack@eecs.umich.edu case 0x6: 8687183Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 8697141Sgblack@eecs.umich.edu case 0x7: 8707183Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 8717141Sgblack@eecs.umich.edu } 8727141Sgblack@eecs.umich.edu } 8737141Sgblack@eecs.umich.edu ''' 8747141Sgblack@eecs.umich.edu}}; 8757141Sgblack@eecs.umich.edu 8767141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 8777141Sgblack@eecs.umich.edu decode_block = ''' 8787141Sgblack@eecs.umich.edu { 8797141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8807141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8817141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 8827141Sgblack@eecs.umich.edu case 0x0: 8837183Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 8847141Sgblack@eecs.umich.edu case 0x1: 8857183Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 8867141Sgblack@eecs.umich.edu case 0x2: //lsl 8877183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 8887141Sgblack@eecs.umich.edu case 0x3: //lsr 8897183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 8907141Sgblack@eecs.umich.edu case 0x4: //asr 8917183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 8927141Sgblack@eecs.umich.edu case 0x5: 8937183Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8947141Sgblack@eecs.umich.edu case 0x6: 8957183Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 8967141Sgblack@eecs.umich.edu case 0x7: // ror 8977183Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 8987141Sgblack@eecs.umich.edu case 0x8: 8997183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9007141Sgblack@eecs.umich.edu case 0x9: 9017183Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 9027141Sgblack@eecs.umich.edu case 0xa: 9037183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9047141Sgblack@eecs.umich.edu case 0xb: 9057183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9067141Sgblack@eecs.umich.edu case 0xc: 9077183Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 9087141Sgblack@eecs.umich.edu case 0xd: 9097183Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 9107141Sgblack@eecs.umich.edu case 0xe: 9117183Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 9127141Sgblack@eecs.umich.edu case 0xf: 9137183Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 9147141Sgblack@eecs.umich.edu } 9157141Sgblack@eecs.umich.edu } 9167141Sgblack@eecs.umich.edu ''' 9177141Sgblack@eecs.umich.edu}}; 9187141Sgblack@eecs.umich.edu 9197141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 9207141Sgblack@eecs.umich.edu decode_block = ''' 9217141Sgblack@eecs.umich.edu { 9227141Sgblack@eecs.umich.edu const IntRegIndex rdn = 9237141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 9247141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 9257141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 9267141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 9277141Sgblack@eecs.umich.edu case 0x0: 9287146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 9297141Sgblack@eecs.umich.edu case 0x1: 9307183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 9317141Sgblack@eecs.umich.edu case 0x2: 9327146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 9337141Sgblack@eecs.umich.edu case 0x3: 9347154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 9357154Sgblack@eecs.umich.edu return new BxReg(machInst, 9367154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9377154Sgblack@eecs.umich.edu COND_UC); 9387154Sgblack@eecs.umich.edu } else { 9397154Sgblack@eecs.umich.edu return new BlxReg(machInst, 9407154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 9417154Sgblack@eecs.umich.edu COND_UC); 9427154Sgblack@eecs.umich.edu } 9437141Sgblack@eecs.umich.edu } 9447141Sgblack@eecs.umich.edu } 9457141Sgblack@eecs.umich.edu ''' 9467141Sgblack@eecs.umich.edu}}; 9477141Sgblack@eecs.umich.edu 9487141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 9497141Sgblack@eecs.umich.edu decode_block = ''' 9507141Sgblack@eecs.umich.edu { 9517141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9527141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9537185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 9547141Sgblack@eecs.umich.edu } 9557141Sgblack@eecs.umich.edu ''' 9567141Sgblack@eecs.umich.edu}}; 9577141Sgblack@eecs.umich.edu 9587141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 9597141Sgblack@eecs.umich.edu decode_block = ''' 9607141Sgblack@eecs.umich.edu { 9617141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 9627141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 9637146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 9647141Sgblack@eecs.umich.edu } 9657141Sgblack@eecs.umich.edu ''' 9667141Sgblack@eecs.umich.edu}}; 9677141Sgblack@eecs.umich.edu 9687141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 9697141Sgblack@eecs.umich.edu decode_block = ''' 9707141Sgblack@eecs.umich.edu { 9717141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 9727141Sgblack@eecs.umich.edu case 0x0: 9737141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 9747146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 9757141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9767141Sgblack@eecs.umich.edu } else { 9777146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 9787141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 9797141Sgblack@eecs.umich.edu } 9807141Sgblack@eecs.umich.edu case 0x1: 9817154Sgblack@eecs.umich.edu return new Cbz(machInst, 9827154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 9837154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 9847154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 9857141Sgblack@eecs.umich.edu case 0x2: 9867235Sgblack@eecs.umich.edu { 9877235Sgblack@eecs.umich.edu const IntRegIndex rd = 9887235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9897235Sgblack@eecs.umich.edu const IntRegIndex rm = 9907235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9917235Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 9927235Sgblack@eecs.umich.edu case 0x0: 9937235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, 0, rm); 9947235Sgblack@eecs.umich.edu case 0x1: 9957235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, 0, rm); 9967235Sgblack@eecs.umich.edu case 0x2: 9977235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, 0, rm); 9987235Sgblack@eecs.umich.edu case 0x3: 9997235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, 0, rm); 10007235Sgblack@eecs.umich.edu } 10017141Sgblack@eecs.umich.edu } 10027141Sgblack@eecs.umich.edu case 0x3: 10037154Sgblack@eecs.umich.edu return new Cbz(machInst, 10047154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10057154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10067154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10077141Sgblack@eecs.umich.edu case 0x4: 10087141Sgblack@eecs.umich.edu case 0x5: 10097201Sgblack@eecs.umich.edu { 10107201Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 10117201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 10127201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 10137201Sgblack@eecs.umich.edu true, false, regList); 10147201Sgblack@eecs.umich.edu } 10157141Sgblack@eecs.umich.edu case 0x6: 10167141Sgblack@eecs.umich.edu { 10177141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 10187141Sgblack@eecs.umich.edu if (opBits == 2) { 10197141Sgblack@eecs.umich.edu return new WarnUnimplemented("setend", machInst); 10207141Sgblack@eecs.umich.edu } else if (opBits == 3) { 10217141Sgblack@eecs.umich.edu return new WarnUnimplemented("cps", machInst); 10227141Sgblack@eecs.umich.edu } 10237141Sgblack@eecs.umich.edu } 10247141Sgblack@eecs.umich.edu case 0x9: 10257154Sgblack@eecs.umich.edu return new Cbnz(machInst, 10267154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10277154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10287154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10297141Sgblack@eecs.umich.edu case 0xa: 10307212Sgblack@eecs.umich.edu { 10317212Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 10327212Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 10337212Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 10347212Sgblack@eecs.umich.edu case 0x0: 10357212Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 10367212Sgblack@eecs.umich.edu case 0x1: 10377212Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 10387212Sgblack@eecs.umich.edu case 0x3: 10397212Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 10407212Sgblack@eecs.umich.edu default: 10417212Sgblack@eecs.umich.edu break; 10427212Sgblack@eecs.umich.edu } 10437141Sgblack@eecs.umich.edu } 10447141Sgblack@eecs.umich.edu break; 10457141Sgblack@eecs.umich.edu case 0xb: 10467154Sgblack@eecs.umich.edu return new Cbnz(machInst, 10477154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 10487154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 10497154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 10507141Sgblack@eecs.umich.edu case 0xc: 10517141Sgblack@eecs.umich.edu case 0xd: 10527201Sgblack@eecs.umich.edu { 10537201Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 10547201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 10557201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 10567201Sgblack@eecs.umich.edu true, true, regList); 10577201Sgblack@eecs.umich.edu } 10587141Sgblack@eecs.umich.edu case 0xe: 10597141Sgblack@eecs.umich.edu return new WarnUnimplemented("bkpt", machInst); 10607141Sgblack@eecs.umich.edu case 0xf: 10617141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 10627141Sgblack@eecs.umich.edu return new WarnUnimplemented("it", machInst); 10637141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 10647141Sgblack@eecs.umich.edu case 0x0: 10657248Sgblack@eecs.umich.edu return new NopInst(machInst); 10667141Sgblack@eecs.umich.edu case 0x1: 10677141Sgblack@eecs.umich.edu return new WarnUnimplemented("yield", machInst); 10687141Sgblack@eecs.umich.edu case 0x2: 10697141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfe", machInst); 10707141Sgblack@eecs.umich.edu case 0x3: 10717141Sgblack@eecs.umich.edu return new WarnUnimplemented("wfi", machInst); 10727141Sgblack@eecs.umich.edu case 0x4: 10737141Sgblack@eecs.umich.edu return new WarnUnimplemented("sev", machInst); 10747141Sgblack@eecs.umich.edu default: 10757141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 10767141Sgblack@eecs.umich.edu } 10777141Sgblack@eecs.umich.edu default: 10787141Sgblack@eecs.umich.edu break; 10797141Sgblack@eecs.umich.edu } 10807141Sgblack@eecs.umich.edu return new Unknown(machInst); 10817141Sgblack@eecs.umich.edu } 10827141Sgblack@eecs.umich.edu ''' 10837141Sgblack@eecs.umich.edu}}; 10847141Sgblack@eecs.umich.edu 10857141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 10867141Sgblack@eecs.umich.edu 10877141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 10887141Sgblack@eecs.umich.edu return ''' 10897141Sgblack@eecs.umich.edu if (s) { 10907146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 10917183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10927141Sgblack@eecs.umich.edu } else { 10937146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 10947183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 10957141Sgblack@eecs.umich.edu } 10967141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 10977141Sgblack@eecs.umich.edu 10987141Sgblack@eecs.umich.edu decode_block = ''' 10997141Sgblack@eecs.umich.edu { 11007141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 11017141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 11027141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11037141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11047141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 11057141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 11067183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 11077141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 11087141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 11097141Sgblack@eecs.umich.edu switch (op) { 11107141Sgblack@eecs.umich.edu case 0x0: 11117141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11127141Sgblack@eecs.umich.edu %(tst)s 11137141Sgblack@eecs.umich.edu } else { 11147141Sgblack@eecs.umich.edu %(and)s 11157141Sgblack@eecs.umich.edu } 11167141Sgblack@eecs.umich.edu case 0x1: 11177141Sgblack@eecs.umich.edu %(bic)s 11187141Sgblack@eecs.umich.edu case 0x2: 11197141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 11207141Sgblack@eecs.umich.edu %(mov)s 11217141Sgblack@eecs.umich.edu } else { 11227141Sgblack@eecs.umich.edu %(orr)s 11237141Sgblack@eecs.umich.edu } 11247141Sgblack@eecs.umich.edu case 0x3: 11257141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 11267141Sgblack@eecs.umich.edu %(mvn)s 11277141Sgblack@eecs.umich.edu } else { 11287141Sgblack@eecs.umich.edu %(orn)s 11297141Sgblack@eecs.umich.edu } 11307141Sgblack@eecs.umich.edu case 0x4: 11317141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11327141Sgblack@eecs.umich.edu %(teq)s 11337141Sgblack@eecs.umich.edu } else { 11347141Sgblack@eecs.umich.edu %(eor)s 11357141Sgblack@eecs.umich.edu } 11367141Sgblack@eecs.umich.edu case 0x8: 11377141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11387141Sgblack@eecs.umich.edu %(cmn)s 11397141Sgblack@eecs.umich.edu } else { 11407141Sgblack@eecs.umich.edu %(add)s 11417141Sgblack@eecs.umich.edu } 11427141Sgblack@eecs.umich.edu case 0xa: 11437141Sgblack@eecs.umich.edu %(adc)s 11447141Sgblack@eecs.umich.edu case 0xb: 11457141Sgblack@eecs.umich.edu %(sbc)s 11467141Sgblack@eecs.umich.edu case 0xd: 11477141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 11487141Sgblack@eecs.umich.edu %(cmp)s 11497141Sgblack@eecs.umich.edu } else { 11507141Sgblack@eecs.umich.edu %(sub)s 11517141Sgblack@eecs.umich.edu } 11527141Sgblack@eecs.umich.edu case 0xe: 11537141Sgblack@eecs.umich.edu %(rsb)s 11547141Sgblack@eecs.umich.edu default: 11557141Sgblack@eecs.umich.edu return new Unknown(machInst); 11567141Sgblack@eecs.umich.edu } 11577141Sgblack@eecs.umich.edu } 11587141Sgblack@eecs.umich.edu ''' % { 11597141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 11607141Sgblack@eecs.umich.edu "and" : decInst("And"), 11617141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 11627141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 11637141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 11647141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 11657141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 11667141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 11677141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 11687141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 11697141Sgblack@eecs.umich.edu "add" : decInst("Add"), 11707141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 11717141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 11727141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 11737141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 11747141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 11757141Sgblack@eecs.umich.edu } 11767141Sgblack@eecs.umich.edu}}; 11777141Sgblack@eecs.umich.edu 11787157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 11797157Sgblack@eecs.umich.edu decode_block = ''' 11807157Sgblack@eecs.umich.edu { 11817157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 11827157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 11837157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 11847157Sgblack@eecs.umich.edu switch (op) { 11857157Sgblack@eecs.umich.edu case 0x0: 11867157Sgblack@eecs.umich.edu { 11877157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 11887157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 11897157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 11907185Sgblack@eecs.umich.edu if (rn == 0xf) { 11917185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 11927185Sgblack@eecs.umich.edu imm, false); 11937185Sgblack@eecs.umich.edu } else { 11947185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 11957185Sgblack@eecs.umich.edu } 11967157Sgblack@eecs.umich.edu } 11977157Sgblack@eecs.umich.edu case 0x4: 11987157Sgblack@eecs.umich.edu { 11997157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12007157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12017157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 12027157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 12037157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 12047157Sgblack@eecs.umich.edu } 12057157Sgblack@eecs.umich.edu case 0xa: 12067157Sgblack@eecs.umich.edu { 12077157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12087157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12097157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 12107185Sgblack@eecs.umich.edu if (rn == 0xf) { 12117185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 12127185Sgblack@eecs.umich.edu imm, false); 12137185Sgblack@eecs.umich.edu } else { 12147185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 12157185Sgblack@eecs.umich.edu } 12167157Sgblack@eecs.umich.edu } 12177157Sgblack@eecs.umich.edu case 0xc: 12187157Sgblack@eecs.umich.edu { 12197157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 12207157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 12217157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 12227157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 12237157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 12247157Sgblack@eecs.umich.edu } 12257157Sgblack@eecs.umich.edu case 0x12: 12267157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12277227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12287227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 12297157Sgblack@eecs.umich.edu } 12307157Sgblack@eecs.umich.edu // Fall through on purpose... 12317157Sgblack@eecs.umich.edu case 0x10: 12327227Sgblack@eecs.umich.edu { 12337227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12347227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12357227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12367227Sgblack@eecs.umich.edu const ArmShiftType type = 12377227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12387227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 12397227Sgblack@eecs.umich.edu } 12407157Sgblack@eecs.umich.edu case 0x14: 12417157Sgblack@eecs.umich.edu return new WarnUnimplemented("sbfx", machInst); 12427157Sgblack@eecs.umich.edu case 0x16: 12437157Sgblack@eecs.umich.edu if (rn == 0xf) { 12447157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfc", machInst); 12457157Sgblack@eecs.umich.edu } else { 12467157Sgblack@eecs.umich.edu return new WarnUnimplemented("bfi", machInst); 12477157Sgblack@eecs.umich.edu } 12487157Sgblack@eecs.umich.edu case 0x1a: 12497157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 12507227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12517227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 12527157Sgblack@eecs.umich.edu } 12537157Sgblack@eecs.umich.edu // Fall through on purpose... 12547157Sgblack@eecs.umich.edu case 0x18: 12557227Sgblack@eecs.umich.edu { 12567227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 12577227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 12587227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 12597227Sgblack@eecs.umich.edu const ArmShiftType type = 12607227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 12617227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 12627227Sgblack@eecs.umich.edu } 12637157Sgblack@eecs.umich.edu case 0x1c: 12647157Sgblack@eecs.umich.edu return new WarnUnimplemented("ubfx", machInst); 12657157Sgblack@eecs.umich.edu default: 12667157Sgblack@eecs.umich.edu return new Unknown(machInst); 12677157Sgblack@eecs.umich.edu } 12687157Sgblack@eecs.umich.edu } 12697157Sgblack@eecs.umich.edu ''' 12707157Sgblack@eecs.umich.edu}}; 12717157Sgblack@eecs.umich.edu 12727141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 12737141Sgblack@eecs.umich.edu 12747141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 12757141Sgblack@eecs.umich.edu return ''' 12767141Sgblack@eecs.umich.edu if (s) { 12777146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 12787141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12797141Sgblack@eecs.umich.edu } else { 12807146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 12817141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 12827141Sgblack@eecs.umich.edu } 12837141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 12847141Sgblack@eecs.umich.edu 12857141Sgblack@eecs.umich.edu decode_block = ''' 12867141Sgblack@eecs.umich.edu { 12877141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 12887141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 12897141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 12907141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 12917141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 12927141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 12937141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 12947141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 12957141Sgblack@eecs.umich.edu switch (op) { 12967141Sgblack@eecs.umich.edu case 0x0: 12977141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 12987141Sgblack@eecs.umich.edu %(tst)s 12997141Sgblack@eecs.umich.edu } else { 13007141Sgblack@eecs.umich.edu %(and)s 13017141Sgblack@eecs.umich.edu } 13027141Sgblack@eecs.umich.edu case 0x1: 13037141Sgblack@eecs.umich.edu %(bic)s 13047141Sgblack@eecs.umich.edu case 0x2: 13057141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13067141Sgblack@eecs.umich.edu %(mov)s 13077141Sgblack@eecs.umich.edu } else { 13087141Sgblack@eecs.umich.edu %(orr)s 13097141Sgblack@eecs.umich.edu } 13107141Sgblack@eecs.umich.edu case 0x3: 13117141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13127141Sgblack@eecs.umich.edu %(mvn)s 13137141Sgblack@eecs.umich.edu } else { 13147141Sgblack@eecs.umich.edu %(orn)s 13157141Sgblack@eecs.umich.edu } 13167141Sgblack@eecs.umich.edu case 0x4: 13177141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13187141Sgblack@eecs.umich.edu %(teq)s 13197141Sgblack@eecs.umich.edu } else { 13207141Sgblack@eecs.umich.edu %(eor)s 13217141Sgblack@eecs.umich.edu } 13227141Sgblack@eecs.umich.edu case 0x6: 13237237Sgblack@eecs.umich.edu if (type) { 13247237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, rn, rm, amt, type); 13257237Sgblack@eecs.umich.edu } else { 13267237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, rn, rm, amt, type); 13277237Sgblack@eecs.umich.edu } 13287141Sgblack@eecs.umich.edu case 0x8: 13297141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13307141Sgblack@eecs.umich.edu %(cmn)s 13317141Sgblack@eecs.umich.edu } else { 13327141Sgblack@eecs.umich.edu %(add)s 13337141Sgblack@eecs.umich.edu } 13347141Sgblack@eecs.umich.edu case 0xa: 13357141Sgblack@eecs.umich.edu %(adc)s 13367141Sgblack@eecs.umich.edu case 0xb: 13377141Sgblack@eecs.umich.edu %(sbc)s 13387141Sgblack@eecs.umich.edu case 0xd: 13397141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13407141Sgblack@eecs.umich.edu %(cmp)s 13417141Sgblack@eecs.umich.edu } else { 13427141Sgblack@eecs.umich.edu %(sub)s 13437141Sgblack@eecs.umich.edu } 13447141Sgblack@eecs.umich.edu case 0xe: 13457141Sgblack@eecs.umich.edu %(rsb)s 13467141Sgblack@eecs.umich.edu default: 13477141Sgblack@eecs.umich.edu return new Unknown(machInst); 13487141Sgblack@eecs.umich.edu } 13497141Sgblack@eecs.umich.edu } 13507141Sgblack@eecs.umich.edu ''' % { 13517141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 13527141Sgblack@eecs.umich.edu "and" : decInst("And"), 13537141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 13547141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 13557141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 13567141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 13577141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 13587141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 13597141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 13607141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 13617141Sgblack@eecs.umich.edu "add" : decInst("Add"), 13627141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 13637141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 13647141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 13657141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 13667141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 13677141Sgblack@eecs.umich.edu } 13687141Sgblack@eecs.umich.edu}}; 1369