data.isa revision 12542
112542Sgiacomo.travaglini@arm.com// Copyright (c) 2010,2017-2018 ARM Limited 27139Sgblack@eecs.umich.edu// All rights reserved 37139Sgblack@eecs.umich.edu// 47139Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57139Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67139Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77139Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87139Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97139Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107139Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117139Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127139Sgblack@eecs.umich.edu// 137139Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147139Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 157139Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 167139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 177139Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 187139Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 197139Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 207139Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 217139Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227139Sgblack@eecs.umich.edu// this software without specific prior written permission. 237139Sgblack@eecs.umich.edu// 247139Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 257139Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267139Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277139Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287139Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297139Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307139Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317139Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327139Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337139Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 347139Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357139Sgblack@eecs.umich.edu// 367139Sgblack@eecs.umich.edu// Authors: Gabe Black 377139Sgblack@eecs.umich.edu 387255Sgblack@eecs.umich.edudef format ArmMiscMedia() {{ 397243Sgblack@eecs.umich.edu decode_block = ''' 407243Sgblack@eecs.umich.edu { 417255Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 427255Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 437243Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 447243Sgblack@eecs.umich.edu const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 457255Sgblack@eecs.umich.edu if (op1 == 0 && op2 == 0) { 467255Sgblack@eecs.umich.edu const IntRegIndex rd = 477255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 487255Sgblack@eecs.umich.edu const IntRegIndex rm = 497255Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 507255Sgblack@eecs.umich.edu if (ra == 0xf) { 517255Sgblack@eecs.umich.edu return new Usad8(machInst, rd, rn, rm); 527255Sgblack@eecs.umich.edu } else { 537255Sgblack@eecs.umich.edu return new Usada8(machInst, rd, rn, rm, ra); 547255Sgblack@eecs.umich.edu } 557255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x2) { 567256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 11, 7); 577256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 20, 16); 587255Sgblack@eecs.umich.edu if (bits(op1, 2, 1) == 0x3) { 597256Sgblack@eecs.umich.edu return new Ubfx(machInst, ra, rn, lsb, msb); 607255Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 0x1) { 617256Sgblack@eecs.umich.edu return new Sbfx(machInst, ra, rn, lsb, msb); 627255Sgblack@eecs.umich.edu } 637255Sgblack@eecs.umich.edu } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 647258Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 11, 7); 657258Sgblack@eecs.umich.edu const uint32_t msb = bits(machInst, 20, 16); 667255Sgblack@eecs.umich.edu if (rn == 0xf) { 677258Sgblack@eecs.umich.edu return new Bfc(machInst, ra, ra, lsb, msb); 687255Sgblack@eecs.umich.edu } else { 697258Sgblack@eecs.umich.edu return new Bfi(machInst, ra, rn, lsb, msb); 707255Sgblack@eecs.umich.edu } 717243Sgblack@eecs.umich.edu } 727255Sgblack@eecs.umich.edu return new Unknown(machInst); 737243Sgblack@eecs.umich.edu } 747243Sgblack@eecs.umich.edu ''' 757243Sgblack@eecs.umich.edu}}; 767243Sgblack@eecs.umich.edu 777139Sgblack@eecs.umich.edudef format ArmDataProcReg() {{ 787188Sgblack@eecs.umich.edu pclr = ''' 797188Sgblack@eecs.umich.edu return new %(className)ssRegPclr(machInst, %(dest)s, 807188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, 817188Sgblack@eecs.umich.edu type); 827188Sgblack@eecs.umich.edu ''' 837139Sgblack@eecs.umich.edu instDecode = ''' 847139Sgblack@eecs.umich.edu case %(opcode)#x: 857139Sgblack@eecs.umich.edu if (immShift) { 867139Sgblack@eecs.umich.edu if (setCc) { 877188Sgblack@eecs.umich.edu if (%(dest)s == INTREG_PC) { 887188Sgblack@eecs.umich.edu %(pclr)s 897188Sgblack@eecs.umich.edu } else { 907188Sgblack@eecs.umich.edu return new %(className)sRegCc(machInst, %(dest)s, 917188Sgblack@eecs.umich.edu %(op1)s, rm, imm5, type); 927188Sgblack@eecs.umich.edu } 937139Sgblack@eecs.umich.edu } else { 947146Sgblack@eecs.umich.edu return new %(className)sReg(machInst, %(dest)s, %(op1)s, 957141Sgblack@eecs.umich.edu rm, imm5, type); 967139Sgblack@eecs.umich.edu } 977139Sgblack@eecs.umich.edu } else { 987139Sgblack@eecs.umich.edu if (setCc) { 997146Sgblack@eecs.umich.edu return new %(className)sRegRegCc(machInst, %(dest)s, 1007141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1017139Sgblack@eecs.umich.edu } else { 1027146Sgblack@eecs.umich.edu return new %(className)sRegReg(machInst, %(dest)s, 1037141Sgblack@eecs.umich.edu %(op1)s, rm, rs, type); 1047139Sgblack@eecs.umich.edu } 1057139Sgblack@eecs.umich.edu } 1067139Sgblack@eecs.umich.edu break; 1077139Sgblack@eecs.umich.edu ''' 1087139Sgblack@eecs.umich.edu 1097188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 1107188Sgblack@eecs.umich.edu global pclr 1117188Sgblack@eecs.umich.edu if useDest: 1127188Sgblack@eecs.umich.edu dest = "rd" 1137188Sgblack@eecs.umich.edu else: 1147188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 1157188Sgblack@eecs.umich.edu if useOp1: 1167188Sgblack@eecs.umich.edu op1 = "rn" 1177188Sgblack@eecs.umich.edu else: 1187188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 1197188Sgblack@eecs.umich.edu global instDecode, pclrCode 1207188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 1217188Sgblack@eecs.umich.edu "opcode": opcode, 1227188Sgblack@eecs.umich.edu "dest": dest, 1237188Sgblack@eecs.umich.edu "op1": op1 } 1247188Sgblack@eecs.umich.edu if useDest: 1257188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 1267188Sgblack@eecs.umich.edu else: 1277188Sgblack@eecs.umich.edu substDict["pclr"] = "" 1287188Sgblack@eecs.umich.edu return instDecode % substDict 1297139Sgblack@eecs.umich.edu 1307139Sgblack@eecs.umich.edu decode_block = ''' 1317139Sgblack@eecs.umich.edu { 1327139Sgblack@eecs.umich.edu const bool immShift = (bits(machInst, 4) == 0); 1337139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 1347139Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 11, 7); 1357139Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1367139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 1377139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 1387139Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 1397139Sgblack@eecs.umich.edu const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 1407139Sgblack@eecs.umich.edu switch (OPCODE) { 1417139Sgblack@eecs.umich.edu ''' 1427139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 1437139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 1447139Sgblack@eecs.umich.edu decode_block += instCode(0x2, "sub") 1457139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 1467139Sgblack@eecs.umich.edu decode_block += instCode(0x4, "add") 1477139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 1487139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 1497139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 1507188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 1517188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 1527188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 1537188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 1547139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 1557188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 1567139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 1577188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 1587139Sgblack@eecs.umich.edu decode_block += ''' 1597139Sgblack@eecs.umich.edu default: 1607139Sgblack@eecs.umich.edu return new Unknown(machInst); 1617139Sgblack@eecs.umich.edu } 1627139Sgblack@eecs.umich.edu } 1637139Sgblack@eecs.umich.edu ''' 1647139Sgblack@eecs.umich.edu}}; 1657139Sgblack@eecs.umich.edu 1667210Sgblack@eecs.umich.edudef format ArmPackUnpackSatReverse() {{ 1677210Sgblack@eecs.umich.edu decode_block = ''' 1687210Sgblack@eecs.umich.edu { 1697210Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 1707210Sgblack@eecs.umich.edu const uint32_t a = bits(machInst, 19, 16); 1717210Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 1727210Sgblack@eecs.umich.edu if (bits(op2, 0) == 0) { 1737227Sgblack@eecs.umich.edu const IntRegIndex rn = 1747227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1757227Sgblack@eecs.umich.edu const IntRegIndex rd = 1767227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 1777227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 1787227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 11, 7); 1797227Sgblack@eecs.umich.edu const ArmShiftType type = 1807227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 1817210Sgblack@eecs.umich.edu if (op1 == 0) { 1827237Sgblack@eecs.umich.edu if (type) { 1837237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, (IntRegIndex)a, 1847237Sgblack@eecs.umich.edu rn, imm, type); 1857237Sgblack@eecs.umich.edu } else { 1867237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, (IntRegIndex)a, 1877237Sgblack@eecs.umich.edu rn, imm, type); 1887237Sgblack@eecs.umich.edu } 1897210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 1) { 1907227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1917210Sgblack@eecs.umich.edu } else if (bits(op1, 2, 1) == 3) { 1927227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 1937210Sgblack@eecs.umich.edu } 1947210Sgblack@eecs.umich.edu return new Unknown(machInst); 1957210Sgblack@eecs.umich.edu } 1967210Sgblack@eecs.umich.edu switch (op1) { 1977210Sgblack@eecs.umich.edu case 0x0: 1987240Sgblack@eecs.umich.edu { 1997235Sgblack@eecs.umich.edu const IntRegIndex rn = 2007235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2017235Sgblack@eecs.umich.edu const IntRegIndex rd = 2027235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2037235Sgblack@eecs.umich.edu const IntRegIndex rm = 2047235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2057240Sgblack@eecs.umich.edu if (op2 == 0x3) { 2067240Sgblack@eecs.umich.edu const uint32_t rotation = 2077240Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2087240Sgblack@eecs.umich.edu if (a == 0xf) { 2097240Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 2107240Sgblack@eecs.umich.edu } else { 2117240Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 2127240Sgblack@eecs.umich.edu } 2137240Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2147240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 2157210Sgblack@eecs.umich.edu } 2167210Sgblack@eecs.umich.edu } 2177210Sgblack@eecs.umich.edu break; 2187210Sgblack@eecs.umich.edu case 0x2: 2197210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2207227Sgblack@eecs.umich.edu const IntRegIndex rn = 2217227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2227227Sgblack@eecs.umich.edu const IntRegIndex rd = 2237227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2247227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2257227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 2267210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2277235Sgblack@eecs.umich.edu const IntRegIndex rn = 2287235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2297235Sgblack@eecs.umich.edu const IntRegIndex rd = 2307235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2317235Sgblack@eecs.umich.edu const IntRegIndex rm = 2327235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2337235Sgblack@eecs.umich.edu const uint32_t rotation = 2347235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2357210Sgblack@eecs.umich.edu if (a == 0xf) { 2367235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 2377210Sgblack@eecs.umich.edu } else { 2387235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 2397210Sgblack@eecs.umich.edu } 2407210Sgblack@eecs.umich.edu } 2417210Sgblack@eecs.umich.edu break; 2427210Sgblack@eecs.umich.edu case 0x3: 2437210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2447211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2457211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2467211Sgblack@eecs.umich.edu return new Rev(machInst, rd, rm); 2477210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2487235Sgblack@eecs.umich.edu const IntRegIndex rn = 2497235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2507235Sgblack@eecs.umich.edu const IntRegIndex rd = 2517235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2527235Sgblack@eecs.umich.edu const IntRegIndex rm = 2537235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2547235Sgblack@eecs.umich.edu const uint32_t rotation = 2557235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2567210Sgblack@eecs.umich.edu if (a == 0xf) { 2577235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 2587210Sgblack@eecs.umich.edu } else { 2597235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 2607210Sgblack@eecs.umich.edu } 2617210Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 2627211Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2637211Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2647211Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rm); 2657210Sgblack@eecs.umich.edu } 2667210Sgblack@eecs.umich.edu break; 2677210Sgblack@eecs.umich.edu case 0x4: 2687210Sgblack@eecs.umich.edu if (op2 == 0x3) { 2697235Sgblack@eecs.umich.edu const IntRegIndex rn = 2707235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2717235Sgblack@eecs.umich.edu const IntRegIndex rd = 2727235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2737235Sgblack@eecs.umich.edu const IntRegIndex rm = 2747235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2757235Sgblack@eecs.umich.edu const uint32_t rotation = 2767235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 2777210Sgblack@eecs.umich.edu if (a == 0xf) { 2787235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 2797210Sgblack@eecs.umich.edu } else { 2807235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 2817210Sgblack@eecs.umich.edu } 2827210Sgblack@eecs.umich.edu } 2837210Sgblack@eecs.umich.edu break; 2847210Sgblack@eecs.umich.edu case 0x6: 2857210Sgblack@eecs.umich.edu if (op2 == 0x1) { 2867227Sgblack@eecs.umich.edu const IntRegIndex rn = 2877227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2887227Sgblack@eecs.umich.edu const IntRegIndex rd = 2897227Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2907227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 20, 16); 2917227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 2927210Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 2937235Sgblack@eecs.umich.edu const IntRegIndex rn = 2947235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 2957235Sgblack@eecs.umich.edu const IntRegIndex rd = 2967235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 2977235Sgblack@eecs.umich.edu const IntRegIndex rm = 2987235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 2997235Sgblack@eecs.umich.edu const uint32_t rotation = 3007235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3017210Sgblack@eecs.umich.edu if (a == 0xf) { 3027235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 3037210Sgblack@eecs.umich.edu } else { 3047235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 3057210Sgblack@eecs.umich.edu } 3067210Sgblack@eecs.umich.edu } 3077210Sgblack@eecs.umich.edu break; 3087210Sgblack@eecs.umich.edu case 0x7: 3097250Sgblack@eecs.umich.edu { 3107235Sgblack@eecs.umich.edu const IntRegIndex rn = 3117235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3127235Sgblack@eecs.umich.edu const IntRegIndex rd = 3137235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3147235Sgblack@eecs.umich.edu const IntRegIndex rm = 3157235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3167250Sgblack@eecs.umich.edu if (op2 == 0x1) { 3177250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 3187250Sgblack@eecs.umich.edu } else if (op2 == 0x3) { 3197250Sgblack@eecs.umich.edu const uint32_t rotation = 3207250Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 11, 10) << 3; 3217250Sgblack@eecs.umich.edu if (a == 0xf) { 3227250Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 3237250Sgblack@eecs.umich.edu } else { 3247250Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 3257250Sgblack@eecs.umich.edu } 3267250Sgblack@eecs.umich.edu } else if (op2 == 0x5) { 3277250Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rm); 3287210Sgblack@eecs.umich.edu } 3297210Sgblack@eecs.umich.edu } 3307210Sgblack@eecs.umich.edu break; 3317210Sgblack@eecs.umich.edu } 3327210Sgblack@eecs.umich.edu return new Unknown(machInst); 3337210Sgblack@eecs.umich.edu } 3347210Sgblack@eecs.umich.edu ''' 3357210Sgblack@eecs.umich.edu}}; 3367210Sgblack@eecs.umich.edu 3377194Sgblack@eecs.umich.edudef format ArmParallelAddSubtract() {{ 3387194Sgblack@eecs.umich.edu decode_block=''' 3397194Sgblack@eecs.umich.edu { 3407194Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 21, 20); 3417194Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 5); 3427194Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 3437194Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 3447194Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 3457194Sgblack@eecs.umich.edu if (bits(machInst, 22) == 0) { 3467194Sgblack@eecs.umich.edu switch (op1) { 3477194Sgblack@eecs.umich.edu case 0x1: 3487194Sgblack@eecs.umich.edu switch (op2) { 3497194Sgblack@eecs.umich.edu case 0x0: 3507216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 3517194Sgblack@eecs.umich.edu case 0x1: 3527224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 3537194Sgblack@eecs.umich.edu case 0x2: 3547224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 3557194Sgblack@eecs.umich.edu case 0x3: 3567218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 3577194Sgblack@eecs.umich.edu case 0x4: 3587216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 3597194Sgblack@eecs.umich.edu case 0x7: 3607218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 3617194Sgblack@eecs.umich.edu } 3627194Sgblack@eecs.umich.edu break; 3637194Sgblack@eecs.umich.edu case 0x2: 3647194Sgblack@eecs.umich.edu switch (op2) { 3657194Sgblack@eecs.umich.edu case 0x0: 3667194Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 3677194Sgblack@eecs.umich.edu case 0x1: 3687194Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 3697194Sgblack@eecs.umich.edu case 0x2: 3707194Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 3717194Sgblack@eecs.umich.edu case 0x3: 3727194Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 3737194Sgblack@eecs.umich.edu case 0x4: 3747194Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 3757194Sgblack@eecs.umich.edu case 0x7: 3767194Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 3777194Sgblack@eecs.umich.edu } 3787194Sgblack@eecs.umich.edu break; 3797194Sgblack@eecs.umich.edu case 0x3: 3807194Sgblack@eecs.umich.edu switch (op2) { 3817194Sgblack@eecs.umich.edu case 0x0: 3827231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 3837194Sgblack@eecs.umich.edu case 0x1: 3847231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 3857194Sgblack@eecs.umich.edu case 0x2: 3867231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 3877194Sgblack@eecs.umich.edu case 0x3: 3887231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 3897194Sgblack@eecs.umich.edu case 0x4: 3907231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 3917194Sgblack@eecs.umich.edu case 0x7: 3927231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 3937194Sgblack@eecs.umich.edu } 3947194Sgblack@eecs.umich.edu break; 3957194Sgblack@eecs.umich.edu } 3967194Sgblack@eecs.umich.edu } else { 3977194Sgblack@eecs.umich.edu switch (op1) { 3987194Sgblack@eecs.umich.edu case 0x1: 3997194Sgblack@eecs.umich.edu switch (op2) { 4007194Sgblack@eecs.umich.edu case 0x0: 4017222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 4027194Sgblack@eecs.umich.edu case 0x1: 4037222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 4047194Sgblack@eecs.umich.edu case 0x2: 4057222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 4067194Sgblack@eecs.umich.edu case 0x3: 4077222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 4087194Sgblack@eecs.umich.edu case 0x4: 4097222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 4107194Sgblack@eecs.umich.edu case 0x7: 4117222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 4127194Sgblack@eecs.umich.edu } 4137194Sgblack@eecs.umich.edu break; 4147194Sgblack@eecs.umich.edu case 0x2: 4157194Sgblack@eecs.umich.edu switch (op2) { 4167194Sgblack@eecs.umich.edu case 0x0: 4177220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 4187194Sgblack@eecs.umich.edu case 0x1: 4197220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 4207194Sgblack@eecs.umich.edu case 0x2: 4217220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 4227194Sgblack@eecs.umich.edu case 0x3: 4237220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 4247194Sgblack@eecs.umich.edu case 0x4: 4257220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 4267194Sgblack@eecs.umich.edu case 0x7: 4277220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 4287194Sgblack@eecs.umich.edu } 4297194Sgblack@eecs.umich.edu break; 4307194Sgblack@eecs.umich.edu case 0x3: 4317194Sgblack@eecs.umich.edu switch (op2) { 4327194Sgblack@eecs.umich.edu case 0x0: 4337231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 4347194Sgblack@eecs.umich.edu case 0x1: 4357231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 4367194Sgblack@eecs.umich.edu case 0x2: 4377231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 4387194Sgblack@eecs.umich.edu case 0x3: 4397231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 4407194Sgblack@eecs.umich.edu case 0x4: 4417231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 4427194Sgblack@eecs.umich.edu case 0x7: 4437231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 4447194Sgblack@eecs.umich.edu } 4457194Sgblack@eecs.umich.edu break; 4467194Sgblack@eecs.umich.edu } 4477194Sgblack@eecs.umich.edu } 4487194Sgblack@eecs.umich.edu return new Unknown(machInst); 4497194Sgblack@eecs.umich.edu } 4507194Sgblack@eecs.umich.edu ''' 4517194Sgblack@eecs.umich.edu}}; 4527194Sgblack@eecs.umich.edu 4537139Sgblack@eecs.umich.edudef format ArmDataProcImm() {{ 4547188Sgblack@eecs.umich.edu pclr = ''' 4557188Sgblack@eecs.umich.edu return new %(className)ssImmPclr(machInst, %(dest)s, 4567188Sgblack@eecs.umich.edu %(op1)s, imm, false); 4577188Sgblack@eecs.umich.edu ''' 4587188Sgblack@eecs.umich.edu adr = ''' 4597188Sgblack@eecs.umich.edu return new AdrImm(machInst, %(dest)s, %(add)s, 4607188Sgblack@eecs.umich.edu imm, false); 4617188Sgblack@eecs.umich.edu ''' 4627139Sgblack@eecs.umich.edu instDecode = ''' 4637188Sgblack@eecs.umich.edu case %(opcode)#x: 4647139Sgblack@eecs.umich.edu if (setCc) { 4657188Sgblack@eecs.umich.edu if (%(pclrInst)s && %(dest)s == INTREG_PC) { 4667188Sgblack@eecs.umich.edu %(pclr)s 4677188Sgblack@eecs.umich.edu } else { 4687188Sgblack@eecs.umich.edu return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 4697188Sgblack@eecs.umich.edu imm, rotC); 4707188Sgblack@eecs.umich.edu } 4717139Sgblack@eecs.umich.edu } else { 4727188Sgblack@eecs.umich.edu if (%(adrInst)s && %(op1)s == INTREG_PC) { 4737188Sgblack@eecs.umich.edu %(adr)s 4747188Sgblack@eecs.umich.edu } else { 4757188Sgblack@eecs.umich.edu return new %(className)sImm(machInst, %(dest)s, %(op1)s, 4767188Sgblack@eecs.umich.edu imm, rotC); 4777188Sgblack@eecs.umich.edu } 4787139Sgblack@eecs.umich.edu } 4797139Sgblack@eecs.umich.edu break; 4807139Sgblack@eecs.umich.edu ''' 4817139Sgblack@eecs.umich.edu 4827188Sgblack@eecs.umich.edu def instCode(opcode, mnem, useDest = True, useOp1 = True): 4837188Sgblack@eecs.umich.edu global instDecode, pclr, adr 4847188Sgblack@eecs.umich.edu if useDest: 4857188Sgblack@eecs.umich.edu dest = "rd" 4867188Sgblack@eecs.umich.edu else: 4877188Sgblack@eecs.umich.edu dest = "INTREG_ZERO" 4887188Sgblack@eecs.umich.edu if useOp1: 4897188Sgblack@eecs.umich.edu op1 = "rn" 4907188Sgblack@eecs.umich.edu else: 4917188Sgblack@eecs.umich.edu op1 = "INTREG_ZERO" 4927188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 4937188Sgblack@eecs.umich.edu "opcode": opcode, 4947188Sgblack@eecs.umich.edu "dest": dest, 4957188Sgblack@eecs.umich.edu "op1": op1, 4967188Sgblack@eecs.umich.edu "adr": "", 4977188Sgblack@eecs.umich.edu "adrInst": "false" } 4987188Sgblack@eecs.umich.edu if useDest: 4997188Sgblack@eecs.umich.edu substDict["pclrInst"] = "true" 5007188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5017188Sgblack@eecs.umich.edu else: 5027188Sgblack@eecs.umich.edu substDict["pclrInst"] = "false" 5037188Sgblack@eecs.umich.edu substDict["pclr"] = "" 5047188Sgblack@eecs.umich.edu return instDecode % substDict 5057185Sgblack@eecs.umich.edu 5067188Sgblack@eecs.umich.edu def adrCode(opcode, mnem, add="1"): 5077188Sgblack@eecs.umich.edu global instDecode, pclr, adr 5087188Sgblack@eecs.umich.edu substDict = { "className": mnem.capitalize(), 5097188Sgblack@eecs.umich.edu "opcode": opcode, 5107188Sgblack@eecs.umich.edu "dest": "rd", 5117188Sgblack@eecs.umich.edu "op1": "rn", 5127188Sgblack@eecs.umich.edu "add": add, 5137188Sgblack@eecs.umich.edu "pclrInst": "true", 5147188Sgblack@eecs.umich.edu "adrInst": "true" } 5157188Sgblack@eecs.umich.edu substDict["pclr"] = pclr % substDict 5167188Sgblack@eecs.umich.edu substDict["adr"] = adr % substDict 5177188Sgblack@eecs.umich.edu return instDecode % substDict 5187139Sgblack@eecs.umich.edu 5197139Sgblack@eecs.umich.edu decode_block = ''' 5207139Sgblack@eecs.umich.edu { 5217139Sgblack@eecs.umich.edu const bool setCc = (bits(machInst, 20) == 1); 5227139Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 5237139Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 5247139Sgblack@eecs.umich.edu const bool rotC = (rotation != 0); 5257139Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 5267139Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 5277139Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 5287139Sgblack@eecs.umich.edu switch (OPCODE) { 5297139Sgblack@eecs.umich.edu ''' 5307139Sgblack@eecs.umich.edu decode_block += instCode(0x0, "and") 5317139Sgblack@eecs.umich.edu decode_block += instCode(0x1, "eor") 5327185Sgblack@eecs.umich.edu decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 5337139Sgblack@eecs.umich.edu decode_block += instCode(0x3, "rsb") 5347185Sgblack@eecs.umich.edu decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 5357139Sgblack@eecs.umich.edu decode_block += instCode(0x5, "adc") 5367139Sgblack@eecs.umich.edu decode_block += instCode(0x6, "sbc") 5377139Sgblack@eecs.umich.edu decode_block += instCode(0x7, "rsc") 5387188Sgblack@eecs.umich.edu decode_block += instCode(0x8, "tst", useDest = False) 5397188Sgblack@eecs.umich.edu decode_block += instCode(0x9, "teq", useDest = False) 5407188Sgblack@eecs.umich.edu decode_block += instCode(0xa, "cmp", useDest = False) 5417188Sgblack@eecs.umich.edu decode_block += instCode(0xb, "cmn", useDest = False) 5427139Sgblack@eecs.umich.edu decode_block += instCode(0xc, "orr") 5437188Sgblack@eecs.umich.edu decode_block += instCode(0xd, "mov", useOp1 = False) 5447139Sgblack@eecs.umich.edu decode_block += instCode(0xe, "bic") 5457188Sgblack@eecs.umich.edu decode_block += instCode(0xf, "mvn", useOp1 = False) 5467139Sgblack@eecs.umich.edu decode_block += ''' 5477139Sgblack@eecs.umich.edu default: 5487139Sgblack@eecs.umich.edu return new Unknown(machInst); 5497139Sgblack@eecs.umich.edu } 5507139Sgblack@eecs.umich.edu } 5517139Sgblack@eecs.umich.edu ''' 5527139Sgblack@eecs.umich.edu}}; 5537141Sgblack@eecs.umich.edu 5547195Sgblack@eecs.umich.edudef format ArmSatAddSub() {{ 5557195Sgblack@eecs.umich.edu decode_block = ''' 5567195Sgblack@eecs.umich.edu { 5577195Sgblack@eecs.umich.edu IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5587195Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 5597195Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5607195Sgblack@eecs.umich.edu switch (OPCODE) { 5617195Sgblack@eecs.umich.edu case 0x8: 5627195Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 5637195Sgblack@eecs.umich.edu case 0x9: 5647195Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 5657195Sgblack@eecs.umich.edu case 0xa: 5667195Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 5677195Sgblack@eecs.umich.edu case 0xb: 5687195Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 5697195Sgblack@eecs.umich.edu default: 5707195Sgblack@eecs.umich.edu return new Unknown(machInst); 5717195Sgblack@eecs.umich.edu } 5727195Sgblack@eecs.umich.edu } 5737195Sgblack@eecs.umich.edu ''' 5747195Sgblack@eecs.umich.edu}}; 5757195Sgblack@eecs.umich.edu 5767213Sgblack@eecs.umich.edudef format Thumb32DataProcReg() {{ 5777213Sgblack@eecs.umich.edu decode_block = ''' 5787213Sgblack@eecs.umich.edu { 5797213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 23, 20); 5807213Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 5817213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 7, 4); 5827290Sgblack@eecs.umich.edu if (bits(machInst, 15, 12) != 0xf) { 5837290Sgblack@eecs.umich.edu return new Unknown(machInst); 5847290Sgblack@eecs.umich.edu } 5857213Sgblack@eecs.umich.edu if (bits(op1, 3) != 1) { 5867213Sgblack@eecs.umich.edu if (op2 == 0) { 5877213Sgblack@eecs.umich.edu IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 5887213Sgblack@eecs.umich.edu IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 5897213Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 5907213Sgblack@eecs.umich.edu case 0x0: 5917213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5927213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5937213Sgblack@eecs.umich.edu case 0x1: 5947213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 5957213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSL); 5967213Sgblack@eecs.umich.edu case 0x2: 5977213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 5987213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 5997213Sgblack@eecs.umich.edu case 0x3: 6007213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6017213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, LSR); 6027213Sgblack@eecs.umich.edu case 0x4: 6037213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6047213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6057213Sgblack@eecs.umich.edu case 0x5: 6067213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6077213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ASR); 6087213Sgblack@eecs.umich.edu case 0x6: 6097213Sgblack@eecs.umich.edu return new MovRegReg(machInst, rd, 6107213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6117213Sgblack@eecs.umich.edu case 0x7: 6127213Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rd, 6137213Sgblack@eecs.umich.edu INTREG_ZERO, rn, rm, ROR); 6147213Sgblack@eecs.umich.edu } 6157290Sgblack@eecs.umich.edu } else if (bits(op2, 3) == 0) { 6167290Sgblack@eecs.umich.edu return new Unknown(machInst); 6177290Sgblack@eecs.umich.edu } else { 6187235Sgblack@eecs.umich.edu const IntRegIndex rd = 6197235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6207235Sgblack@eecs.umich.edu const IntRegIndex rm = 6217235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6227235Sgblack@eecs.umich.edu const uint32_t rotation = 6237235Sgblack@eecs.umich.edu (uint32_t)bits(machInst, 5, 4) << 3; 6247235Sgblack@eecs.umich.edu switch (bits(op1, 2, 0)) { 6257235Sgblack@eecs.umich.edu case 0x0: 6267235Sgblack@eecs.umich.edu if (rn == 0xf) { 6277235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, rotation, rm); 6287235Sgblack@eecs.umich.edu } else { 6297235Sgblack@eecs.umich.edu return new Sxtah(machInst, rd, rn, rm, rotation); 6307235Sgblack@eecs.umich.edu } 6317235Sgblack@eecs.umich.edu case 0x1: 6327235Sgblack@eecs.umich.edu if (rn == 0xf) { 6337235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, rotation, rm); 6347235Sgblack@eecs.umich.edu } else { 6357235Sgblack@eecs.umich.edu return new Uxtah(machInst, rd, rn, rm, rotation); 6367235Sgblack@eecs.umich.edu } 6377235Sgblack@eecs.umich.edu case 0x2: 6387235Sgblack@eecs.umich.edu if (rn == 0xf) { 6397235Sgblack@eecs.umich.edu return new Sxtb16(machInst, rd, rotation, rm); 6407235Sgblack@eecs.umich.edu } else { 6417235Sgblack@eecs.umich.edu return new Sxtab16(machInst, rd, rn, rm, rotation); 6427235Sgblack@eecs.umich.edu } 6437235Sgblack@eecs.umich.edu case 0x3: 6447235Sgblack@eecs.umich.edu if (rn == 0xf) { 6457235Sgblack@eecs.umich.edu return new Uxtb16(machInst, rd, rotation, rm); 6467235Sgblack@eecs.umich.edu } else { 6477235Sgblack@eecs.umich.edu return new Uxtab16(machInst, rd, rn, rm, rotation); 6487235Sgblack@eecs.umich.edu } 6497235Sgblack@eecs.umich.edu case 0x4: 6507235Sgblack@eecs.umich.edu if (rn == 0xf) { 6517235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, rotation, rm); 6527235Sgblack@eecs.umich.edu } else { 6537235Sgblack@eecs.umich.edu return new Sxtab(machInst, rd, rn, rm, rotation); 6547235Sgblack@eecs.umich.edu } 6557235Sgblack@eecs.umich.edu case 0x5: 6567235Sgblack@eecs.umich.edu if (rn == 0xf) { 6577235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, rotation, rm); 6587235Sgblack@eecs.umich.edu } else { 6597235Sgblack@eecs.umich.edu return new Uxtab(machInst, rd, rn, rm, rotation); 6607235Sgblack@eecs.umich.edu } 6617235Sgblack@eecs.umich.edu default: 6627235Sgblack@eecs.umich.edu return new Unknown(machInst); 6637213Sgblack@eecs.umich.edu } 6647213Sgblack@eecs.umich.edu } 6657213Sgblack@eecs.umich.edu } else { 6667213Sgblack@eecs.umich.edu if (bits(op2, 3) == 0) { 6677220Sgblack@eecs.umich.edu const IntRegIndex rd = 6687220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 6697220Sgblack@eecs.umich.edu const IntRegIndex rm = 6707220Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 6717213Sgblack@eecs.umich.edu if (bits(op2, 2) == 0x0) { 6727213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 6737213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 6747213Sgblack@eecs.umich.edu switch (op2) { 6757213Sgblack@eecs.umich.edu case 0x0: 6767213Sgblack@eecs.umich.edu switch (op1) { 6777213Sgblack@eecs.umich.edu case 0x1: 6787216Sgblack@eecs.umich.edu return new Sadd16RegCc(machInst, rd, 6797216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6807213Sgblack@eecs.umich.edu case 0x2: 6817224Sgblack@eecs.umich.edu return new SasxRegCc(machInst, rd, 6827224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6837213Sgblack@eecs.umich.edu case 0x6: 6847224Sgblack@eecs.umich.edu return new SsaxRegCc(machInst, rd, 6857224Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6867213Sgblack@eecs.umich.edu case 0x5: 6877218Sgblack@eecs.umich.edu return new Ssub16RegCc(machInst, rd, 6887218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6897213Sgblack@eecs.umich.edu case 0x0: 6907216Sgblack@eecs.umich.edu return new Sadd8RegCc(machInst, rd, 6917216Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6927213Sgblack@eecs.umich.edu case 0x4: 6937218Sgblack@eecs.umich.edu return new Ssub8RegCc(machInst, rd, 6947218Sgblack@eecs.umich.edu rn, rm, 0, LSL); 6957213Sgblack@eecs.umich.edu } 6967213Sgblack@eecs.umich.edu break; 6977213Sgblack@eecs.umich.edu case 0x1: 6987216Sgblack@eecs.umich.edu switch (op1) { 6997216Sgblack@eecs.umich.edu case 0x1: 7007216Sgblack@eecs.umich.edu return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 7017216Sgblack@eecs.umich.edu case 0x2: 7027216Sgblack@eecs.umich.edu return new QasxReg(machInst, rd, rn, rm, 0, LSL); 7037216Sgblack@eecs.umich.edu case 0x6: 7047216Sgblack@eecs.umich.edu return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 7057216Sgblack@eecs.umich.edu case 0x5: 7067216Sgblack@eecs.umich.edu return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 7077216Sgblack@eecs.umich.edu case 0x0: 7087216Sgblack@eecs.umich.edu return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 7097216Sgblack@eecs.umich.edu case 0x4: 7107216Sgblack@eecs.umich.edu return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 7117213Sgblack@eecs.umich.edu } 7127213Sgblack@eecs.umich.edu break; 7137213Sgblack@eecs.umich.edu case 0x2: 7147213Sgblack@eecs.umich.edu switch (op1) { 7157213Sgblack@eecs.umich.edu case 0x1: 7167231Sgblack@eecs.umich.edu return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 7177213Sgblack@eecs.umich.edu case 0x2: 7187231Sgblack@eecs.umich.edu return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 7197213Sgblack@eecs.umich.edu case 0x6: 7207231Sgblack@eecs.umich.edu return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 7217213Sgblack@eecs.umich.edu case 0x5: 7227231Sgblack@eecs.umich.edu return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 7237213Sgblack@eecs.umich.edu case 0x0: 7247231Sgblack@eecs.umich.edu return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 7257213Sgblack@eecs.umich.edu case 0x4: 7267231Sgblack@eecs.umich.edu return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 7277213Sgblack@eecs.umich.edu } 7287213Sgblack@eecs.umich.edu break; 7297213Sgblack@eecs.umich.edu } 7307213Sgblack@eecs.umich.edu } else { 7317213Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 22, 20); 7327213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7337213Sgblack@eecs.umich.edu switch (op2) { 7347213Sgblack@eecs.umich.edu case 0x0: 7357213Sgblack@eecs.umich.edu switch (op1) { 7367213Sgblack@eecs.umich.edu case 0x1: 7377222Sgblack@eecs.umich.edu return new Uadd16RegCc(machInst, rd, 7387222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7397213Sgblack@eecs.umich.edu case 0x2: 7407222Sgblack@eecs.umich.edu return new UasxRegCc(machInst, rd, 7417222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7427213Sgblack@eecs.umich.edu case 0x6: 7437222Sgblack@eecs.umich.edu return new UsaxRegCc(machInst, rd, 7447222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7457213Sgblack@eecs.umich.edu case 0x5: 7467222Sgblack@eecs.umich.edu return new Usub16RegCc(machInst, rd, 7477222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7487213Sgblack@eecs.umich.edu case 0x0: 7497222Sgblack@eecs.umich.edu return new Uadd8RegCc(machInst, rd, 7507222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7517213Sgblack@eecs.umich.edu case 0x4: 7527222Sgblack@eecs.umich.edu return new Usub8RegCc(machInst, rd, 7537222Sgblack@eecs.umich.edu rn, rm, 0, LSL); 7547213Sgblack@eecs.umich.edu } 7557213Sgblack@eecs.umich.edu break; 7567213Sgblack@eecs.umich.edu case 0x1: 7577213Sgblack@eecs.umich.edu switch (op1) { 7587213Sgblack@eecs.umich.edu case 0x1: 7597220Sgblack@eecs.umich.edu return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 7607213Sgblack@eecs.umich.edu case 0x2: 7617220Sgblack@eecs.umich.edu return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 7627213Sgblack@eecs.umich.edu case 0x6: 7637220Sgblack@eecs.umich.edu return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 7647213Sgblack@eecs.umich.edu case 0x5: 7657220Sgblack@eecs.umich.edu return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 7667213Sgblack@eecs.umich.edu case 0x0: 7677220Sgblack@eecs.umich.edu return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 7687213Sgblack@eecs.umich.edu case 0x4: 7697220Sgblack@eecs.umich.edu return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 7707213Sgblack@eecs.umich.edu } 7717213Sgblack@eecs.umich.edu break; 7727213Sgblack@eecs.umich.edu case 0x2: 7737213Sgblack@eecs.umich.edu switch (op1) { 7747213Sgblack@eecs.umich.edu case 0x1: 7757231Sgblack@eecs.umich.edu return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 7767213Sgblack@eecs.umich.edu case 0x2: 7777231Sgblack@eecs.umich.edu return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 7787213Sgblack@eecs.umich.edu case 0x6: 7797231Sgblack@eecs.umich.edu return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 7807213Sgblack@eecs.umich.edu case 0x5: 7817231Sgblack@eecs.umich.edu return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 7827213Sgblack@eecs.umich.edu case 0x0: 7837231Sgblack@eecs.umich.edu return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 7847213Sgblack@eecs.umich.edu case 0x4: 7857231Sgblack@eecs.umich.edu return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 7867213Sgblack@eecs.umich.edu } 7877213Sgblack@eecs.umich.edu break; 7887213Sgblack@eecs.umich.edu } 7897213Sgblack@eecs.umich.edu } 7907213Sgblack@eecs.umich.edu } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 79112258Sgiacomo.travaglini@arm.com const uint32_t op1 = bits(machInst, 22, 20); 7927213Sgblack@eecs.umich.edu const uint32_t op2 = bits(machInst, 5, 4); 7937240Sgblack@eecs.umich.edu const IntRegIndex rd = 7947240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 7957240Sgblack@eecs.umich.edu const IntRegIndex rm = 7967240Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 7977213Sgblack@eecs.umich.edu switch (op1) { 7987213Sgblack@eecs.umich.edu case 0x0: 7997240Sgblack@eecs.umich.edu switch (op2) { 8007240Sgblack@eecs.umich.edu case 0x0: 8017240Sgblack@eecs.umich.edu return new QaddRegCc(machInst, rd, 8027240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8037240Sgblack@eecs.umich.edu case 0x1: 8047240Sgblack@eecs.umich.edu return new QdaddRegCc(machInst, rd, 8057240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8067240Sgblack@eecs.umich.edu case 0x2: 8077240Sgblack@eecs.umich.edu return new QsubRegCc(machInst, rd, 8087240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8097240Sgblack@eecs.umich.edu case 0x3: 8107240Sgblack@eecs.umich.edu return new QdsubRegCc(machInst, rd, 8117240Sgblack@eecs.umich.edu rm, rn, 0, LSL); 8127213Sgblack@eecs.umich.edu } 8137213Sgblack@eecs.umich.edu break; 8147213Sgblack@eecs.umich.edu case 0x1: 8157240Sgblack@eecs.umich.edu switch (op2) { 8167240Sgblack@eecs.umich.edu case 0x0: 8177240Sgblack@eecs.umich.edu return new Rev(machInst, rd, rn); 8187240Sgblack@eecs.umich.edu case 0x1: 8197240Sgblack@eecs.umich.edu return new Rev16(machInst, rd, rn); 8207240Sgblack@eecs.umich.edu case 0x2: 8217250Sgblack@eecs.umich.edu return new Rbit(machInst, rd, rm); 8227240Sgblack@eecs.umich.edu case 0x3: 8237240Sgblack@eecs.umich.edu return new Revsh(machInst, rd, rn); 8247213Sgblack@eecs.umich.edu } 8257213Sgblack@eecs.umich.edu break; 8267213Sgblack@eecs.umich.edu case 0x2: 8277213Sgblack@eecs.umich.edu if (op2 == 0) { 8287240Sgblack@eecs.umich.edu return new Sel(machInst, rd, rn, rm); 8297213Sgblack@eecs.umich.edu } 8307213Sgblack@eecs.umich.edu break; 8317213Sgblack@eecs.umich.edu case 0x3: 8327213Sgblack@eecs.umich.edu if (op2 == 0) { 8337252Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 8347213Sgblack@eecs.umich.edu } 83512258Sgiacomo.travaglini@arm.com break; 83612258Sgiacomo.travaglini@arm.com case 0x4: 83712258Sgiacomo.travaglini@arm.com switch (op2) { 83812258Sgiacomo.travaglini@arm.com case 0x0: 83912258Sgiacomo.travaglini@arm.com return new Crc32b(machInst, rd, rn, rm); 84012258Sgiacomo.travaglini@arm.com case 0x1: 84112258Sgiacomo.travaglini@arm.com return new Crc32h(machInst, rd, rn, rm); 84212258Sgiacomo.travaglini@arm.com case 0x2: 84312258Sgiacomo.travaglini@arm.com return new Crc32w(machInst, rd, rn, rm); 84412258Sgiacomo.travaglini@arm.com } 84512258Sgiacomo.travaglini@arm.com break; 84612258Sgiacomo.travaglini@arm.com case 0x5: 84712258Sgiacomo.travaglini@arm.com switch (op2) { 84812258Sgiacomo.travaglini@arm.com case 0x0: 84912258Sgiacomo.travaglini@arm.com return new Crc32cb(machInst, rd, rn, rm); 85012258Sgiacomo.travaglini@arm.com case 0x1: 85112258Sgiacomo.travaglini@arm.com return new Crc32ch(machInst, rd, rn, rm); 85212258Sgiacomo.travaglini@arm.com case 0x2: 85312258Sgiacomo.travaglini@arm.com return new Crc32cw(machInst, rd, rn, rm); 85412258Sgiacomo.travaglini@arm.com } 85512258Sgiacomo.travaglini@arm.com break; 8567213Sgblack@eecs.umich.edu } 8577213Sgblack@eecs.umich.edu } 8587213Sgblack@eecs.umich.edu return new Unknown(machInst); 8597213Sgblack@eecs.umich.edu } 8607213Sgblack@eecs.umich.edu } 8617213Sgblack@eecs.umich.edu ''' 8627213Sgblack@eecs.umich.edu}}; 8637213Sgblack@eecs.umich.edu 8647141Sgblack@eecs.umich.edudef format Thumb16ShiftAddSubMoveCmp() {{ 8657141Sgblack@eecs.umich.edu decode_block = ''' 8667141Sgblack@eecs.umich.edu { 8677141Sgblack@eecs.umich.edu const uint32_t imm5 = bits(machInst, 10, 6); 8687141Sgblack@eecs.umich.edu const uint32_t imm3 = bits(machInst, 8, 6); 8697141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0); 8707141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 8717141Sgblack@eecs.umich.edu const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 8727141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 8737141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 8747141Sgblack@eecs.umich.edu switch (bits(machInst, 13, 11)) { 8757141Sgblack@eecs.umich.edu case 0x0: // lsl 8767408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8777408Sgblack@eecs.umich.edu return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8787408Sgblack@eecs.umich.edu } else { 8797408Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 8807408Sgblack@eecs.umich.edu } 8817141Sgblack@eecs.umich.edu case 0x1: // lsr 8827408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8837408Sgblack@eecs.umich.edu return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8847408Sgblack@eecs.umich.edu } else { 8857408Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 8867408Sgblack@eecs.umich.edu } 8877141Sgblack@eecs.umich.edu case 0x2: // asr 8887408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8897408Sgblack@eecs.umich.edu return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8907408Sgblack@eecs.umich.edu } else { 8917408Sgblack@eecs.umich.edu return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 8927408Sgblack@eecs.umich.edu } 8937141Sgblack@eecs.umich.edu case 0x3: 8947141Sgblack@eecs.umich.edu switch (bits(machInst, 10, 9)) { 8957141Sgblack@eecs.umich.edu case 0x0: 8967408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 8977408Sgblack@eecs.umich.edu return new AddReg(machInst, rd, rn, rm, 0, LSL); 8987408Sgblack@eecs.umich.edu } else { 8997408Sgblack@eecs.umich.edu return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 9007408Sgblack@eecs.umich.edu } 9017141Sgblack@eecs.umich.edu case 0x1: 9027408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9037408Sgblack@eecs.umich.edu return new SubReg(machInst, rd, rn, rm, 0, LSL); 9047408Sgblack@eecs.umich.edu } else { 9057408Sgblack@eecs.umich.edu return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 9067408Sgblack@eecs.umich.edu } 9077141Sgblack@eecs.umich.edu case 0x2: 9087408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9097408Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm3, true); 9107408Sgblack@eecs.umich.edu } else { 9117408Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd, rn, imm3, true); 9127408Sgblack@eecs.umich.edu } 9137141Sgblack@eecs.umich.edu case 0x3: 9147408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9157408Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm3, true); 9167408Sgblack@eecs.umich.edu } else { 9177408Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd, rn, imm3, true); 9187408Sgblack@eecs.umich.edu } 9197141Sgblack@eecs.umich.edu } 9207141Sgblack@eecs.umich.edu case 0x4: 9217408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9227408Sgblack@eecs.umich.edu return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false); 9237408Sgblack@eecs.umich.edu } else { 9247408Sgblack@eecs.umich.edu return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 9257408Sgblack@eecs.umich.edu } 9267141Sgblack@eecs.umich.edu case 0x5: 9277146Sgblack@eecs.umich.edu return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 9287141Sgblack@eecs.umich.edu case 0x6: 9297408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9307408Sgblack@eecs.umich.edu return new AddImm(machInst, rd8, rd8, imm8, true); 9317408Sgblack@eecs.umich.edu } else { 9327408Sgblack@eecs.umich.edu return new AddImmCc(machInst, rd8, rd8, imm8, true); 9337408Sgblack@eecs.umich.edu } 9347141Sgblack@eecs.umich.edu case 0x7: 9357408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9367408Sgblack@eecs.umich.edu return new SubImm(machInst, rd8, rd8, imm8, true); 9377408Sgblack@eecs.umich.edu } else { 9387408Sgblack@eecs.umich.edu return new SubImmCc(machInst, rd8, rd8, imm8, true); 9397408Sgblack@eecs.umich.edu } 9407141Sgblack@eecs.umich.edu } 9417141Sgblack@eecs.umich.edu } 9427141Sgblack@eecs.umich.edu ''' 9437141Sgblack@eecs.umich.edu}}; 9447141Sgblack@eecs.umich.edu 9457141Sgblack@eecs.umich.edudef format Thumb16DataProcessing() {{ 9467141Sgblack@eecs.umich.edu decode_block = ''' 9477141Sgblack@eecs.umich.edu { 9487141Sgblack@eecs.umich.edu const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 9497141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 9507141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 6)) { 9517141Sgblack@eecs.umich.edu case 0x0: 9527408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9537408Sgblack@eecs.umich.edu return new AndReg(machInst, rdn, rdn, rm, 0, LSL); 9547408Sgblack@eecs.umich.edu } else { 9557408Sgblack@eecs.umich.edu return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 9567408Sgblack@eecs.umich.edu } 9577141Sgblack@eecs.umich.edu case 0x1: 9587408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9597408Sgblack@eecs.umich.edu return new EorReg(machInst, rdn, rdn, rm, 0, LSL); 9607408Sgblack@eecs.umich.edu } else { 9617408Sgblack@eecs.umich.edu return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 9627408Sgblack@eecs.umich.edu } 9637141Sgblack@eecs.umich.edu case 0x2: //lsl 9647408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9657408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 9667408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSL); 9677408Sgblack@eecs.umich.edu } else { 9687408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 9697408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSL); 9707408Sgblack@eecs.umich.edu } 9717141Sgblack@eecs.umich.edu case 0x3: //lsr 9727408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9737408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 9747408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSR); 9757408Sgblack@eecs.umich.edu } else { 9767408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 9777408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, LSR); 9787408Sgblack@eecs.umich.edu } 9797141Sgblack@eecs.umich.edu case 0x4: //asr 9807408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9817408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 9827408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ASR); 9837408Sgblack@eecs.umich.edu } else { 9847408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 9857408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ASR); 9867408Sgblack@eecs.umich.edu } 9877141Sgblack@eecs.umich.edu case 0x5: 9887408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9897408Sgblack@eecs.umich.edu return new AdcReg(machInst, rdn, rdn, rm, 0, LSL); 9907408Sgblack@eecs.umich.edu } else { 9917408Sgblack@eecs.umich.edu return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 9927408Sgblack@eecs.umich.edu } 9937141Sgblack@eecs.umich.edu case 0x6: 9947408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 9957408Sgblack@eecs.umich.edu return new SbcReg(machInst, rdn, rdn, rm, 0, LSL); 9967408Sgblack@eecs.umich.edu } else { 9977408Sgblack@eecs.umich.edu return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 9987408Sgblack@eecs.umich.edu } 9997141Sgblack@eecs.umich.edu case 0x7: // ror 10007408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10017408Sgblack@eecs.umich.edu return new MovRegReg(machInst, rdn, 10027408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ROR); 10037408Sgblack@eecs.umich.edu } else { 10047408Sgblack@eecs.umich.edu return new MovRegRegCc(machInst, rdn, 10057408Sgblack@eecs.umich.edu INTREG_ZERO, rdn, rm, ROR); 10067408Sgblack@eecs.umich.edu } 10077141Sgblack@eecs.umich.edu case 0x8: 10087183Sgblack@eecs.umich.edu return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10097141Sgblack@eecs.umich.edu case 0x9: 10107408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10117408Sgblack@eecs.umich.edu return new RsbImm(machInst, rdn, rm, 0, true); 10127408Sgblack@eecs.umich.edu } else { 10137408Sgblack@eecs.umich.edu return new RsbImmCc(machInst, rdn, rm, 0, true); 10147408Sgblack@eecs.umich.edu } 10157141Sgblack@eecs.umich.edu case 0xa: 10167183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10177141Sgblack@eecs.umich.edu case 0xb: 10187183Sgblack@eecs.umich.edu return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10197141Sgblack@eecs.umich.edu case 0xc: 10207408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10217408Sgblack@eecs.umich.edu return new OrrReg(machInst, rdn, rdn, rm, 0, LSL); 10227408Sgblack@eecs.umich.edu } else { 10237408Sgblack@eecs.umich.edu return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 10247408Sgblack@eecs.umich.edu } 10257141Sgblack@eecs.umich.edu case 0xd: 10267408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10277408Sgblack@eecs.umich.edu return new Mul(machInst, rdn, rm, rdn); 10287408Sgblack@eecs.umich.edu } else { 10297408Sgblack@eecs.umich.edu return new MulCc(machInst, rdn, rm, rdn); 10307408Sgblack@eecs.umich.edu } 10317141Sgblack@eecs.umich.edu case 0xe: 10327408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10337408Sgblack@eecs.umich.edu return new BicReg(machInst, rdn, rdn, rm, 0, LSL); 10347408Sgblack@eecs.umich.edu } else { 10357408Sgblack@eecs.umich.edu return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 10367408Sgblack@eecs.umich.edu } 10377141Sgblack@eecs.umich.edu case 0xf: 10387408Sgblack@eecs.umich.edu if (machInst.itstateMask) { 10397408Sgblack@eecs.umich.edu return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 10407408Sgblack@eecs.umich.edu } else { 10417408Sgblack@eecs.umich.edu return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 10427408Sgblack@eecs.umich.edu } 10437141Sgblack@eecs.umich.edu } 10447141Sgblack@eecs.umich.edu } 10457141Sgblack@eecs.umich.edu ''' 10467141Sgblack@eecs.umich.edu}}; 10477141Sgblack@eecs.umich.edu 10487141Sgblack@eecs.umich.edudef format Thumb16SpecDataAndBx() {{ 10497141Sgblack@eecs.umich.edu decode_block = ''' 10507141Sgblack@eecs.umich.edu { 10517141Sgblack@eecs.umich.edu const IntRegIndex rdn = 10527141Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 10537141Sgblack@eecs.umich.edu (bits(machInst, 7) << 3)); 10547141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 10557141Sgblack@eecs.umich.edu switch (bits(machInst, 9, 8)) { 10567141Sgblack@eecs.umich.edu case 0x0: 10577146Sgblack@eecs.umich.edu return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 10587141Sgblack@eecs.umich.edu case 0x1: 10597183Sgblack@eecs.umich.edu return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 10607141Sgblack@eecs.umich.edu case 0x2: 10617146Sgblack@eecs.umich.edu return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 10627141Sgblack@eecs.umich.edu case 0x3: 10637154Sgblack@eecs.umich.edu if (bits(machInst, 7) == 0) { 10647154Sgblack@eecs.umich.edu return new BxReg(machInst, 10657154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 10668909SAli.Saidi@ARM.com COND_UC); 10677154Sgblack@eecs.umich.edu } else { 10687154Sgblack@eecs.umich.edu return new BlxReg(machInst, 10697154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 10708909SAli.Saidi@ARM.com COND_UC); 10717154Sgblack@eecs.umich.edu } 10727141Sgblack@eecs.umich.edu } 10737141Sgblack@eecs.umich.edu } 10747141Sgblack@eecs.umich.edu ''' 10757141Sgblack@eecs.umich.edu}}; 10767141Sgblack@eecs.umich.edu 10777141Sgblack@eecs.umich.edudef format Thumb16Adr() {{ 10787141Sgblack@eecs.umich.edu decode_block = ''' 10797141Sgblack@eecs.umich.edu { 10807141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 10817141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 10827185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 10837141Sgblack@eecs.umich.edu } 10847141Sgblack@eecs.umich.edu ''' 10857141Sgblack@eecs.umich.edu}}; 10867141Sgblack@eecs.umich.edu 10877141Sgblack@eecs.umich.edudef format Thumb16AddSp() {{ 10887141Sgblack@eecs.umich.edu decode_block = ''' 10897141Sgblack@eecs.umich.edu { 10907141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 10917141Sgblack@eecs.umich.edu const uint32_t imm8 = bits(machInst, 7, 0) << 2; 10927146Sgblack@eecs.umich.edu return new AddImm(machInst, rd, INTREG_SP, imm8, true); 10937141Sgblack@eecs.umich.edu } 10947141Sgblack@eecs.umich.edu ''' 10957141Sgblack@eecs.umich.edu}}; 10967141Sgblack@eecs.umich.edu 10977418Sgblack@eecs.umich.edudef format ArmMisc() {{ 10987418Sgblack@eecs.umich.edu decode_block = ''' 10997418Sgblack@eecs.umich.edu { 11007418Sgblack@eecs.umich.edu const uint32_t unrotated = bits(machInst, 7, 0); 11017418Sgblack@eecs.umich.edu const uint32_t rotation = (bits(machInst, 11, 8) << 1); 11027418Sgblack@eecs.umich.edu const uint32_t imm = rotate_imm(unrotated, rotation); 11037418Sgblack@eecs.umich.edu const uint8_t byteMask = bits(machInst, 19, 16); 11047418Sgblack@eecs.umich.edu switch (OPCODE) { 11057418Sgblack@eecs.umich.edu case 0x8: 11067418Sgblack@eecs.umich.edu return new MovImm(machInst, (IntRegIndex)(uint32_t)RD, 11077418Sgblack@eecs.umich.edu (IntRegIndex)INTREG_ZERO, 11087418Sgblack@eecs.umich.edu bits(machInst, 11, 0) | (bits(machInst, 19, 16) << 12), 11097418Sgblack@eecs.umich.edu false); 11107418Sgblack@eecs.umich.edu case 0x9: 11117418Sgblack@eecs.umich.edu if (RN == 0) { 11127418Sgblack@eecs.umich.edu switch (IMM) { 11137418Sgblack@eecs.umich.edu case 0x0: 11147418Sgblack@eecs.umich.edu return new NopInst(machInst); 11157418Sgblack@eecs.umich.edu case 0x1: 11167418Sgblack@eecs.umich.edu return new YieldInst(machInst); 11177418Sgblack@eecs.umich.edu case 0x2: 11187418Sgblack@eecs.umich.edu return new WfeInst(machInst); 11197418Sgblack@eecs.umich.edu case 0x3: 11207418Sgblack@eecs.umich.edu return new WfiInst(machInst); 11217418Sgblack@eecs.umich.edu case 0x4: 11227418Sgblack@eecs.umich.edu return new SevInst(machInst); 11237418Sgblack@eecs.umich.edu default: 11247418Sgblack@eecs.umich.edu return new Unknown(machInst); 11257418Sgblack@eecs.umich.edu } 11267418Sgblack@eecs.umich.edu } else { 11277418Sgblack@eecs.umich.edu return new MsrCpsrImm(machInst, imm, byteMask); 11287418Sgblack@eecs.umich.edu } 11297418Sgblack@eecs.umich.edu case 0xa: 11307418Sgblack@eecs.umich.edu { 11317418Sgblack@eecs.umich.edu const uint32_t timm = (bits(machInst, 19, 16) << 12) | 11327418Sgblack@eecs.umich.edu bits(machInst, 11, 0); 11337418Sgblack@eecs.umich.edu return new MovtImm(machInst, (IntRegIndex)(uint32_t)RD, 11347418Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)RD, timm, true); 11357418Sgblack@eecs.umich.edu } 11367418Sgblack@eecs.umich.edu case 0xb: 11377418Sgblack@eecs.umich.edu return new MsrSpsrImm(machInst, imm, byteMask); 11387418Sgblack@eecs.umich.edu default: 11397418Sgblack@eecs.umich.edu return new Unknown(machInst); 11407418Sgblack@eecs.umich.edu } 11417418Sgblack@eecs.umich.edu } 11427418Sgblack@eecs.umich.edu ''' 11437418Sgblack@eecs.umich.edu}}; 11447418Sgblack@eecs.umich.edu 11457141Sgblack@eecs.umich.edudef format Thumb16Misc() {{ 11467141Sgblack@eecs.umich.edu decode_block = ''' 11477141Sgblack@eecs.umich.edu { 11487141Sgblack@eecs.umich.edu switch (bits(machInst, 11, 8)) { 11497141Sgblack@eecs.umich.edu case 0x0: 11507141Sgblack@eecs.umich.edu if (bits(machInst, 7)) { 11517146Sgblack@eecs.umich.edu return new SubImm(machInst, INTREG_SP, INTREG_SP, 11527141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 11537141Sgblack@eecs.umich.edu } else { 11547146Sgblack@eecs.umich.edu return new AddImm(machInst, INTREG_SP, INTREG_SP, 11557141Sgblack@eecs.umich.edu bits(machInst, 6, 0) << 2, true); 11567141Sgblack@eecs.umich.edu } 11577141Sgblack@eecs.umich.edu case 0x2: 11587235Sgblack@eecs.umich.edu { 11597235Sgblack@eecs.umich.edu const IntRegIndex rd = 11607235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 11617235Sgblack@eecs.umich.edu const IntRegIndex rm = 11627235Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 11637235Sgblack@eecs.umich.edu switch (bits(machInst, 7, 6)) { 11647235Sgblack@eecs.umich.edu case 0x0: 11657235Sgblack@eecs.umich.edu return new Sxth(machInst, rd, 0, rm); 11667235Sgblack@eecs.umich.edu case 0x1: 11677235Sgblack@eecs.umich.edu return new Sxtb(machInst, rd, 0, rm); 11687235Sgblack@eecs.umich.edu case 0x2: 11697235Sgblack@eecs.umich.edu return new Uxth(machInst, rd, 0, rm); 11707235Sgblack@eecs.umich.edu case 0x3: 11717235Sgblack@eecs.umich.edu return new Uxtb(machInst, rd, 0, rm); 11727235Sgblack@eecs.umich.edu } 11737141Sgblack@eecs.umich.edu } 11747432Sgblack@eecs.umich.edu case 0x1: 11757141Sgblack@eecs.umich.edu case 0x3: 11767154Sgblack@eecs.umich.edu return new Cbz(machInst, 11777154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 11787154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 11797154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 11807141Sgblack@eecs.umich.edu case 0x4: 11817141Sgblack@eecs.umich.edu case 0x5: 11827201Sgblack@eecs.umich.edu { 11837201Sgblack@eecs.umich.edu const uint32_t m = bits(machInst, 8); 11847201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 11857201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, false, false, false, 11867201Sgblack@eecs.umich.edu true, false, regList); 11877201Sgblack@eecs.umich.edu } 11887141Sgblack@eecs.umich.edu case 0x6: 11897141Sgblack@eecs.umich.edu { 11907141Sgblack@eecs.umich.edu const uint32_t opBits = bits(machInst, 7, 5); 11917141Sgblack@eecs.umich.edu if (opBits == 2) { 11927308Sgblack@eecs.umich.edu return new Setend(machInst, bits(machInst, 3)); 11937141Sgblack@eecs.umich.edu } else if (opBits == 3) { 11947316Sgblack@eecs.umich.edu const bool enable = (bits(machInst, 4) == 0); 11957316Sgblack@eecs.umich.edu const uint32_t mods = (bits(machInst, 2, 0) << 5) | 11967316Sgblack@eecs.umich.edu ((enable ? 1 : 0) << 9); 11977316Sgblack@eecs.umich.edu return new Cps(machInst, mods); 11987141Sgblack@eecs.umich.edu } 11997141Sgblack@eecs.umich.edu } 12007141Sgblack@eecs.umich.edu case 0xa: 12017212Sgblack@eecs.umich.edu { 120212542Sgiacomo.travaglini@arm.com const uint8_t op1 = bits(machInst, 7, 6); 120312542Sgiacomo.travaglini@arm.com if (op1 == 0x2) { 120412542Sgiacomo.travaglini@arm.com return new Hlt(machInst, bits(machInst, 5, 0)); 120512542Sgiacomo.travaglini@arm.com } else { 120612542Sgiacomo.travaglini@arm.com IntRegIndex rd = 120712542Sgiacomo.travaglini@arm.com (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 120812542Sgiacomo.travaglini@arm.com IntRegIndex rm = 120912542Sgiacomo.travaglini@arm.com (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 121012542Sgiacomo.travaglini@arm.com 121112542Sgiacomo.travaglini@arm.com switch (op1) { 121212542Sgiacomo.travaglini@arm.com case 0x0: 121312542Sgiacomo.travaglini@arm.com return new Rev(machInst, rd, rm); 121412542Sgiacomo.travaglini@arm.com case 0x1: 121512542Sgiacomo.travaglini@arm.com return new Rev16(machInst, rd, rm); 121612542Sgiacomo.travaglini@arm.com case 0x3: 121712542Sgiacomo.travaglini@arm.com return new Revsh(machInst, rd, rm); 121812542Sgiacomo.travaglini@arm.com default: 121912542Sgiacomo.travaglini@arm.com break; 122012542Sgiacomo.travaglini@arm.com } 12217212Sgblack@eecs.umich.edu } 12227141Sgblack@eecs.umich.edu } 12237141Sgblack@eecs.umich.edu break; 12247432Sgblack@eecs.umich.edu case 0x9: 12257141Sgblack@eecs.umich.edu case 0xb: 12267154Sgblack@eecs.umich.edu return new Cbnz(machInst, 12277154Sgblack@eecs.umich.edu (bits(machInst, 9) << 6) | 12287154Sgblack@eecs.umich.edu (bits(machInst, 7, 3) << 1), 12297154Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 12307141Sgblack@eecs.umich.edu case 0xc: 12317141Sgblack@eecs.umich.edu case 0xd: 12327201Sgblack@eecs.umich.edu { 12337201Sgblack@eecs.umich.edu const uint32_t p = bits(machInst, 8); 12347201Sgblack@eecs.umich.edu const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 12357201Sgblack@eecs.umich.edu return new LdmStm(machInst, INTREG_SP, true, true, false, 12367201Sgblack@eecs.umich.edu true, true, regList); 12377201Sgblack@eecs.umich.edu } 12387141Sgblack@eecs.umich.edu case 0xe: 12397410Sgblack@eecs.umich.edu return new BkptInst(machInst); 12407141Sgblack@eecs.umich.edu case 0xf: 12417141Sgblack@eecs.umich.edu if (bits(machInst, 3, 0) != 0) 12427408Sgblack@eecs.umich.edu return new ItInst(machInst); 12437141Sgblack@eecs.umich.edu switch (bits(machInst, 7, 4)) { 12447141Sgblack@eecs.umich.edu case 0x0: 12457248Sgblack@eecs.umich.edu return new NopInst(machInst); 12467141Sgblack@eecs.umich.edu case 0x1: 12477419Sgblack@eecs.umich.edu return new YieldInst(machInst); 12487141Sgblack@eecs.umich.edu case 0x2: 12497419Sgblack@eecs.umich.edu return new WfeInst(machInst); 12507141Sgblack@eecs.umich.edu case 0x3: 12517419Sgblack@eecs.umich.edu return new WfiInst(machInst); 12527141Sgblack@eecs.umich.edu case 0x4: 12537419Sgblack@eecs.umich.edu return new SevInst(machInst); 12547141Sgblack@eecs.umich.edu default: 12557141Sgblack@eecs.umich.edu return new WarnUnimplemented("unallocated_hint", machInst); 12567141Sgblack@eecs.umich.edu } 12577141Sgblack@eecs.umich.edu default: 12587141Sgblack@eecs.umich.edu break; 12597141Sgblack@eecs.umich.edu } 12607141Sgblack@eecs.umich.edu return new Unknown(machInst); 12617141Sgblack@eecs.umich.edu } 12627141Sgblack@eecs.umich.edu ''' 12637141Sgblack@eecs.umich.edu}}; 12647141Sgblack@eecs.umich.edu 12657141Sgblack@eecs.umich.edudef format Thumb32DataProcModImm() {{ 12667141Sgblack@eecs.umich.edu 12677141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 12687141Sgblack@eecs.umich.edu return ''' 12697141Sgblack@eecs.umich.edu if (s) { 12707146Sgblack@eecs.umich.edu return new %(mnem)sImmCc(machInst, %(dest)s, 12717183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 12727141Sgblack@eecs.umich.edu } else { 12737146Sgblack@eecs.umich.edu return new %(mnem)sImm(machInst, %(dest)s, 12747183Sgblack@eecs.umich.edu %(op1)s, imm, rotC); 12757141Sgblack@eecs.umich.edu } 12767141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 12777141Sgblack@eecs.umich.edu 12787141Sgblack@eecs.umich.edu decode_block = ''' 12797141Sgblack@eecs.umich.edu { 12807141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 12817141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 12827141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 12837141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 12847141Sgblack@eecs.umich.edu const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 12857141Sgblack@eecs.umich.edu bits(machInst, 14, 12); 12867183Sgblack@eecs.umich.edu const bool rotC = ctrlImm > 3; 12877141Sgblack@eecs.umich.edu const uint32_t dataImm = bits(machInst, 7, 0); 12887141Sgblack@eecs.umich.edu const uint32_t imm = modified_imm(ctrlImm, dataImm); 12897141Sgblack@eecs.umich.edu switch (op) { 12907141Sgblack@eecs.umich.edu case 0x0: 12917141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 12927141Sgblack@eecs.umich.edu %(tst)s 12937141Sgblack@eecs.umich.edu } else { 12947141Sgblack@eecs.umich.edu %(and)s 12957141Sgblack@eecs.umich.edu } 12967141Sgblack@eecs.umich.edu case 0x1: 12977141Sgblack@eecs.umich.edu %(bic)s 12987141Sgblack@eecs.umich.edu case 0x2: 12997141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13007141Sgblack@eecs.umich.edu %(mov)s 13017141Sgblack@eecs.umich.edu } else { 13027141Sgblack@eecs.umich.edu %(orr)s 13037141Sgblack@eecs.umich.edu } 13047141Sgblack@eecs.umich.edu case 0x3: 13057141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 13067141Sgblack@eecs.umich.edu %(mvn)s 13077141Sgblack@eecs.umich.edu } else { 13087141Sgblack@eecs.umich.edu %(orn)s 13097141Sgblack@eecs.umich.edu } 13107141Sgblack@eecs.umich.edu case 0x4: 13117141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13127141Sgblack@eecs.umich.edu %(teq)s 13137141Sgblack@eecs.umich.edu } else { 13147141Sgblack@eecs.umich.edu %(eor)s 13157141Sgblack@eecs.umich.edu } 13167141Sgblack@eecs.umich.edu case 0x8: 13177141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13187141Sgblack@eecs.umich.edu %(cmn)s 13197141Sgblack@eecs.umich.edu } else { 13207141Sgblack@eecs.umich.edu %(add)s 13217141Sgblack@eecs.umich.edu } 13227141Sgblack@eecs.umich.edu case 0xa: 13237141Sgblack@eecs.umich.edu %(adc)s 13247141Sgblack@eecs.umich.edu case 0xb: 13257141Sgblack@eecs.umich.edu %(sbc)s 13267141Sgblack@eecs.umich.edu case 0xd: 13277141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 13287141Sgblack@eecs.umich.edu %(cmp)s 13297141Sgblack@eecs.umich.edu } else { 13307141Sgblack@eecs.umich.edu %(sub)s 13317141Sgblack@eecs.umich.edu } 13327141Sgblack@eecs.umich.edu case 0xe: 13337141Sgblack@eecs.umich.edu %(rsb)s 13347141Sgblack@eecs.umich.edu default: 13357141Sgblack@eecs.umich.edu return new Unknown(machInst); 13367141Sgblack@eecs.umich.edu } 13377141Sgblack@eecs.umich.edu } 13387141Sgblack@eecs.umich.edu ''' % { 13397141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 13407141Sgblack@eecs.umich.edu "and" : decInst("And"), 13417141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 13427141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 13437141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 13447141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 13457141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 13467141Sgblack@eecs.umich.edu "teq" : decInst("Teq", dest="INTREG_ZERO"), 13477141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 13487141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 13497141Sgblack@eecs.umich.edu "add" : decInst("Add"), 13507141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 13517141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 13527141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 13537141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 13547141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 13557141Sgblack@eecs.umich.edu } 13567141Sgblack@eecs.umich.edu}}; 13577141Sgblack@eecs.umich.edu 13587157Sgblack@eecs.umich.edudef format Thumb32DataProcPlainBin() {{ 13597157Sgblack@eecs.umich.edu decode_block = ''' 13607157Sgblack@eecs.umich.edu { 13617157Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 20); 13627157Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 13637157Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 13647157Sgblack@eecs.umich.edu switch (op) { 13657157Sgblack@eecs.umich.edu case 0x0: 13667157Sgblack@eecs.umich.edu { 13677157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 13687157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 13697157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 13707185Sgblack@eecs.umich.edu if (rn == 0xf) { 13717185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)1, 13727185Sgblack@eecs.umich.edu imm, false); 13737185Sgblack@eecs.umich.edu } else { 13747185Sgblack@eecs.umich.edu return new AddImm(machInst, rd, rn, imm, true); 13757185Sgblack@eecs.umich.edu } 13767157Sgblack@eecs.umich.edu } 13777157Sgblack@eecs.umich.edu case 0x4: 13787157Sgblack@eecs.umich.edu { 13797157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 13807157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 13817157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 13827157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 13837157Sgblack@eecs.umich.edu return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 13847157Sgblack@eecs.umich.edu } 13857157Sgblack@eecs.umich.edu case 0xa: 13867157Sgblack@eecs.umich.edu { 13877157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 13887157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 13897157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11); 13907185Sgblack@eecs.umich.edu if (rn == 0xf) { 13917185Sgblack@eecs.umich.edu return new AdrImm(machInst, rd, (IntRegIndex)0, 13927185Sgblack@eecs.umich.edu imm, false); 13937185Sgblack@eecs.umich.edu } else { 13947185Sgblack@eecs.umich.edu return new SubImm(machInst, rd, rn, imm, true); 13957185Sgblack@eecs.umich.edu } 13967157Sgblack@eecs.umich.edu } 13977157Sgblack@eecs.umich.edu case 0xc: 13987157Sgblack@eecs.umich.edu { 13997157Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 0) | 14007157Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 8) | 14017157Sgblack@eecs.umich.edu (bits(machInst, 26) << 11) | 14027157Sgblack@eecs.umich.edu (bits(machInst, 19, 16) << 12); 14037157Sgblack@eecs.umich.edu return new MovtImm(machInst, rd, rd, imm, true); 14047157Sgblack@eecs.umich.edu } 14057157Sgblack@eecs.umich.edu case 0x12: 14067157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 14077227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14087227Sgblack@eecs.umich.edu return new Ssat16(machInst, rd, satImm + 1, rn); 14097157Sgblack@eecs.umich.edu } 14107157Sgblack@eecs.umich.edu // Fall through on purpose... 14117157Sgblack@eecs.umich.edu case 0x10: 14127227Sgblack@eecs.umich.edu { 14137227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14147227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 14157227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14167227Sgblack@eecs.umich.edu const ArmShiftType type = 14177227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 14187227Sgblack@eecs.umich.edu return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 14197227Sgblack@eecs.umich.edu } 14207157Sgblack@eecs.umich.edu case 0x14: 14217256Sgblack@eecs.umich.edu { 14227256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 14237256Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14247256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 4, 0); 14257256Sgblack@eecs.umich.edu return new Sbfx(machInst, rd, rn, lsb, msb); 14267256Sgblack@eecs.umich.edu } 14277157Sgblack@eecs.umich.edu case 0x16: 14287258Sgblack@eecs.umich.edu { 14297258Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 14307258Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14317258Sgblack@eecs.umich.edu const uint32_t msb = bits(machInst, 4, 0); 14327258Sgblack@eecs.umich.edu if (rn == 0xf) { 14337258Sgblack@eecs.umich.edu return new Bfc(machInst, rd, rd, lsb, msb); 14347258Sgblack@eecs.umich.edu } else { 14357258Sgblack@eecs.umich.edu return new Bfi(machInst, rd, rn, lsb, msb); 14367258Sgblack@eecs.umich.edu } 14377157Sgblack@eecs.umich.edu } 14387157Sgblack@eecs.umich.edu case 0x1a: 14397157Sgblack@eecs.umich.edu if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 14407227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14417227Sgblack@eecs.umich.edu return new Usat16(machInst, rd, satImm, rn); 14427157Sgblack@eecs.umich.edu } 14437157Sgblack@eecs.umich.edu // Fall through on purpose... 14447157Sgblack@eecs.umich.edu case 0x18: 14457227Sgblack@eecs.umich.edu { 14467227Sgblack@eecs.umich.edu const uint32_t satImm = bits(machInst, 4, 0); 14477227Sgblack@eecs.umich.edu const uint32_t imm = bits(machInst, 7, 6) | 14487227Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14497227Sgblack@eecs.umich.edu const ArmShiftType type = 14507227Sgblack@eecs.umich.edu (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 14517227Sgblack@eecs.umich.edu return new Usat(machInst, rd, satImm, rn, imm, type); 14527227Sgblack@eecs.umich.edu } 14537157Sgblack@eecs.umich.edu case 0x1c: 14547256Sgblack@eecs.umich.edu { 14557256Sgblack@eecs.umich.edu const uint32_t lsb = bits(machInst, 7, 6) | 14567256Sgblack@eecs.umich.edu (bits(machInst, 14, 12) << 2); 14577256Sgblack@eecs.umich.edu const uint32_t msb = lsb + bits(machInst, 4, 0); 14587256Sgblack@eecs.umich.edu return new Ubfx(machInst, rd, rn, lsb, msb); 14597256Sgblack@eecs.umich.edu } 14607157Sgblack@eecs.umich.edu default: 14617157Sgblack@eecs.umich.edu return new Unknown(machInst); 14627157Sgblack@eecs.umich.edu } 14637157Sgblack@eecs.umich.edu } 14647157Sgblack@eecs.umich.edu ''' 14657157Sgblack@eecs.umich.edu}}; 14667157Sgblack@eecs.umich.edu 14677141Sgblack@eecs.umich.edudef format Thumb32DataProcShiftReg() {{ 14687141Sgblack@eecs.umich.edu 14697141Sgblack@eecs.umich.edu def decInst(mnem, dest="rd", op1="rn"): 14707141Sgblack@eecs.umich.edu return ''' 14717141Sgblack@eecs.umich.edu if (s) { 14727146Sgblack@eecs.umich.edu return new %(mnem)sRegCc(machInst, %(dest)s, 14737141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 14747141Sgblack@eecs.umich.edu } else { 14757146Sgblack@eecs.umich.edu return new %(mnem)sReg(machInst, %(dest)s, 14767141Sgblack@eecs.umich.edu %(op1)s, rm, amt, type); 14777141Sgblack@eecs.umich.edu } 14787141Sgblack@eecs.umich.edu ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 14797141Sgblack@eecs.umich.edu 14807141Sgblack@eecs.umich.edu decode_block = ''' 14817141Sgblack@eecs.umich.edu { 14827141Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 24, 21); 14837141Sgblack@eecs.umich.edu const bool s = (bits(machInst, 20) == 1); 14847141Sgblack@eecs.umich.edu const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 14857141Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 14867141Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 14877141Sgblack@eecs.umich.edu const uint32_t amt = (bits(machInst, 14, 12) << 2) | 14887141Sgblack@eecs.umich.edu bits(machInst, 7, 6); 14897141Sgblack@eecs.umich.edu const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 14907141Sgblack@eecs.umich.edu switch (op) { 14917141Sgblack@eecs.umich.edu case 0x0: 14927141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 14937141Sgblack@eecs.umich.edu %(tst)s 14947141Sgblack@eecs.umich.edu } else { 14957141Sgblack@eecs.umich.edu %(and)s 14967141Sgblack@eecs.umich.edu } 14977141Sgblack@eecs.umich.edu case 0x1: 14987141Sgblack@eecs.umich.edu %(bic)s 14997141Sgblack@eecs.umich.edu case 0x2: 15007141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 15017141Sgblack@eecs.umich.edu %(mov)s 15027141Sgblack@eecs.umich.edu } else { 15037141Sgblack@eecs.umich.edu %(orr)s 15047141Sgblack@eecs.umich.edu } 15057141Sgblack@eecs.umich.edu case 0x3: 15067141Sgblack@eecs.umich.edu if (rn == INTREG_PC) { 15077141Sgblack@eecs.umich.edu %(mvn)s 15087141Sgblack@eecs.umich.edu } else { 15097141Sgblack@eecs.umich.edu %(orn)s 15107141Sgblack@eecs.umich.edu } 15117141Sgblack@eecs.umich.edu case 0x4: 15127141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15137141Sgblack@eecs.umich.edu %(teq)s 15147141Sgblack@eecs.umich.edu } else { 15157141Sgblack@eecs.umich.edu %(eor)s 15167141Sgblack@eecs.umich.edu } 15177141Sgblack@eecs.umich.edu case 0x6: 15187237Sgblack@eecs.umich.edu if (type) { 15197237Sgblack@eecs.umich.edu return new PkhtbReg(machInst, rd, rn, rm, amt, type); 15207237Sgblack@eecs.umich.edu } else { 15217237Sgblack@eecs.umich.edu return new PkhbtReg(machInst, rd, rn, rm, amt, type); 15227237Sgblack@eecs.umich.edu } 15237141Sgblack@eecs.umich.edu case 0x8: 15247141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15257141Sgblack@eecs.umich.edu %(cmn)s 15267141Sgblack@eecs.umich.edu } else { 15277141Sgblack@eecs.umich.edu %(add)s 15287141Sgblack@eecs.umich.edu } 15297141Sgblack@eecs.umich.edu case 0xa: 15307141Sgblack@eecs.umich.edu %(adc)s 15317141Sgblack@eecs.umich.edu case 0xb: 15327141Sgblack@eecs.umich.edu %(sbc)s 15337141Sgblack@eecs.umich.edu case 0xd: 15347141Sgblack@eecs.umich.edu if (rd == INTREG_PC) { 15357141Sgblack@eecs.umich.edu %(cmp)s 15367141Sgblack@eecs.umich.edu } else { 15377141Sgblack@eecs.umich.edu %(sub)s 15387141Sgblack@eecs.umich.edu } 15397141Sgblack@eecs.umich.edu case 0xe: 15407141Sgblack@eecs.umich.edu %(rsb)s 15417141Sgblack@eecs.umich.edu default: 15427141Sgblack@eecs.umich.edu return new Unknown(machInst); 15437141Sgblack@eecs.umich.edu } 15447141Sgblack@eecs.umich.edu } 15457141Sgblack@eecs.umich.edu ''' % { 15467141Sgblack@eecs.umich.edu "tst" : decInst("Tst", "INTREG_ZERO"), 15477141Sgblack@eecs.umich.edu "and" : decInst("And"), 15487141Sgblack@eecs.umich.edu "bic" : decInst("Bic"), 15497141Sgblack@eecs.umich.edu "mov" : decInst("Mov", op1="INTREG_ZERO"), 15507141Sgblack@eecs.umich.edu "orr" : decInst("Orr"), 15517141Sgblack@eecs.umich.edu "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 15527141Sgblack@eecs.umich.edu "orn" : decInst("Orn"), 15537141Sgblack@eecs.umich.edu "teq" : decInst("Teq", "INTREG_ZERO"), 15547141Sgblack@eecs.umich.edu "eor" : decInst("Eor"), 15557141Sgblack@eecs.umich.edu "cmn" : decInst("Cmn", "INTREG_ZERO"), 15567141Sgblack@eecs.umich.edu "add" : decInst("Add"), 15577141Sgblack@eecs.umich.edu "adc" : decInst("Adc"), 15587141Sgblack@eecs.umich.edu "sbc" : decInst("Sbc"), 15597141Sgblack@eecs.umich.edu "cmp" : decInst("Cmp", "INTREG_ZERO"), 15607141Sgblack@eecs.umich.edu "sub" : decInst("Sub"), 15617141Sgblack@eecs.umich.edu "rsb" : decInst("Rsb") 15627141Sgblack@eecs.umich.edu } 15637141Sgblack@eecs.umich.edu}}; 1564