breakpoint.isa revision 7189
12SN/A// -*- mode:c++ -*- 21762SN/A 32SN/A// Copyright (c) 2010 ARM Limited 42SN/A// All rights reserved 52SN/A// 62SN/A// The license below extends only to copyright in the software and shall 72SN/A// not be construed as granting a license to any other intellectual 82SN/A// property including but not limited to intellectual property relating 92SN/A// to a hardware implementation of the functionality of the software 102SN/A// licensed hereunder. You may use the software subject to the license 112SN/A// terms below provided that you ensure that this notice is replicated 122SN/A// unmodified and in its entirety in all distributions of the software, 132SN/A// modified or unmodified, in source code or in binary form. 142SN/A// 152SN/A// Copyright (c) 2007-2008 The Florida State University 162SN/A// All rights reserved. 172SN/A// 182SN/A// Redistribution and use in source and binary forms, with or without 192SN/A// modification, are permitted provided that the following conditions are 202SN/A// met: redistributions of source code must retain the above copyright 212SN/A// notice, this list of conditions and the following disclaimer; 222SN/A// redistributions in binary form must reproduce the above copyright 232SN/A// notice, this list of conditions and the following disclaimer in the 242SN/A// documentation and/or other materials provided with the distribution; 252SN/A// neither the name of the copyright holders nor the names of its 262SN/A// contributors may be used to endorse or promote products derived from 272665SN/A// this software without specific prior written permission. 282665SN/A// 292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336214Snate@binkert.org// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376214Snate@binkert.org// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386214Snate@binkert.org// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402SN/A// 412SN/A// Authors: Stephen Hines 429180Sandreas.hansson@arm.com 4310474Sandreas.hansson@arm.com//////////////////////////////////////////////////////////////////// 449500Snilay@cs.wisc.edu// 4511004SAndreas.Sandberg@ARM.com// Unknown instructions 469180Sandreas.hansson@arm.com// 4710276SAndreas.Sandberg@ARM.com 4810276SAndreas.Sandberg@ARM.comoutput header {{ 492SN/A /** 505543SN/A * Static instruction class for unknown (illegal) instructions. 512SN/A * These cause simulator termination if they are executed in a 525543SN/A * non-speculative mode. This is a leaf class. 532SN/A */ 542SN/A class Unknown : public ArmStaticInst 552SN/A { 562SN/A public: 572SN/A /// Constructor 582SN/A Unknown(ExtMachInst _machInst) 592SN/A : ArmStaticInst("unknown", _machInst, No_OpClass) 602SN/A { 619158Sandreas.hansson@arm.com // don't call execute() (which panics) if we're on a 622SN/A // speculative path 639158Sandreas.hansson@arm.com flags[IsNonSpeculative] = true; 642SN/A } 659158Sandreas.hansson@arm.com 662667SN/A %(BasicExecDeclare)s 672130SN/A 689180Sandreas.hansson@arm.com std::string 699180Sandreas.hansson@arm.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 709180Sandreas.hansson@arm.com }; 719180Sandreas.hansson@arm.com}}; 729180Sandreas.hansson@arm.com 739180Sandreas.hansson@arm.comoutput decoder {{ 749180Sandreas.hansson@arm.com std::string 759180Sandreas.hansson@arm.com Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const 7611990Sandreas.sandberg@arm.com { 779180Sandreas.hansson@arm.com return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)", 789180Sandreas.hansson@arm.com "unknown", machInst, OPCODE, inst2string(machInst)); 799180Sandreas.hansson@arm.com } 809180Sandreas.hansson@arm.com}}; 819180Sandreas.hansson@arm.com 829180Sandreas.hansson@arm.comoutput exec {{ 839180Sandreas.hansson@arm.com Fault 849180Sandreas.hansson@arm.com Unknown::execute(%(CPU_exec_context)s *xc, 859180Sandreas.hansson@arm.com Trace::InstRecord *traceData) const 869180Sandreas.hansson@arm.com { 879180Sandreas.hansson@arm.com#if FULL_SYSTEM 889180Sandreas.hansson@arm.com return new UndefinedInstruction; 899180Sandreas.hansson@arm.com#else 909180Sandreas.hansson@arm.com return new UndefinedInstruction(machInst, true); 919180Sandreas.hansson@arm.com#endif 929180Sandreas.hansson@arm.com } 939180Sandreas.hansson@arm.com}}; 9411004SAndreas.Sandberg@ARM.com 959180Sandreas.hansson@arm.comdef format Unknown() {{ 969184Sandreas.hansson@arm.com decode_block = 'return new Unknown(machInst);\n' 979184Sandreas.hansson@arm.com}}; 989184Sandreas.hansson@arm.com 999180Sandreas.hansson@arm.com