breakpoint.isa revision 12542
16019SN/A// -*- mode:c++ -*-
26019SN/A
312542Sgiacomo.travaglini@arm.com// Copyright (c) 2010,2018 ARM Limited
47189SN/A// All rights reserved
57189SN/A//
67189SN/A// The license below extends only to copyright in the software and shall
77189SN/A// not be construed as granting a license to any other intellectual
87189SN/A// property including but not limited to intellectual property relating
97189SN/A// to a hardware implementation of the functionality of the software
107189SN/A// licensed hereunder.  You may use the software subject to the license
117189SN/A// terms below provided that you ensure that this notice is replicated
127189SN/A// unmodified and in its entirety in all distributions of the software,
137189SN/A// modified or unmodified, in source code or in binary form.
147189SN/A//
156019SN/A// Copyright (c) 2007-2008 The Florida State University
166019SN/A// All rights reserved.
176019SN/A//
186019SN/A// Redistribution and use in source and binary forms, with or without
196019SN/A// modification, are permitted provided that the following conditions are
206019SN/A// met: redistributions of source code must retain the above copyright
216019SN/A// notice, this list of conditions and the following disclaimer;
226019SN/A// redistributions in binary form must reproduce the above copyright
236019SN/A// notice, this list of conditions and the following disclaimer in the
246019SN/A// documentation and/or other materials provided with the distribution;
256019SN/A// neither the name of the copyright holders nor the names of its
266019SN/A// contributors may be used to endorse or promote products derived from
276019SN/A// this software without specific prior written permission.
286019SN/A//
296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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406019SN/A//
416019SN/A// Authors: Stephen Hines
426019SN/A
436019SN/A////////////////////////////////////////////////////////////////////
446019SN/A//
457401SAli.Saidi@ARM.com// Breakpoint instructions
466019SN/A//
476019SN/A
486019SN/Aoutput header {{
496019SN/A    /**
507401SAli.Saidi@ARM.com     * Static instruction class for Breakpoint (illegal) instructions.
516019SN/A     * These cause simulator termination if they are executed in a
526019SN/A     * non-speculative mode.  This is a leaf class.
536019SN/A     */
547401SAli.Saidi@ARM.com    class Breakpoint : public ArmStaticInst
556019SN/A    {
566019SN/A      public:
576019SN/A        /// Constructor
587401SAli.Saidi@ARM.com        Breakpoint(ExtMachInst _machInst)
597401SAli.Saidi@ARM.com            : ArmStaticInst("Breakpoint", _machInst, No_OpClass)
606019SN/A        {
616019SN/A            // don't call execute() (which panics) if we're on a
626019SN/A            // speculative path
636019SN/A            flags[IsNonSpeculative] = true;
646019SN/A        }
656019SN/A
6612236Sgabeblack@google.com        Fault execute(ExecContext *, Trace::InstRecord *) const;
676019SN/A
686019SN/A        std::string
696019SN/A        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
706019SN/A    };
716019SN/A}};
726019SN/A
736019SN/Aoutput decoder {{
746019SN/A    std::string
757401SAli.Saidi@ARM.com    Breakpoint::generateDisassembly(Addr pc, const SymbolTable *symtab) const
766019SN/A    {
777426Sgblack@eecs.umich.edu        return csprintf("%-10s (inst 0x%x)", "Breakpoint", machInst);
786019SN/A    }
796019SN/A}};
806019SN/A
816019SN/Aoutput exec {{
826019SN/A    Fault
8312234Sgabeblack@google.com    Breakpoint::execute(ExecContext *xc, Trace::InstRecord *traceData) const
846019SN/A    {
8510474Sandreas.hansson@arm.com        return std::make_shared<PrefetchAbort>(xc->pcState().pc(),
8610474Sandreas.hansson@arm.com                                               ArmFault::DebugEvent);
876019SN/A    }
886019SN/A}};
896019SN/A
9012542Sgiacomo.travaglini@arm.comdef format ArmBkptHlt() {{
9112542Sgiacomo.travaglini@arm.com    decode_block = '''
9212542Sgiacomo.travaglini@arm.com    {
9312542Sgiacomo.travaglini@arm.com        if (bits(machInst, 21)) {
9412542Sgiacomo.travaglini@arm.com            return new Breakpoint(machInst);
9512542Sgiacomo.travaglini@arm.com        } else {
9612542Sgiacomo.travaglini@arm.com            uint32_t imm16 = (bits(machInst, 19, 8) << 4) |
9712542Sgiacomo.travaglini@arm.com                             (bits(machInst,  3, 0) << 0);
9812542Sgiacomo.travaglini@arm.com            return new Hlt(machInst, imm16);
9912542Sgiacomo.travaglini@arm.com        }
10012542Sgiacomo.travaglini@arm.com    }
10112542Sgiacomo.travaglini@arm.com    '''
1026019SN/A}};
1036019SN/A
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