branch.isa revision 7152 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43////////////////////////////////////////////////////////////////////
44//
45// Control transfer instructions
46//
47
48def format ArmBBlxImm() {{
49    decode_block = '''
50        if (machInst.condCode == 0xF) {
51            int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
52                          (bits(machInst, 24) << 1);
53            return new BlxImm(machInst, imm);
54        } else {
55            return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
56                         (ConditionCode)(uint32_t)machInst.condCode);
57        }
58    '''
59}};
60
61def format ArmBlBlxImm() {{
62    decode_block = '''
63        if (machInst.condCode == 0xF) {
64            int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
65                          (bits(machInst, 24) << 1);
66            return new BlxImm(machInst, imm);
67        } else {
68            return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
69                          (ConditionCode)(uint32_t)machInst.condCode);
70        }
71    '''
72}};
73
74def format ArmBx() {{
75    decode_block = '''
76        return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
77                         (ConditionCode)(uint32_t)machInst.condCode);
78    '''
79}};
80
81def format ArmBlxReg() {{
82    decode_block = '''
83        return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
84                          (ConditionCode)(uint32_t)machInst.condCode);
85    '''
86}};
87
88def format Branch(code,*opt_flags) {{
89
90    #Build Instruction Flags
91    #Use Link & Likely Flags to Add Link/Condition Code
92    inst_flags = ('IsDirectControl', )
93    linking = False
94    for x in opt_flags:
95        if x == 'Link':
96            linking = True
97            code += 'LR = NPC;\n'
98        else:
99            inst_flags += (x, )
100
101    #Take into account uncond. branch instruction
102    if 'cond == 1' in code:
103         inst_flags += ('IsUnCondControl', )
104    else:
105         inst_flags += ('IsCondControl', )
106
107    icode =  'if (testPredicate(CondCodes, condCode)) {\n'
108    icode += code
109    icode += '  NPC = NPC + 4 + disp;\n'
110    icode += '} else {\n'
111    icode += '  NPC = NPC;\n'
112    if linking:
113        icode += '  LR = LR;\n'
114    icode += '};\n'
115
116    code = icode
117
118    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
119    header_output = BasicDeclare.subst(iop)
120    decoder_output = BasicConstructor.subst(iop)
121    decode_block = BasicDecode.subst(iop)
122    exec_output = BasicExecute.subst(iop)
123}};
124
125def format BranchExchange(code,*opt_flags) {{
126    #Build Instruction Flags
127    #Use Link & Likely Flags to Add Link/Condition Code
128    inst_flags = ('IsIndirectControl', )
129    linking = False
130    for x in opt_flags:
131        if x == 'Link':
132            linking = True
133            code += 'LR = NPC;\n'
134        else:
135            inst_flags += (x, )
136
137    #Take into account uncond. branch instruction
138    if 'cond == 1' in code:
139         inst_flags += ('IsUnCondControl', )
140    else:
141         inst_flags += ('IsCondControl', )
142
143    #Condition code
144
145    icode =  'if (testPredicate(CondCodes, condCode)) {\n'
146    icode += code
147    icode += '  NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
148    icode += '} else {\n'
149    icode += '  NPC = NPC;\n'
150    if linking:
151        icode += '  LR = LR;\n'
152    icode += '};\n'
153
154    code = icode
155
156    iop = InstObjParams(name, Name, 'BranchExchange', code, inst_flags)
157    header_output = BasicDeclare.subst(iop)
158    decoder_output = BasicConstructor.subst(iop)
159    decode_block = BasicDecode.subst(iop)
160    exec_output = BasicExecute.subst(iop)
161}};
162
163