aarch64.isa revision 14157
114127Sgiacomo.travaglini@arm.com// Copyright (c) 2011-2019 ARM Limited 210037SARM gem5 Developers// All rights reserved 310037SARM gem5 Developers// 410037SARM gem5 Developers// The license below extends only to copyright in the software and shall 510037SARM gem5 Developers// not be construed as granting a license to any other intellectual 610037SARM gem5 Developers// property including but not limited to intellectual property relating 710037SARM gem5 Developers// to a hardware implementation of the functionality of the software 810037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers// 1310037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1410037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1510037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1610037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1710037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1910037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2010037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2110037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2210037SARM gem5 Developers// this software without specific prior written permission. 2310037SARM gem5 Developers// 2410037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510037SARM gem5 Developers// 3610037SARM gem5 Developers// Authors: Gabe Black 3710037SARM gem5 Developers// Thomas Grocutt 3810037SARM gem5 Developers// Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developersoutput header {{ 4210037SARM gem5 Developersnamespace Aarch64 4310037SARM gem5 Developers{ 4410037SARM gem5 Developers StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 4510037SARM gem5 Developers StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 4610037SARM gem5 Developers StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 4710037SARM gem5 Developers StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 4810037SARM gem5 Developers 4911165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5010037SARM gem5 Developers StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 5110037SARM gem5 Developers StaticInstPtr decodeFp(ExtMachInst machInst); 5211165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5310037SARM gem5 Developers StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 5410037SARM gem5 Developers StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 5510037SARM gem5 Developers 5613759Sgiacomo.gabrielli@arm.com StaticInstPtr decodeSveInt(ExtMachInst machInst); 5713759Sgiacomo.gabrielli@arm.com StaticInstPtr decodeSveFp(ExtMachInst machInst); 5813759Sgiacomo.gabrielli@arm.com StaticInstPtr decodeSveMem(ExtMachInst machInst); 5913759Sgiacomo.gabrielli@arm.com 6010037SARM gem5 Developers StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 6110037SARM gem5 Developers} 6210037SARM gem5 Developers}}; 6310037SARM gem5 Developers 6410037SARM gem5 Developersoutput decoder {{ 6510037SARM gem5 Developersnamespace Aarch64 6610037SARM gem5 Developers{ 6710037SARM gem5 Developers StaticInstPtr 6810037SARM gem5 Developers decodeDataProcImm(ExtMachInst machInst) 6910037SARM gem5 Developers { 7010037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 7110037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 7210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 7310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 7410037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 7510037SARM gem5 Developers 7610037SARM gem5 Developers uint8_t opc = bits(machInst, 30, 29); 7710037SARM gem5 Developers bool sf = bits(machInst, 31); 7810037SARM gem5 Developers bool n = bits(machInst, 22); 7910037SARM gem5 Developers uint8_t immr = bits(machInst, 21, 16); 8010037SARM gem5 Developers uint8_t imms = bits(machInst, 15, 10); 8110037SARM gem5 Developers switch (bits(machInst, 25, 23)) { 8210037SARM gem5 Developers case 0x0: 8310037SARM gem5 Developers case 0x1: 8410037SARM gem5 Developers { 8510037SARM gem5 Developers uint64_t immlo = bits(machInst, 30, 29); 8610037SARM gem5 Developers uint64_t immhi = bits(machInst, 23, 5); 8710037SARM gem5 Developers uint64_t imm = (immlo << 0) | (immhi << 2); 8810037SARM gem5 Developers if (bits(machInst, 31) == 0) 8910337SAndrew.Bardsley@arm.com return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 9010037SARM gem5 Developers else 9110337SAndrew.Bardsley@arm.com return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 9210037SARM gem5 Developers sext<33>(imm << 12)); 9310037SARM gem5 Developers } 9410037SARM gem5 Developers case 0x2: 9510037SARM gem5 Developers case 0x3: 9610037SARM gem5 Developers { 9710037SARM gem5 Developers uint32_t imm12 = bits(machInst, 21, 10); 9810037SARM gem5 Developers uint8_t shift = bits(machInst, 23, 22); 9910037SARM gem5 Developers uint32_t imm; 10010037SARM gem5 Developers if (shift == 0x0) 10110037SARM gem5 Developers imm = imm12 << 0; 10210037SARM gem5 Developers else if (shift == 0x1) 10310037SARM gem5 Developers imm = imm12 << 12; 10410037SARM gem5 Developers else 10510037SARM gem5 Developers return new Unknown64(machInst); 10610037SARM gem5 Developers switch (opc) { 10710037SARM gem5 Developers case 0x0: 10810037SARM gem5 Developers return new AddXImm(machInst, rdsp, rnsp, imm); 10910037SARM gem5 Developers case 0x1: 11010337SAndrew.Bardsley@arm.com return new AddXImmCc(machInst, rdzr, rnsp, imm); 11110037SARM gem5 Developers case 0x2: 11210037SARM gem5 Developers return new SubXImm(machInst, rdsp, rnsp, imm); 11310037SARM gem5 Developers case 0x3: 11410337SAndrew.Bardsley@arm.com return new SubXImmCc(machInst, rdzr, rnsp, imm); 11512595Ssiddhesh.poyarekar@gmail.com default: 11612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 11710037SARM gem5 Developers } 11810037SARM gem5 Developers } 11910037SARM gem5 Developers case 0x4: 12010037SARM gem5 Developers { 12110037SARM gem5 Developers if (!sf && n) 12210037SARM gem5 Developers return new Unknown64(machInst); 12310037SARM gem5 Developers // len = MSB(n:NOT(imms)), len < 1 is undefined. 12410037SARM gem5 Developers uint8_t len = 0; 12510037SARM gem5 Developers if (n) { 12610037SARM gem5 Developers len = 6; 12710037SARM gem5 Developers } else if (imms == 0x3f || imms == 0x3e) { 12810037SARM gem5 Developers return new Unknown64(machInst); 12910037SARM gem5 Developers } else { 13010037SARM gem5 Developers len = findMsbSet(imms ^ 0x3f); 13110037SARM gem5 Developers } 13210037SARM gem5 Developers // Generate r, s, and size. 13310037SARM gem5 Developers uint64_t r = bits(immr, len - 1, 0); 13410037SARM gem5 Developers uint64_t s = bits(imms, len - 1, 0); 13510037SARM gem5 Developers uint8_t size = 1 << len; 13610037SARM gem5 Developers if (s == size - 1) 13710037SARM gem5 Developers return new Unknown64(machInst); 13810037SARM gem5 Developers // Generate the pattern with s 1s, rotated by r, with size bits. 13910037SARM gem5 Developers uint64_t pattern = mask(s + 1); 14010037SARM gem5 Developers if (r) { 14110037SARM gem5 Developers pattern = (pattern >> r) | (pattern << (size - r)); 14210037SARM gem5 Developers pattern &= mask(size); 14310037SARM gem5 Developers } 14410037SARM gem5 Developers uint8_t width = sf ? 64 : 32; 14510037SARM gem5 Developers // Replicate that to fill up the immediate. 14610037SARM gem5 Developers for (unsigned i = 1; i < (width / size); i *= 2) 14710037SARM gem5 Developers pattern |= (pattern << (i * size)); 14810037SARM gem5 Developers uint64_t imm = pattern; 14910037SARM gem5 Developers 15010037SARM gem5 Developers switch (opc) { 15110037SARM gem5 Developers case 0x0: 15210037SARM gem5 Developers return new AndXImm(machInst, rdsp, rn, imm); 15310037SARM gem5 Developers case 0x1: 15410037SARM gem5 Developers return new OrrXImm(machInst, rdsp, rn, imm); 15510037SARM gem5 Developers case 0x2: 15610037SARM gem5 Developers return new EorXImm(machInst, rdsp, rn, imm); 15710037SARM gem5 Developers case 0x3: 15810337SAndrew.Bardsley@arm.com return new AndXImmCc(machInst, rdzr, rn, imm); 15912595Ssiddhesh.poyarekar@gmail.com default: 16012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 16110037SARM gem5 Developers } 16210037SARM gem5 Developers } 16310037SARM gem5 Developers case 0x5: 16410037SARM gem5 Developers { 16510037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 16610337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 16710037SARM gem5 Developers uint32_t imm16 = bits(machInst, 20, 5); 16810037SARM gem5 Developers uint32_t hw = bits(machInst, 22, 21); 16910037SARM gem5 Developers switch (opc) { 17010037SARM gem5 Developers case 0x0: 17110337SAndrew.Bardsley@arm.com return new Movn(machInst, rdzr, imm16, hw * 16); 17210037SARM gem5 Developers case 0x1: 17310037SARM gem5 Developers return new Unknown64(machInst); 17410037SARM gem5 Developers case 0x2: 17510337SAndrew.Bardsley@arm.com return new Movz(machInst, rdzr, imm16, hw * 16); 17610037SARM gem5 Developers case 0x3: 17710337SAndrew.Bardsley@arm.com return new Movk(machInst, rdzr, imm16, hw * 16); 17812595Ssiddhesh.poyarekar@gmail.com default: 17912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 18010037SARM gem5 Developers } 18110037SARM gem5 Developers } 18210037SARM gem5 Developers case 0x6: 18310037SARM gem5 Developers if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 18410037SARM gem5 Developers return new Unknown64(machInst); 18510037SARM gem5 Developers switch (opc) { 18610037SARM gem5 Developers case 0x0: 18710337SAndrew.Bardsley@arm.com return new Sbfm64(machInst, rdzr, rn, immr, imms); 18810037SARM gem5 Developers case 0x1: 18910337SAndrew.Bardsley@arm.com return new Bfm64(machInst, rdzr, rn, immr, imms); 19010037SARM gem5 Developers case 0x2: 19110337SAndrew.Bardsley@arm.com return new Ubfm64(machInst, rdzr, rn, immr, imms); 19210037SARM gem5 Developers case 0x3: 19310037SARM gem5 Developers return new Unknown64(machInst); 19412595Ssiddhesh.poyarekar@gmail.com default: 19512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 19610037SARM gem5 Developers } 19710037SARM gem5 Developers case 0x7: 19810037SARM gem5 Developers { 19910037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 20010037SARM gem5 Developers if (opc || bits(machInst, 21)) 20110037SARM gem5 Developers return new Unknown64(machInst); 20210037SARM gem5 Developers else 20310337SAndrew.Bardsley@arm.com return new Extr64(machInst, rdzr, rn, rm, imms); 20410037SARM gem5 Developers } 20510037SARM gem5 Developers } 20610037SARM gem5 Developers return new FailUnimplemented("Unhandled Case8", machInst); 20710037SARM gem5 Developers } 20810037SARM gem5 Developers} 20910037SARM gem5 Developers}}; 21010037SARM gem5 Developers 21110037SARM gem5 Developersoutput decoder {{ 21210037SARM gem5 Developersnamespace Aarch64 21310037SARM gem5 Developers{ 21410037SARM gem5 Developers StaticInstPtr 21510037SARM gem5 Developers decodeBranchExcSys(ExtMachInst machInst) 21610037SARM gem5 Developers { 21710037SARM gem5 Developers switch (bits(machInst, 30, 29)) { 21810037SARM gem5 Developers case 0x0: 21910037SARM gem5 Developers { 22010037SARM gem5 Developers int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 22110037SARM gem5 Developers if (bits(machInst, 31) == 0) 22210037SARM gem5 Developers return new B64(machInst, imm); 22310037SARM gem5 Developers else 22410037SARM gem5 Developers return new Bl64(machInst, imm); 22510037SARM gem5 Developers } 22610037SARM gem5 Developers case 0x1: 22710037SARM gem5 Developers { 22810037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 22910037SARM gem5 Developers if (bits(machInst, 25) == 0) { 23010037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 23110037SARM gem5 Developers if (bits(machInst, 24) == 0) 23210037SARM gem5 Developers return new Cbz64(machInst, imm, rt); 23310037SARM gem5 Developers else 23410037SARM gem5 Developers return new Cbnz64(machInst, imm, rt); 23510037SARM gem5 Developers } else { 23610037SARM gem5 Developers uint64_t bitmask = 0x1; 23710037SARM gem5 Developers bitmask <<= bits(machInst, 23, 19); 23810037SARM gem5 Developers int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 23910037SARM gem5 Developers if (bits(machInst, 31)) 24010037SARM gem5 Developers bitmask <<= 32; 24110037SARM gem5 Developers if (bits(machInst, 24) == 0) 24210037SARM gem5 Developers return new Tbz64(machInst, bitmask, imm, rt); 24310037SARM gem5 Developers else 24410037SARM gem5 Developers return new Tbnz64(machInst, bitmask, imm, rt); 24510037SARM gem5 Developers } 24610037SARM gem5 Developers } 24710037SARM gem5 Developers case 0x2: 24810037SARM gem5 Developers // bit 30:26=10101 24910037SARM gem5 Developers if (bits(machInst, 31) == 0) { 25010037SARM gem5 Developers if (bits(machInst, 25, 24) || bits(machInst, 4)) 25110037SARM gem5 Developers return new Unknown64(machInst); 25210037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 25310037SARM gem5 Developers ConditionCode condCode = 25410037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 25510037SARM gem5 Developers return new BCond64(machInst, imm, condCode); 25610037SARM gem5 Developers } else if (bits(machInst, 25, 24) == 0x0) { 25712538Sgiacomo.travaglini@arm.com 25810037SARM gem5 Developers if (bits(machInst, 4, 2)) 25910037SARM gem5 Developers return new Unknown64(machInst); 26012538Sgiacomo.travaglini@arm.com 26112538Sgiacomo.travaglini@arm.com auto imm16 = bits(machInst, 20, 5); 26210037SARM gem5 Developers uint8_t decVal = (bits(machInst, 1, 0) << 0) | 26310037SARM gem5 Developers (bits(machInst, 23, 21) << 2); 26412538Sgiacomo.travaglini@arm.com 26510037SARM gem5 Developers switch (decVal) { 26610037SARM gem5 Developers case 0x01: 26712538Sgiacomo.travaglini@arm.com return new Svc64(machInst, imm16); 26810037SARM gem5 Developers case 0x02: 26912538Sgiacomo.travaglini@arm.com return new Hvc64(machInst, imm16); 27010037SARM gem5 Developers case 0x03: 27112538Sgiacomo.travaglini@arm.com return new Smc64(machInst, imm16); 27210037SARM gem5 Developers case 0x04: 27312538Sgiacomo.travaglini@arm.com return new Brk64(machInst, imm16); 27410037SARM gem5 Developers case 0x08: 27512538Sgiacomo.travaglini@arm.com return new Hlt64(machInst, imm16); 27610037SARM gem5 Developers case 0x15: 27710037SARM gem5 Developers return new FailUnimplemented("dcps1", machInst); 27810037SARM gem5 Developers case 0x16: 27910037SARM gem5 Developers return new FailUnimplemented("dcps2", machInst); 28010037SARM gem5 Developers case 0x17: 28110037SARM gem5 Developers return new FailUnimplemented("dcps3", machInst); 28210037SARM gem5 Developers default: 28310037SARM gem5 Developers return new Unknown64(machInst); 28410037SARM gem5 Developers } 28510037SARM gem5 Developers } else if (bits(machInst, 25, 22) == 0x4) { 28610037SARM gem5 Developers // bit 31:22=1101010100 28710037SARM gem5 Developers bool l = bits(machInst, 21); 28810037SARM gem5 Developers uint8_t op0 = bits(machInst, 20, 19); 28910037SARM gem5 Developers uint8_t op1 = bits(machInst, 18, 16); 29010037SARM gem5 Developers uint8_t crn = bits(machInst, 15, 12); 29110037SARM gem5 Developers uint8_t crm = bits(machInst, 11, 8); 29210037SARM gem5 Developers uint8_t op2 = bits(machInst, 7, 5); 29310037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 29410037SARM gem5 Developers switch (op0) { 29510037SARM gem5 Developers case 0x0: 29610037SARM gem5 Developers if (rt != 0x1f || l) 29710037SARM gem5 Developers return new Unknown64(machInst); 29810037SARM gem5 Developers if (crn == 0x2 && op1 == 0x3) { 29913354Sciro.santilli@arm.com switch (crm) { 30010037SARM gem5 Developers case 0x0: 30113354Sciro.santilli@arm.com switch (op2) { 30213354Sciro.santilli@arm.com case 0x0: 30313354Sciro.santilli@arm.com return new NopInst(machInst); 30413354Sciro.santilli@arm.com case 0x1: 30513354Sciro.santilli@arm.com return new YieldInst(machInst); 30613354Sciro.santilli@arm.com case 0x2: 30713354Sciro.santilli@arm.com return new WfeInst(machInst); 30813354Sciro.santilli@arm.com case 0x3: 30913354Sciro.santilli@arm.com return new WfiInst(machInst); 31013354Sciro.santilli@arm.com case 0x4: 31113354Sciro.santilli@arm.com return new SevInst(machInst); 31213354Sciro.santilli@arm.com case 0x5: 31313354Sciro.santilli@arm.com return new SevlInst(machInst); 31413354Sciro.santilli@arm.com } 31513354Sciro.santilli@arm.com break; 31610037SARM gem5 Developers case 0x1: 31713354Sciro.santilli@arm.com switch (op2) { 31813354Sciro.santilli@arm.com case 0x0: 31913354Sciro.santilli@arm.com return new WarnUnimplemented( 32013354Sciro.santilli@arm.com "pacia", machInst); 32113354Sciro.santilli@arm.com case 0x2: 32213354Sciro.santilli@arm.com return new WarnUnimplemented( 32313354Sciro.santilli@arm.com "pacib", machInst); 32413354Sciro.santilli@arm.com case 0x4: 32513354Sciro.santilli@arm.com return new WarnUnimplemented( 32613354Sciro.santilli@arm.com "autia", machInst); 32713354Sciro.santilli@arm.com case 0x6: 32813354Sciro.santilli@arm.com return new WarnUnimplemented( 32913354Sciro.santilli@arm.com "autib", machInst); 33013354Sciro.santilli@arm.com } 33113354Sciro.santilli@arm.com break; 33210037SARM gem5 Developers case 0x2: 33313354Sciro.santilli@arm.com switch (op2) { 33413354Sciro.santilli@arm.com case 0x0: 33513354Sciro.santilli@arm.com return new WarnUnimplemented( 33613354Sciro.santilli@arm.com "esb", machInst); 33713354Sciro.santilli@arm.com case 0x1: 33813354Sciro.santilli@arm.com return new WarnUnimplemented( 33913354Sciro.santilli@arm.com "psb csync", machInst); 34013354Sciro.santilli@arm.com case 0x2: 34113354Sciro.santilli@arm.com return new WarnUnimplemented( 34213354Sciro.santilli@arm.com "tsb csync", machInst); 34313354Sciro.santilli@arm.com case 0x4: 34413354Sciro.santilli@arm.com return new WarnUnimplemented( 34513354Sciro.santilli@arm.com "csdb", machInst); 34613354Sciro.santilli@arm.com } 34713354Sciro.santilli@arm.com break; 34810037SARM gem5 Developers case 0x3: 34913354Sciro.santilli@arm.com switch (op2) { 35013354Sciro.santilli@arm.com case 0x0: 35113354Sciro.santilli@arm.com case 0x1: 35213354Sciro.santilli@arm.com return new WarnUnimplemented( 35313354Sciro.santilli@arm.com "pacia", machInst); 35413354Sciro.santilli@arm.com case 0x2: 35513354Sciro.santilli@arm.com case 0x3: 35613354Sciro.santilli@arm.com return new WarnUnimplemented( 35713354Sciro.santilli@arm.com "pacib", machInst); 35813354Sciro.santilli@arm.com case 0x4: 35913354Sciro.santilli@arm.com case 0x5: 36013354Sciro.santilli@arm.com return new WarnUnimplemented( 36113354Sciro.santilli@arm.com "autia", machInst); 36213354Sciro.santilli@arm.com case 0x6: 36313354Sciro.santilli@arm.com case 0x7: 36413354Sciro.santilli@arm.com return new WarnUnimplemented( 36513354Sciro.santilli@arm.com "autib", machInst); 36613354Sciro.santilli@arm.com } 36713354Sciro.santilli@arm.com break; 36810037SARM gem5 Developers case 0x4: 36913354Sciro.santilli@arm.com switch (op2 & 0x1) { 37013354Sciro.santilli@arm.com case 0x0: 37113354Sciro.santilli@arm.com return new WarnUnimplemented( 37213354Sciro.santilli@arm.com "bti", machInst); 37313354Sciro.santilli@arm.com } 37413354Sciro.santilli@arm.com break; 37510037SARM gem5 Developers } 37613355Sciro.santilli@arm.com return new WarnUnimplemented( 37713355Sciro.santilli@arm.com "unallocated_hint", machInst); 37810037SARM gem5 Developers } else if (crn == 0x3 && op1 == 0x3) { 37910037SARM gem5 Developers switch (op2) { 38010037SARM gem5 Developers case 0x2: 38110037SARM gem5 Developers return new Clrex64(machInst); 38210037SARM gem5 Developers case 0x4: 38310037SARM gem5 Developers return new Dsb64(machInst); 38410037SARM gem5 Developers case 0x5: 38510037SARM gem5 Developers return new Dmb64(machInst); 38610037SARM gem5 Developers case 0x6: 38710037SARM gem5 Developers return new Isb64(machInst); 38810037SARM gem5 Developers default: 38910037SARM gem5 Developers return new Unknown64(machInst); 39010037SARM gem5 Developers } 39110037SARM gem5 Developers } else if (crn == 0x4) { 39214127Sgiacomo.travaglini@arm.com // MSR immediate: moving immediate value to selected 39314127Sgiacomo.travaglini@arm.com // bits of the PSTATE 39410037SARM gem5 Developers switch (op1 << 3 | op2) { 39514128Sgiacomo.travaglini@arm.com case 0x4: 39614128Sgiacomo.travaglini@arm.com // PAN 39714128Sgiacomo.travaglini@arm.com return new MsrImm64( 39814128Sgiacomo.travaglini@arm.com machInst, MISCREG_PAN, crm); 39910037SARM gem5 Developers case 0x5: 40010037SARM gem5 Developers // SP 40114127Sgiacomo.travaglini@arm.com return new MsrImm64( 40214127Sgiacomo.travaglini@arm.com machInst, MISCREG_SPSEL, crm); 40310037SARM gem5 Developers case 0x1e: 40410037SARM gem5 Developers // DAIFSet 40514127Sgiacomo.travaglini@arm.com return new MsrImmDAIFSet64( 40614127Sgiacomo.travaglini@arm.com machInst, MISCREG_DAIF, crm); 40710037SARM gem5 Developers case 0x1f: 40810037SARM gem5 Developers // DAIFClr 40914127Sgiacomo.travaglini@arm.com return new MsrImmDAIFClr64( 41014127Sgiacomo.travaglini@arm.com machInst, MISCREG_DAIF, crm); 41110037SARM gem5 Developers default: 41210037SARM gem5 Developers return new Unknown64(machInst); 41310037SARM gem5 Developers } 41410037SARM gem5 Developers } else { 41510037SARM gem5 Developers return new Unknown64(machInst); 41610037SARM gem5 Developers } 41710037SARM gem5 Developers break; 41810037SARM gem5 Developers case 0x1: 41910037SARM gem5 Developers case 0x2: 42010037SARM gem5 Developers case 0x3: 42110037SARM gem5 Developers { 42210037SARM gem5 Developers // bit 31:22=1101010100, 20:19=11 42310037SARM gem5 Developers bool read = l; 42410037SARM gem5 Developers MiscRegIndex miscReg = 42510037SARM gem5 Developers decodeAArch64SysReg(op0, op1, crn, crm, op2); 42610037SARM gem5 Developers if (read) { 42710037SARM gem5 Developers if ((miscReg == MISCREG_DC_CIVAC_Xt) || 42810037SARM gem5 Developers (miscReg == MISCREG_DC_CVAC_Xt) || 42912359Snikos.nikoleris@arm.com (miscReg == MISCREG_DC_IVAC_Xt) || 43010037SARM gem5 Developers (miscReg == MISCREG_DC_ZVA_Xt)) { 43110037SARM gem5 Developers return new Unknown64(machInst); 43210037SARM gem5 Developers } 43310037SARM gem5 Developers } 43410037SARM gem5 Developers // Check for invalid registers 43510037SARM gem5 Developers if (miscReg == MISCREG_UNKNOWN) { 43612673Sgiacomo.travaglini@arm.com auto full_mnemonic = 43712673Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 43812673Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 43912673Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 44012673Sgiacomo.travaglini@arm.com 44112673Sgiacomo.travaglini@arm.com return new FailUnimplemented(read ? "mrs" : "msr", 44212673Sgiacomo.travaglini@arm.com machInst, full_mnemonic); 44312673Sgiacomo.travaglini@arm.com 44412714Sgiacomo.travaglini@arm.com } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { 44512714Sgiacomo.travaglini@arm.com auto full_mnemonic = 44612714Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 44712714Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 44812714Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 44912714Sgiacomo.travaglini@arm.com 45013365Sgiacomo.travaglini@arm.com uint32_t iss = msrMrs64IssBuild( 45113365Sgiacomo.travaglini@arm.com read, op0, op1, crn, crm, op2, rt); 45213365Sgiacomo.travaglini@arm.com 45313365Sgiacomo.travaglini@arm.com return new MiscRegImplDefined64( 45413365Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 45513365Sgiacomo.travaglini@arm.com machInst, miscReg, read, iss, full_mnemonic, 45613365Sgiacomo.travaglini@arm.com miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]); 45712714Sgiacomo.travaglini@arm.com 45810037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 45910037SARM gem5 Developers if (miscReg == MISCREG_NZCV) { 46010037SARM gem5 Developers if (read) 46110037SARM gem5 Developers return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 46210037SARM gem5 Developers else 46310037SARM gem5 Developers return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 46410037SARM gem5 Developers } 46510037SARM gem5 Developers uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 46610506SAli.Saidi@ARM.com if (read) { 46712280Sgiacomo.travaglini@arm.com StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); 46810506SAli.Saidi@ARM.com if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 46910506SAli.Saidi@ARM.com si->setFlag(StaticInst::IsUnverifiable); 47010506SAli.Saidi@ARM.com return si; 47112280Sgiacomo.travaglini@arm.com } else { 47212359Snikos.nikoleris@arm.com switch (miscReg) { 47312359Snikos.nikoleris@arm.com case MISCREG_DC_ZVA_Xt: 47412359Snikos.nikoleris@arm.com return new Dczva(machInst, rt, miscReg, iss); 47512359Snikos.nikoleris@arm.com case MISCREG_DC_CVAU_Xt: 47612359Snikos.nikoleris@arm.com return new Dccvau(machInst, rt, miscReg, iss); 47712359Snikos.nikoleris@arm.com case MISCREG_DC_CVAC_Xt: 47812359Snikos.nikoleris@arm.com return new Dccvac(machInst, rt, miscReg, iss); 47912359Snikos.nikoleris@arm.com case MISCREG_DC_CIVAC_Xt: 48012359Snikos.nikoleris@arm.com return new Dccivac(machInst, rt, miscReg, iss); 48112359Snikos.nikoleris@arm.com case MISCREG_DC_IVAC_Xt: 48212359Snikos.nikoleris@arm.com return new Dcivac(machInst, rt, miscReg, iss); 48312359Snikos.nikoleris@arm.com default: 48412359Snikos.nikoleris@arm.com return new Msr64(machInst, miscReg, rt, iss); 48512359Snikos.nikoleris@arm.com } 48612280Sgiacomo.travaglini@arm.com } 48710037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 48810037SARM gem5 Developers std::string full_mnem = csprintf("%s %s", 48910037SARM gem5 Developers read ? "mrs" : "msr", miscRegName[miscReg]); 49010037SARM gem5 Developers return new WarnUnimplemented(read ? "mrs" : "msr", 49110037SARM gem5 Developers machInst, full_mnem); 49210037SARM gem5 Developers } else { 49310173SMitchell.Hayenga@ARM.com return new FailUnimplemented(read ? "mrs" : "msr", 49410173SMitchell.Hayenga@ARM.com machInst, 49510173SMitchell.Hayenga@ARM.com csprintf("%s %s", 49610173SMitchell.Hayenga@ARM.com read ? "mrs" : "msr", 49710173SMitchell.Hayenga@ARM.com miscRegName[miscReg])); 49810037SARM gem5 Developers } 49910037SARM gem5 Developers } 50010037SARM gem5 Developers break; 50112595Ssiddhesh.poyarekar@gmail.com default: 50212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 50310037SARM gem5 Developers } 50410037SARM gem5 Developers } else if (bits(machInst, 25) == 0x1) { 50510037SARM gem5 Developers uint8_t opc = bits(machInst, 24, 21); 50610037SARM gem5 Developers uint8_t op2 = bits(machInst, 20, 16); 50710037SARM gem5 Developers uint8_t op3 = bits(machInst, 15, 10); 50810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 50910037SARM gem5 Developers uint8_t op4 = bits(machInst, 4, 0); 51010037SARM gem5 Developers if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 51110037SARM gem5 Developers return new Unknown64(machInst); 51210037SARM gem5 Developers switch (opc) { 51310037SARM gem5 Developers case 0x0: 51410037SARM gem5 Developers return new Br64(machInst, rn); 51510037SARM gem5 Developers case 0x1: 51610037SARM gem5 Developers return new Blr64(machInst, rn); 51710037SARM gem5 Developers case 0x2: 51810037SARM gem5 Developers return new Ret64(machInst, rn); 51910037SARM gem5 Developers case 0x4: 52010037SARM gem5 Developers if (rn != 0x1f) 52110037SARM gem5 Developers return new Unknown64(machInst); 52210037SARM gem5 Developers return new Eret64(machInst); 52310037SARM gem5 Developers case 0x5: 52410037SARM gem5 Developers if (rn != 0x1f) 52510037SARM gem5 Developers return new Unknown64(machInst); 52610037SARM gem5 Developers return new FailUnimplemented("dret", machInst); 52712595Ssiddhesh.poyarekar@gmail.com default: 52812595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 52910037SARM gem5 Developers } 53010037SARM gem5 Developers } 53112595Ssiddhesh.poyarekar@gmail.com M5_FALLTHROUGH; 53210037SARM gem5 Developers default: 53310037SARM gem5 Developers return new Unknown64(machInst); 53410037SARM gem5 Developers } 53510037SARM gem5 Developers return new FailUnimplemented("Unhandled Case7", machInst); 53610037SARM gem5 Developers } 53710037SARM gem5 Developers} 53810037SARM gem5 Developers}}; 53910037SARM gem5 Developers 54010037SARM gem5 Developersoutput decoder {{ 54110037SARM gem5 Developersnamespace Aarch64 54210037SARM gem5 Developers{ 54310037SARM gem5 Developers StaticInstPtr 54414157Sjordi.vaquero@metempsy.com decodeAtomicArithOp(ExtMachInst machInst) 54514157Sjordi.vaquero@metempsy.com { 54614157Sjordi.vaquero@metempsy.com uint8_t opc = bits(machInst, 14, 12); 54714157Sjordi.vaquero@metempsy.com uint8_t o3 = bits(machInst, 15); 54814157Sjordi.vaquero@metempsy.com uint8_t size_ar = bits(machInst, 23, 22)<<0 | bits(machInst, 31, 30)<<2; 54914157Sjordi.vaquero@metempsy.com IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 55014157Sjordi.vaquero@metempsy.com IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 55114157Sjordi.vaquero@metempsy.com IntRegIndex rnsp = makeSP(rn); 55214157Sjordi.vaquero@metempsy.com IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 55314157Sjordi.vaquero@metempsy.com uint8_t A_rt = bits(machInst, 4, 0)<<0 | bits(machInst, 23)<<5; 55414157Sjordi.vaquero@metempsy.com 55514157Sjordi.vaquero@metempsy.com switch(opc) { 55614157Sjordi.vaquero@metempsy.com case 0x0: 55714157Sjordi.vaquero@metempsy.com switch(size_ar){ 55814157Sjordi.vaquero@metempsy.com case 0x0: 55914157Sjordi.vaquero@metempsy.com if (o3 == 1) 56014157Sjordi.vaquero@metempsy.com return new SWPB(machInst, rt, rnsp, rs); 56114157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 56214157Sjordi.vaquero@metempsy.com return new STADDB(machInst, rt, rnsp, rs); 56314157Sjordi.vaquero@metempsy.com else 56414157Sjordi.vaquero@metempsy.com return new LDADDB(machInst, rt, rnsp, rs); 56514157Sjordi.vaquero@metempsy.com case 0x1 : 56614157Sjordi.vaquero@metempsy.com if (o3 == 1) 56714157Sjordi.vaquero@metempsy.com return new SWPLB(machInst, rt, rnsp, rs); 56814157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 56914157Sjordi.vaquero@metempsy.com return new STADDLB(machInst, rt, rnsp, rs); 57014157Sjordi.vaquero@metempsy.com else 57114157Sjordi.vaquero@metempsy.com return new LDADDLB(machInst, rt, rnsp, rs); 57214157Sjordi.vaquero@metempsy.com case 0x2: 57314157Sjordi.vaquero@metempsy.com if (o3 == 1) 57414157Sjordi.vaquero@metempsy.com return new SWPAB(machInst, rt, rnsp, rs); 57514157Sjordi.vaquero@metempsy.com else 57614157Sjordi.vaquero@metempsy.com return new LDADDAB(machInst, rt, rnsp, rs); 57714157Sjordi.vaquero@metempsy.com case 0x3: 57814157Sjordi.vaquero@metempsy.com if (o3 == 1) 57914157Sjordi.vaquero@metempsy.com return new SWPLAB(machInst, rt, rnsp, rs); 58014157Sjordi.vaquero@metempsy.com else 58114157Sjordi.vaquero@metempsy.com return new LDADDLAB(machInst, rt, rnsp, rs); 58214157Sjordi.vaquero@metempsy.com case 0x4: 58314157Sjordi.vaquero@metempsy.com if (o3 == 1) 58414157Sjordi.vaquero@metempsy.com return new SWPH(machInst, rt, rnsp, rs); 58514157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 58614157Sjordi.vaquero@metempsy.com return new STADDH(machInst, rt, rnsp, rs); 58714157Sjordi.vaquero@metempsy.com else 58814157Sjordi.vaquero@metempsy.com return new LDADDH(machInst, rt, rnsp, rs); 58914157Sjordi.vaquero@metempsy.com case 0x5 : 59014157Sjordi.vaquero@metempsy.com if (o3 == 1) 59114157Sjordi.vaquero@metempsy.com return new SWPLH(machInst, rt, rnsp, rs); 59214157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 59314157Sjordi.vaquero@metempsy.com return new STADDLH(machInst, rt, rnsp, rs); 59414157Sjordi.vaquero@metempsy.com else 59514157Sjordi.vaquero@metempsy.com return new LDADDLH(machInst, rt, rnsp, rs); 59614157Sjordi.vaquero@metempsy.com case 0x6: 59714157Sjordi.vaquero@metempsy.com if (o3 == 1) 59814157Sjordi.vaquero@metempsy.com return new SWPAH(machInst, rt, rnsp, rs); 59914157Sjordi.vaquero@metempsy.com else 60014157Sjordi.vaquero@metempsy.com return new LDADDAH(machInst, rt, rnsp, rs); 60114157Sjordi.vaquero@metempsy.com case 0x7: 60214157Sjordi.vaquero@metempsy.com if (o3 == 1) 60314157Sjordi.vaquero@metempsy.com return new SWPLAH(machInst, rt, rnsp, rs); 60414157Sjordi.vaquero@metempsy.com else 60514157Sjordi.vaquero@metempsy.com return new LDADDLAH(machInst, rt, rnsp, rs); 60614157Sjordi.vaquero@metempsy.com case 0x8: 60714157Sjordi.vaquero@metempsy.com if (o3 == 1) 60814157Sjordi.vaquero@metempsy.com return new SWP(machInst, rt, rnsp, rs); 60914157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 61014157Sjordi.vaquero@metempsy.com return new STADD(machInst, rt, rnsp, rs); 61114157Sjordi.vaquero@metempsy.com else 61214157Sjordi.vaquero@metempsy.com return new LDADD(machInst, rt, rnsp, rs); 61314157Sjordi.vaquero@metempsy.com case 0x9 : 61414157Sjordi.vaquero@metempsy.com if (o3 == 1) 61514157Sjordi.vaquero@metempsy.com return new SWPL(machInst, rt, rnsp, rs); 61614157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 61714157Sjordi.vaquero@metempsy.com return new STADDL(machInst, rt, rnsp, rs); 61814157Sjordi.vaquero@metempsy.com else 61914157Sjordi.vaquero@metempsy.com return new LDADDL(machInst, rt, rnsp, rs); 62014157Sjordi.vaquero@metempsy.com case 0xa: 62114157Sjordi.vaquero@metempsy.com if (o3 == 1) 62214157Sjordi.vaquero@metempsy.com return new SWPA(machInst, rt, rnsp, rs); 62314157Sjordi.vaquero@metempsy.com else 62414157Sjordi.vaquero@metempsy.com return new LDADDA(machInst, rt, rnsp, rs); 62514157Sjordi.vaquero@metempsy.com case 0xb: 62614157Sjordi.vaquero@metempsy.com if (o3 == 1) 62714157Sjordi.vaquero@metempsy.com return new SWPLA(machInst, rt, rnsp, rs); 62814157Sjordi.vaquero@metempsy.com else 62914157Sjordi.vaquero@metempsy.com return new LDADDLA(machInst, rt, rnsp, rs); 63014157Sjordi.vaquero@metempsy.com case 0xc: 63114157Sjordi.vaquero@metempsy.com if (o3 == 1) 63214157Sjordi.vaquero@metempsy.com return new SWP64(machInst, rt, rnsp, rs); 63314157Sjordi.vaquero@metempsy.com 63414157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 63514157Sjordi.vaquero@metempsy.com return new STADD64(machInst, rt, rnsp, rs); 63614157Sjordi.vaquero@metempsy.com else 63714157Sjordi.vaquero@metempsy.com return new LDADD64(machInst, rt, rnsp, rs); 63814157Sjordi.vaquero@metempsy.com case 0xd : 63914157Sjordi.vaquero@metempsy.com if (o3 == 1) 64014157Sjordi.vaquero@metempsy.com return new SWPL64(machInst, rt, rnsp, rs); 64114157Sjordi.vaquero@metempsy.com else if (A_rt == 0x1f) 64214157Sjordi.vaquero@metempsy.com return new STADDL64(machInst, rt, rnsp, rs); 64314157Sjordi.vaquero@metempsy.com else 64414157Sjordi.vaquero@metempsy.com return new LDADDL64(machInst, rt, rnsp, rs); 64514157Sjordi.vaquero@metempsy.com case 0xe: 64614157Sjordi.vaquero@metempsy.com if (o3 == 1) 64714157Sjordi.vaquero@metempsy.com return new SWPA64(machInst, rt, rnsp, rs); 64814157Sjordi.vaquero@metempsy.com else 64914157Sjordi.vaquero@metempsy.com return new LDADDA64(machInst, rt, rnsp, rs); 65014157Sjordi.vaquero@metempsy.com case 0xf: 65114157Sjordi.vaquero@metempsy.com if (o3 == 1) 65214157Sjordi.vaquero@metempsy.com return new SWPLA64(machInst, rt, rnsp, rs); 65314157Sjordi.vaquero@metempsy.com else 65414157Sjordi.vaquero@metempsy.com return new LDADDLA64(machInst, rt, rnsp, rs); 65514157Sjordi.vaquero@metempsy.com } 65614157Sjordi.vaquero@metempsy.com case 0x1: 65714157Sjordi.vaquero@metempsy.com switch(size_ar){ 65814157Sjordi.vaquero@metempsy.com case 0x0: 65914157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 66014157Sjordi.vaquero@metempsy.com return new STCLRB(machInst, rt, rnsp, rs); 66114157Sjordi.vaquero@metempsy.com else 66214157Sjordi.vaquero@metempsy.com return new LDCLRB(machInst, rt, rnsp, rs); 66314157Sjordi.vaquero@metempsy.com case 0x1 : 66414157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 66514157Sjordi.vaquero@metempsy.com return new STCLRLB(machInst, rt, rnsp, rs); 66614157Sjordi.vaquero@metempsy.com else 66714157Sjordi.vaquero@metempsy.com return new LDCLRLB(machInst, rt, rnsp, rs); 66814157Sjordi.vaquero@metempsy.com case 0x2: 66914157Sjordi.vaquero@metempsy.com return new LDCLRAB(machInst, rt, rnsp, rs); 67014157Sjordi.vaquero@metempsy.com case 0x3: 67114157Sjordi.vaquero@metempsy.com return new LDCLRLAB(machInst, rt, rnsp, rs); 67214157Sjordi.vaquero@metempsy.com case 0x4: 67314157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 67414157Sjordi.vaquero@metempsy.com return new STCLRH(machInst, rt, rnsp, rs); 67514157Sjordi.vaquero@metempsy.com else 67614157Sjordi.vaquero@metempsy.com return new LDCLRH(machInst, rt, rnsp, rs); 67714157Sjordi.vaquero@metempsy.com case 0x5 : 67814157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 67914157Sjordi.vaquero@metempsy.com return new STCLRLH(machInst, rt, rnsp, rs); 68014157Sjordi.vaquero@metempsy.com else 68114157Sjordi.vaquero@metempsy.com return new LDCLRLH(machInst, rt, rnsp, rs); 68214157Sjordi.vaquero@metempsy.com case 0x6: 68314157Sjordi.vaquero@metempsy.com return new LDCLRAH(machInst, rt, rnsp, rs); 68414157Sjordi.vaquero@metempsy.com case 0x7: 68514157Sjordi.vaquero@metempsy.com return new LDCLRLAH(machInst, rt, rnsp, rs); 68614157Sjordi.vaquero@metempsy.com case 0x8: 68714157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 68814157Sjordi.vaquero@metempsy.com return new STCLR(machInst, rt, rnsp, rs); 68914157Sjordi.vaquero@metempsy.com else 69014157Sjordi.vaquero@metempsy.com return new LDCLR(machInst, rt, rnsp, rs); 69114157Sjordi.vaquero@metempsy.com case 0x9 : 69214157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 69314157Sjordi.vaquero@metempsy.com return new STCLRL(machInst, rt, rnsp, rs); 69414157Sjordi.vaquero@metempsy.com else 69514157Sjordi.vaquero@metempsy.com return new LDCLRL(machInst, rt, rnsp, rs); 69614157Sjordi.vaquero@metempsy.com case 0xa: 69714157Sjordi.vaquero@metempsy.com return new LDCLRA(machInst, rt, rnsp, rs); 69814157Sjordi.vaquero@metempsy.com case 0xb: 69914157Sjordi.vaquero@metempsy.com return new LDCLRLA(machInst, rt, rnsp, rs); 70014157Sjordi.vaquero@metempsy.com case 0xc: 70114157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 70214157Sjordi.vaquero@metempsy.com return new STCLR64(machInst, rt, rnsp, rs); 70314157Sjordi.vaquero@metempsy.com else 70414157Sjordi.vaquero@metempsy.com return new LDCLR64(machInst, rt, rnsp, rs); 70514157Sjordi.vaquero@metempsy.com case 0xd : 70614157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 70714157Sjordi.vaquero@metempsy.com return new STCLRL64(machInst, rt, rnsp, rs); 70814157Sjordi.vaquero@metempsy.com else 70914157Sjordi.vaquero@metempsy.com return new LDCLRL64(machInst, rt, rnsp, rs); 71014157Sjordi.vaquero@metempsy.com case 0xe: 71114157Sjordi.vaquero@metempsy.com return new LDCLRA64(machInst, rt, rnsp, rs); 71214157Sjordi.vaquero@metempsy.com case 0xf: 71314157Sjordi.vaquero@metempsy.com return new LDCLRLA64(machInst, rt, rnsp, rs); 71414157Sjordi.vaquero@metempsy.com } 71514157Sjordi.vaquero@metempsy.com case 0x2: 71614157Sjordi.vaquero@metempsy.com switch(size_ar){ 71714157Sjordi.vaquero@metempsy.com case 0x0: 71814157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 71914157Sjordi.vaquero@metempsy.com return new STEORB(machInst, rt, rnsp, rs); 72014157Sjordi.vaquero@metempsy.com else 72114157Sjordi.vaquero@metempsy.com return new LDEORB(machInst, rt, rnsp, rs); 72214157Sjordi.vaquero@metempsy.com case 0x1 : 72314157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 72414157Sjordi.vaquero@metempsy.com return new STEORLB(machInst, rt, rnsp, rs); 72514157Sjordi.vaquero@metempsy.com else 72614157Sjordi.vaquero@metempsy.com return new LDEORLB(machInst, rt, rnsp, rs); 72714157Sjordi.vaquero@metempsy.com case 0x2: 72814157Sjordi.vaquero@metempsy.com return new LDEORAB(machInst, rt, rnsp, rs); 72914157Sjordi.vaquero@metempsy.com case 0x3: 73014157Sjordi.vaquero@metempsy.com return new LDEORLAB(machInst, rt, rnsp, rs); 73114157Sjordi.vaquero@metempsy.com case 0x4: 73214157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 73314157Sjordi.vaquero@metempsy.com return new STEORH(machInst, rt, rnsp, rs); 73414157Sjordi.vaquero@metempsy.com else 73514157Sjordi.vaquero@metempsy.com return new LDEORH(machInst, rt, rnsp, rs); 73614157Sjordi.vaquero@metempsy.com case 0x5 : 73714157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 73814157Sjordi.vaquero@metempsy.com return new STEORLH(machInst, rt, rnsp, rs); 73914157Sjordi.vaquero@metempsy.com else 74014157Sjordi.vaquero@metempsy.com return new LDEORLH(machInst, rt, rnsp, rs); 74114157Sjordi.vaquero@metempsy.com case 0x6: 74214157Sjordi.vaquero@metempsy.com return new LDEORAH(machInst, rt, rnsp, rs); 74314157Sjordi.vaquero@metempsy.com case 0x7: 74414157Sjordi.vaquero@metempsy.com return new LDEORLAH(machInst, rt, rnsp, rs); 74514157Sjordi.vaquero@metempsy.com case 0x8: 74614157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 74714157Sjordi.vaquero@metempsy.com return new STEOR(machInst, rt, rnsp, rs); 74814157Sjordi.vaquero@metempsy.com else 74914157Sjordi.vaquero@metempsy.com return new LDEOR(machInst, rt, rnsp, rs); 75014157Sjordi.vaquero@metempsy.com case 0x9 : 75114157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 75214157Sjordi.vaquero@metempsy.com return new STEORL(machInst, rt, rnsp, rs); 75314157Sjordi.vaquero@metempsy.com else 75414157Sjordi.vaquero@metempsy.com return new LDEORL(machInst, rt, rnsp, rs); 75514157Sjordi.vaquero@metempsy.com case 0xa: 75614157Sjordi.vaquero@metempsy.com return new LDEORA(machInst, rt, rnsp, rs); 75714157Sjordi.vaquero@metempsy.com case 0xb: 75814157Sjordi.vaquero@metempsy.com return new LDEORLA(machInst, rt, rnsp, rs); 75914157Sjordi.vaquero@metempsy.com case 0xc: 76014157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 76114157Sjordi.vaquero@metempsy.com return new STEOR64(machInst, rt, rnsp, rs); 76214157Sjordi.vaquero@metempsy.com else 76314157Sjordi.vaquero@metempsy.com return new LDEOR64(machInst, rt, rnsp, rs); 76414157Sjordi.vaquero@metempsy.com case 0xd : 76514157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 76614157Sjordi.vaquero@metempsy.com return new STEORL64(machInst, rt, rnsp, rs); 76714157Sjordi.vaquero@metempsy.com else 76814157Sjordi.vaquero@metempsy.com return new LDEORL64(machInst, rt, rnsp, rs); 76914157Sjordi.vaquero@metempsy.com case 0xe: 77014157Sjordi.vaquero@metempsy.com return new LDEORA64(machInst, rt, rnsp, rs); 77114157Sjordi.vaquero@metempsy.com case 0xf: 77214157Sjordi.vaquero@metempsy.com return new LDEORLA64(machInst, rt, rnsp, rs); 77314157Sjordi.vaquero@metempsy.com } 77414157Sjordi.vaquero@metempsy.com case 0x3: 77514157Sjordi.vaquero@metempsy.com switch(size_ar){ 77614157Sjordi.vaquero@metempsy.com case 0x0: 77714157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 77814157Sjordi.vaquero@metempsy.com return new STSETB(machInst, rt, rnsp, rs); 77914157Sjordi.vaquero@metempsy.com else 78014157Sjordi.vaquero@metempsy.com return new LDSETB(machInst, rt, rnsp, rs); 78114157Sjordi.vaquero@metempsy.com case 0x1 : 78214157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 78314157Sjordi.vaquero@metempsy.com return new STSETLB(machInst, rt, rnsp, rs); 78414157Sjordi.vaquero@metempsy.com else 78514157Sjordi.vaquero@metempsy.com return new LDSETLB(machInst, rt, rnsp, rs); 78614157Sjordi.vaquero@metempsy.com case 0x2: 78714157Sjordi.vaquero@metempsy.com return new LDSETAB(machInst, rt, rnsp, rs); 78814157Sjordi.vaquero@metempsy.com case 0x3: 78914157Sjordi.vaquero@metempsy.com return new LDSETLAB(machInst, rt, rnsp, rs); 79014157Sjordi.vaquero@metempsy.com case 0x4: 79114157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 79214157Sjordi.vaquero@metempsy.com return new STSETH(machInst, rt, rnsp, rs); 79314157Sjordi.vaquero@metempsy.com else 79414157Sjordi.vaquero@metempsy.com return new LDSETH(machInst, rt, rnsp, rs); 79514157Sjordi.vaquero@metempsy.com case 0x5 : 79614157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 79714157Sjordi.vaquero@metempsy.com return new STSETLH(machInst, rt, rnsp, rs); 79814157Sjordi.vaquero@metempsy.com else 79914157Sjordi.vaquero@metempsy.com return new LDSETLH(machInst, rt, rnsp, rs); 80014157Sjordi.vaquero@metempsy.com case 0x6: 80114157Sjordi.vaquero@metempsy.com return new LDSETAH(machInst, rt, rnsp, rs); 80214157Sjordi.vaquero@metempsy.com case 0x7: 80314157Sjordi.vaquero@metempsy.com return new LDSETLAH(machInst, rt, rnsp, rs); 80414157Sjordi.vaquero@metempsy.com case 0x8: 80514157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 80614157Sjordi.vaquero@metempsy.com return new STSET(machInst, rt, rnsp, rs); 80714157Sjordi.vaquero@metempsy.com else 80814157Sjordi.vaquero@metempsy.com return new LDSET(machInst, rt, rnsp, rs); 80914157Sjordi.vaquero@metempsy.com case 0x9 : 81014157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 81114157Sjordi.vaquero@metempsy.com return new STSETL(machInst, rt, rnsp, rs); 81214157Sjordi.vaquero@metempsy.com else 81314157Sjordi.vaquero@metempsy.com return new LDSETL(machInst, rt, rnsp, rs); 81414157Sjordi.vaquero@metempsy.com case 0xa: 81514157Sjordi.vaquero@metempsy.com return new LDSETA(machInst, rt, rnsp, rs); 81614157Sjordi.vaquero@metempsy.com case 0xb: 81714157Sjordi.vaquero@metempsy.com return new LDSETLA(machInst, rt, rnsp, rs); 81814157Sjordi.vaquero@metempsy.com case 0xc: 81914157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 82014157Sjordi.vaquero@metempsy.com return new STSET64(machInst, rt, rnsp, rs); 82114157Sjordi.vaquero@metempsy.com else 82214157Sjordi.vaquero@metempsy.com return new LDSET64(machInst, rt, rnsp, rs); 82314157Sjordi.vaquero@metempsy.com case 0xd : 82414157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 82514157Sjordi.vaquero@metempsy.com return new STSETL64(machInst, rt, rnsp, rs); 82614157Sjordi.vaquero@metempsy.com else 82714157Sjordi.vaquero@metempsy.com return new LDSETL64(machInst, rt, rnsp, rs); 82814157Sjordi.vaquero@metempsy.com case 0xe: 82914157Sjordi.vaquero@metempsy.com return new LDSETA64(machInst, rt, rnsp, rs); 83014157Sjordi.vaquero@metempsy.com case 0xf: 83114157Sjordi.vaquero@metempsy.com return new LDSETLA64(machInst, rt, rnsp, rs); 83214157Sjordi.vaquero@metempsy.com } 83314157Sjordi.vaquero@metempsy.com case 0x4: 83414157Sjordi.vaquero@metempsy.com switch(size_ar){ 83514157Sjordi.vaquero@metempsy.com case 0x0: 83614157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 83714157Sjordi.vaquero@metempsy.com return new STSMAXB(machInst, rt, rnsp, rs); 83814157Sjordi.vaquero@metempsy.com else 83914157Sjordi.vaquero@metempsy.com return new LDSMAXB(machInst, rt, rnsp, rs); 84014157Sjordi.vaquero@metempsy.com case 0x1 : 84114157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 84214157Sjordi.vaquero@metempsy.com return new STSMAXLB(machInst, rt, rnsp, rs); 84314157Sjordi.vaquero@metempsy.com else 84414157Sjordi.vaquero@metempsy.com return new LDSMAXLB(machInst, rt, rnsp, rs); 84514157Sjordi.vaquero@metempsy.com case 0x2: 84614157Sjordi.vaquero@metempsy.com return new LDSMAXAB(machInst, rt, rnsp, rs); 84714157Sjordi.vaquero@metempsy.com case 0x3: 84814157Sjordi.vaquero@metempsy.com return new LDSMAXLAB(machInst, rt, rnsp, rs); 84914157Sjordi.vaquero@metempsy.com case 0x4: 85014157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 85114157Sjordi.vaquero@metempsy.com return new STSMAXH(machInst, rt, rnsp, rs); 85214157Sjordi.vaquero@metempsy.com else 85314157Sjordi.vaquero@metempsy.com return new LDSMAXH(machInst, rt, rnsp, rs); 85414157Sjordi.vaquero@metempsy.com case 0x5 : 85514157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 85614157Sjordi.vaquero@metempsy.com return new STSMAXLH(machInst, rt, rnsp, rs); 85714157Sjordi.vaquero@metempsy.com else 85814157Sjordi.vaquero@metempsy.com return new LDSMAXLH(machInst, rt, rnsp, rs); 85914157Sjordi.vaquero@metempsy.com case 0x6: 86014157Sjordi.vaquero@metempsy.com return new LDSMAXAH(machInst, rt, rnsp, rs); 86114157Sjordi.vaquero@metempsy.com case 0x7: 86214157Sjordi.vaquero@metempsy.com return new LDSMAXLAH(machInst, rt, rnsp, rs); 86314157Sjordi.vaquero@metempsy.com case 0x8: 86414157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 86514157Sjordi.vaquero@metempsy.com return new STSMAX(machInst, rt, rnsp, rs); 86614157Sjordi.vaquero@metempsy.com else 86714157Sjordi.vaquero@metempsy.com return new LDSMAX(machInst, rt, rnsp, rs); 86814157Sjordi.vaquero@metempsy.com case 0x9 : 86914157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 87014157Sjordi.vaquero@metempsy.com return new STSMAXL(machInst, rt, rnsp, rs); 87114157Sjordi.vaquero@metempsy.com else 87214157Sjordi.vaquero@metempsy.com return new LDSMAXL(machInst, rt, rnsp, rs); 87314157Sjordi.vaquero@metempsy.com case 0xa: 87414157Sjordi.vaquero@metempsy.com return new LDSMAXA(machInst, rt, rnsp, rs); 87514157Sjordi.vaquero@metempsy.com case 0xb: 87614157Sjordi.vaquero@metempsy.com return new LDSMAXLA(machInst, rt, rnsp, rs); 87714157Sjordi.vaquero@metempsy.com case 0xc: 87814157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 87914157Sjordi.vaquero@metempsy.com return new STSMAX64(machInst, rt, rnsp, rs); 88014157Sjordi.vaquero@metempsy.com else 88114157Sjordi.vaquero@metempsy.com return new LDSMAX64(machInst, rt, rnsp, rs); 88214157Sjordi.vaquero@metempsy.com case 0xd : 88314157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 88414157Sjordi.vaquero@metempsy.com return new STSMAXL64(machInst, rt, rnsp, rs); 88514157Sjordi.vaquero@metempsy.com else 88614157Sjordi.vaquero@metempsy.com return new LDSMAXL64(machInst, rt, rnsp, rs); 88714157Sjordi.vaquero@metempsy.com case 0xe: 88814157Sjordi.vaquero@metempsy.com return new LDSMAXA64(machInst, rt, rnsp, rs); 88914157Sjordi.vaquero@metempsy.com case 0xf: 89014157Sjordi.vaquero@metempsy.com return new LDSMAXLA64(machInst, rt, rnsp, rs); 89114157Sjordi.vaquero@metempsy.com } 89214157Sjordi.vaquero@metempsy.com case 0x5: 89314157Sjordi.vaquero@metempsy.com switch(size_ar){ 89414157Sjordi.vaquero@metempsy.com case 0x0: 89514157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 89614157Sjordi.vaquero@metempsy.com return new STSMINB(machInst, rt, rnsp, rs); 89714157Sjordi.vaquero@metempsy.com else 89814157Sjordi.vaquero@metempsy.com return new LDSMINB(machInst, rt, rnsp, rs); 89914157Sjordi.vaquero@metempsy.com case 0x1 : 90014157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 90114157Sjordi.vaquero@metempsy.com return new STSMINLB(machInst, rt, rnsp, rs); 90214157Sjordi.vaquero@metempsy.com else 90314157Sjordi.vaquero@metempsy.com return new LDSMINLB(machInst, rt, rnsp, rs); 90414157Sjordi.vaquero@metempsy.com case 0x2: 90514157Sjordi.vaquero@metempsy.com return new LDSMINAB(machInst, rt, rnsp, rs); 90614157Sjordi.vaquero@metempsy.com case 0x3: 90714157Sjordi.vaquero@metempsy.com return new LDSMINLAB(machInst, rt, rnsp, rs); 90814157Sjordi.vaquero@metempsy.com case 0x4: 90914157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 91014157Sjordi.vaquero@metempsy.com return new STSMINH(machInst, rt, rnsp, rs); 91114157Sjordi.vaquero@metempsy.com else 91214157Sjordi.vaquero@metempsy.com return new LDSMINH(machInst, rt, rnsp, rs); 91314157Sjordi.vaquero@metempsy.com case 0x5 : 91414157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 91514157Sjordi.vaquero@metempsy.com return new STSMINLH(machInst, rt, rnsp, rs); 91614157Sjordi.vaquero@metempsy.com else 91714157Sjordi.vaquero@metempsy.com return new LDSMINLH(machInst, rt, rnsp, rs); 91814157Sjordi.vaquero@metempsy.com case 0x6: 91914157Sjordi.vaquero@metempsy.com return new LDSMINAH(machInst, rt, rnsp, rs); 92014157Sjordi.vaquero@metempsy.com case 0x7: 92114157Sjordi.vaquero@metempsy.com return new LDSMINLAH(machInst, rt, rnsp, rs); 92214157Sjordi.vaquero@metempsy.com case 0x8: 92314157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 92414157Sjordi.vaquero@metempsy.com return new STSMIN(machInst, rt, rnsp, rs); 92514157Sjordi.vaquero@metempsy.com else 92614157Sjordi.vaquero@metempsy.com return new LDSMIN(machInst, rt, rnsp, rs); 92714157Sjordi.vaquero@metempsy.com case 0x9 : 92814157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 92914157Sjordi.vaquero@metempsy.com return new STSMINL(machInst, rt, rnsp, rs); 93014157Sjordi.vaquero@metempsy.com else 93114157Sjordi.vaquero@metempsy.com return new LDSMINL(machInst, rt, rnsp, rs); 93214157Sjordi.vaquero@metempsy.com case 0xa: 93314157Sjordi.vaquero@metempsy.com return new LDSMINA(machInst, rt, rnsp, rs); 93414157Sjordi.vaquero@metempsy.com case 0xb: 93514157Sjordi.vaquero@metempsy.com return new LDSMINLA(machInst, rt, rnsp, rs); 93614157Sjordi.vaquero@metempsy.com case 0xc: 93714157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 93814157Sjordi.vaquero@metempsy.com return new STSMIN64(machInst, rt, rnsp, rs); 93914157Sjordi.vaquero@metempsy.com else 94014157Sjordi.vaquero@metempsy.com return new LDSMIN64(machInst, rt, rnsp, rs); 94114157Sjordi.vaquero@metempsy.com case 0xd : 94214157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 94314157Sjordi.vaquero@metempsy.com return new STSMINL64(machInst, rt, rnsp, rs); 94414157Sjordi.vaquero@metempsy.com else 94514157Sjordi.vaquero@metempsy.com return new LDSMINL64(machInst, rt, rnsp, rs); 94614157Sjordi.vaquero@metempsy.com case 0xe: 94714157Sjordi.vaquero@metempsy.com return new LDSMINA64(machInst, rt, rnsp, rs); 94814157Sjordi.vaquero@metempsy.com case 0xf: 94914157Sjordi.vaquero@metempsy.com return new LDSMINLA64(machInst, rt, rnsp, rs); 95014157Sjordi.vaquero@metempsy.com } 95114157Sjordi.vaquero@metempsy.com case 0x6: 95214157Sjordi.vaquero@metempsy.com switch(size_ar){ 95314157Sjordi.vaquero@metempsy.com case 0x0: 95414157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 95514157Sjordi.vaquero@metempsy.com return new STUMAXB(machInst, rt, rnsp, rs); 95614157Sjordi.vaquero@metempsy.com else 95714157Sjordi.vaquero@metempsy.com return new LDUMAXB(machInst, rt, rnsp, rs); 95814157Sjordi.vaquero@metempsy.com case 0x1 : 95914157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 96014157Sjordi.vaquero@metempsy.com return new STUMAXLB(machInst, rt, rnsp, rs); 96114157Sjordi.vaquero@metempsy.com else 96214157Sjordi.vaquero@metempsy.com return new LDUMAXLB(machInst, rt, rnsp, rs); 96314157Sjordi.vaquero@metempsy.com case 0x2: 96414157Sjordi.vaquero@metempsy.com return new LDUMAXAB(machInst, rt, rnsp, rs); 96514157Sjordi.vaquero@metempsy.com case 0x3: 96614157Sjordi.vaquero@metempsy.com return new LDUMAXLAB(machInst, rt, rnsp, rs); 96714157Sjordi.vaquero@metempsy.com case 0x4: 96814157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 96914157Sjordi.vaquero@metempsy.com return new STUMAXH(machInst, rt, rnsp, rs); 97014157Sjordi.vaquero@metempsy.com else 97114157Sjordi.vaquero@metempsy.com return new LDUMAXH(machInst, rt, rnsp, rs); 97214157Sjordi.vaquero@metempsy.com case 0x5 : 97314157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 97414157Sjordi.vaquero@metempsy.com return new STUMAXLH(machInst, rt, rnsp, rs); 97514157Sjordi.vaquero@metempsy.com else 97614157Sjordi.vaquero@metempsy.com return new LDUMAXLH(machInst, rt, rnsp, rs); 97714157Sjordi.vaquero@metempsy.com case 0x6: 97814157Sjordi.vaquero@metempsy.com return new LDUMAXAH(machInst, rt, rnsp, rs); 97914157Sjordi.vaquero@metempsy.com case 0x7: 98014157Sjordi.vaquero@metempsy.com return new LDUMAXLAH(machInst, rt, rnsp, rs); 98114157Sjordi.vaquero@metempsy.com case 0x8: 98214157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 98314157Sjordi.vaquero@metempsy.com return new STUMAX(machInst, rt, rnsp, rs); 98414157Sjordi.vaquero@metempsy.com else 98514157Sjordi.vaquero@metempsy.com return new LDUMAX(machInst, rt, rnsp, rs); 98614157Sjordi.vaquero@metempsy.com case 0x9 : 98714157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 98814157Sjordi.vaquero@metempsy.com return new STUMAXL(machInst, rt, rnsp, rs); 98914157Sjordi.vaquero@metempsy.com else 99014157Sjordi.vaquero@metempsy.com return new LDUMAXL(machInst, rt, rnsp, rs); 99114157Sjordi.vaquero@metempsy.com case 0xa: 99214157Sjordi.vaquero@metempsy.com return new LDUMAXA(machInst, rt, rnsp, rs); 99314157Sjordi.vaquero@metempsy.com case 0xb: 99414157Sjordi.vaquero@metempsy.com return new LDUMAXLA(machInst, rt, rnsp, rs); 99514157Sjordi.vaquero@metempsy.com case 0xc: 99614157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 99714157Sjordi.vaquero@metempsy.com return new STUMAX64(machInst, rt, rnsp, rs); 99814157Sjordi.vaquero@metempsy.com else 99914157Sjordi.vaquero@metempsy.com return new LDUMAX64(machInst, rt, rnsp, rs); 100014157Sjordi.vaquero@metempsy.com case 0xd : 100114157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 100214157Sjordi.vaquero@metempsy.com return new STUMAXL64(machInst, rt, rnsp, rs); 100314157Sjordi.vaquero@metempsy.com else 100414157Sjordi.vaquero@metempsy.com return new LDUMAXL64(machInst, rt, rnsp, rs); 100514157Sjordi.vaquero@metempsy.com case 0xe: 100614157Sjordi.vaquero@metempsy.com return new LDUMAXA64(machInst, rt, rnsp, rs); 100714157Sjordi.vaquero@metempsy.com case 0xf: 100814157Sjordi.vaquero@metempsy.com return new LDUMAXLA64(machInst, rt, rnsp, rs); 100914157Sjordi.vaquero@metempsy.com } 101014157Sjordi.vaquero@metempsy.com case 0x7: 101114157Sjordi.vaquero@metempsy.com switch(size_ar){ 101214157Sjordi.vaquero@metempsy.com case 0x0: 101314157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 101414157Sjordi.vaquero@metempsy.com return new STUMINB(machInst, rt, rnsp, rs); 101514157Sjordi.vaquero@metempsy.com else 101614157Sjordi.vaquero@metempsy.com return new LDUMINB(machInst, rt, rnsp, rs); 101714157Sjordi.vaquero@metempsy.com case 0x1 : 101814157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 101914157Sjordi.vaquero@metempsy.com return new STUMINLB(machInst, rt, rnsp, rs); 102014157Sjordi.vaquero@metempsy.com else 102114157Sjordi.vaquero@metempsy.com return new LDUMINLB(machInst, rt, rnsp, rs); 102214157Sjordi.vaquero@metempsy.com case 0x2: 102314157Sjordi.vaquero@metempsy.com return new LDUMINAB(machInst, rt, rnsp, rs); 102414157Sjordi.vaquero@metempsy.com case 0x3: 102514157Sjordi.vaquero@metempsy.com return new LDUMINLAB(machInst, rt, rnsp, rs); 102614157Sjordi.vaquero@metempsy.com case 0x4: 102714157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 102814157Sjordi.vaquero@metempsy.com return new STUMINH(machInst, rt, rnsp, rs); 102914157Sjordi.vaquero@metempsy.com else 103014157Sjordi.vaquero@metempsy.com return new LDUMINH(machInst, rt, rnsp, rs); 103114157Sjordi.vaquero@metempsy.com case 0x5 : 103214157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 103314157Sjordi.vaquero@metempsy.com return new STUMINLH(machInst, rt, rnsp, rs); 103414157Sjordi.vaquero@metempsy.com else 103514157Sjordi.vaquero@metempsy.com return new LDUMINLH(machInst, rt, rnsp, rs); 103614157Sjordi.vaquero@metempsy.com case 0x6: 103714157Sjordi.vaquero@metempsy.com return new LDUMINAH(machInst, rt, rnsp, rs); 103814157Sjordi.vaquero@metempsy.com case 0x7: 103914157Sjordi.vaquero@metempsy.com return new LDUMINLAH(machInst, rt, rnsp, rs); 104014157Sjordi.vaquero@metempsy.com case 0x8: 104114157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 104214157Sjordi.vaquero@metempsy.com return new STUMIN(machInst, rt, rnsp, rs); 104314157Sjordi.vaquero@metempsy.com else 104414157Sjordi.vaquero@metempsy.com return new LDUMIN(machInst, rt, rnsp, rs); 104514157Sjordi.vaquero@metempsy.com case 0x9 : 104614157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 104714157Sjordi.vaquero@metempsy.com return new STUMINL(machInst, rt, rnsp, rs); 104814157Sjordi.vaquero@metempsy.com else 104914157Sjordi.vaquero@metempsy.com return new LDUMINL(machInst, rt, rnsp, rs); 105014157Sjordi.vaquero@metempsy.com case 0xa: 105114157Sjordi.vaquero@metempsy.com return new LDUMINA(machInst, rt, rnsp, rs); 105214157Sjordi.vaquero@metempsy.com case 0xb: 105314157Sjordi.vaquero@metempsy.com return new LDUMINLA(machInst, rt, rnsp, rs); 105414157Sjordi.vaquero@metempsy.com case 0xc: 105514157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 105614157Sjordi.vaquero@metempsy.com return new STUMIN64(machInst, rt, rnsp, rs); 105714157Sjordi.vaquero@metempsy.com else 105814157Sjordi.vaquero@metempsy.com return new LDUMIN64(machInst, rt, rnsp, rs); 105914157Sjordi.vaquero@metempsy.com case 0xd : 106014157Sjordi.vaquero@metempsy.com if (A_rt == 0x1f) 106114157Sjordi.vaquero@metempsy.com return new STUMINL64(machInst, rt, rnsp, rs); 106214157Sjordi.vaquero@metempsy.com else 106314157Sjordi.vaquero@metempsy.com return new LDUMINL64(machInst, rt, rnsp, rs); 106414157Sjordi.vaquero@metempsy.com case 0xe: 106514157Sjordi.vaquero@metempsy.com return new LDUMINA64(machInst, rt, rnsp, rs); 106614157Sjordi.vaquero@metempsy.com case 0xf: 106714157Sjordi.vaquero@metempsy.com return new LDUMINLA64(machInst, rt, rnsp, rs); 106814157Sjordi.vaquero@metempsy.com } 106914157Sjordi.vaquero@metempsy.com default: 107014157Sjordi.vaquero@metempsy.com return new Unknown64(machInst); 107114157Sjordi.vaquero@metempsy.com } 107214157Sjordi.vaquero@metempsy.com } 107314157Sjordi.vaquero@metempsy.com} 107414157Sjordi.vaquero@metempsy.com}}; 107514157Sjordi.vaquero@metempsy.com 107614157Sjordi.vaquero@metempsy.com 107714157Sjordi.vaquero@metempsy.comoutput decoder {{ 107814157Sjordi.vaquero@metempsy.comnamespace Aarch64 107914157Sjordi.vaquero@metempsy.com{ 108014157Sjordi.vaquero@metempsy.com 108114157Sjordi.vaquero@metempsy.com StaticInstPtr 108210037SARM gem5 Developers decodeLoadsStores(ExtMachInst machInst) 108310037SARM gem5 Developers { 108410037SARM gem5 Developers // bit 27,25=10 108510037SARM gem5 Developers switch (bits(machInst, 29, 28)) { 108610037SARM gem5 Developers case 0x0: 108710037SARM gem5 Developers if (bits(machInst, 26) == 0) { 108810037SARM gem5 Developers if (bits(machInst, 24) != 0) 108910037SARM gem5 Developers return new Unknown64(machInst); 109010037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 109110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 109210037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 109310037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 109410037SARM gem5 Developers IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 109510037SARM gem5 Developers uint8_t opc = (bits(machInst, 15) << 0) | 109610037SARM gem5 Developers (bits(machInst, 23, 21) << 1); 109710037SARM gem5 Developers uint8_t size = bits(machInst, 31, 30); 109810037SARM gem5 Developers switch (opc) { 109910037SARM gem5 Developers case 0x0: 110010037SARM gem5 Developers switch (size) { 110110037SARM gem5 Developers case 0x0: 110210037SARM gem5 Developers return new STXRB64(machInst, rt, rnsp, rs); 110310037SARM gem5 Developers case 0x1: 110410037SARM gem5 Developers return new STXRH64(machInst, rt, rnsp, rs); 110510037SARM gem5 Developers case 0x2: 110610037SARM gem5 Developers return new STXRW64(machInst, rt, rnsp, rs); 110710037SARM gem5 Developers case 0x3: 110810037SARM gem5 Developers return new STXRX64(machInst, rt, rnsp, rs); 110912595Ssiddhesh.poyarekar@gmail.com default: 111012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 111110037SARM gem5 Developers } 111210037SARM gem5 Developers case 0x1: 111310037SARM gem5 Developers switch (size) { 111410037SARM gem5 Developers case 0x0: 111510037SARM gem5 Developers return new STLXRB64(machInst, rt, rnsp, rs); 111610037SARM gem5 Developers case 0x1: 111710037SARM gem5 Developers return new STLXRH64(machInst, rt, rnsp, rs); 111810037SARM gem5 Developers case 0x2: 111910037SARM gem5 Developers return new STLXRW64(machInst, rt, rnsp, rs); 112010037SARM gem5 Developers case 0x3: 112110037SARM gem5 Developers return new STLXRX64(machInst, rt, rnsp, rs); 112212595Ssiddhesh.poyarekar@gmail.com default: 112312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 112410037SARM gem5 Developers } 112510037SARM gem5 Developers case 0x2: 112610037SARM gem5 Developers switch (size) { 112710037SARM gem5 Developers case 0x0: 112814150Sjordi.vaquero@metempsy.com return new CASP32(machInst, rt, rnsp, rs); 112910037SARM gem5 Developers case 0x1: 113014150Sjordi.vaquero@metempsy.com return new CASP64(machInst, rt, rnsp, rs); 113110037SARM gem5 Developers case 0x2: 113210037SARM gem5 Developers return new STXPW64(machInst, rs, rt, rt2, rnsp); 113310037SARM gem5 Developers case 0x3: 113410037SARM gem5 Developers return new STXPX64(machInst, rs, rt, rt2, rnsp); 113512595Ssiddhesh.poyarekar@gmail.com default: 113612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 113710037SARM gem5 Developers } 113810037SARM gem5 Developers 113910037SARM gem5 Developers case 0x3: 114010037SARM gem5 Developers switch (size) { 114110037SARM gem5 Developers case 0x0: 114214150Sjordi.vaquero@metempsy.com return new CASPL32(machInst, rt, rnsp, rs); 114310037SARM gem5 Developers case 0x1: 114414150Sjordi.vaquero@metempsy.com return new CASPL64(machInst, rt, rnsp, rs); 114510037SARM gem5 Developers case 0x2: 114610037SARM gem5 Developers return new STLXPW64(machInst, rs, rt, rt2, rnsp); 114710037SARM gem5 Developers case 0x3: 114810037SARM gem5 Developers return new STLXPX64(machInst, rs, rt, rt2, rnsp); 114912595Ssiddhesh.poyarekar@gmail.com default: 115012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 115110037SARM gem5 Developers } 115210037SARM gem5 Developers 115310037SARM gem5 Developers case 0x4: 115410037SARM gem5 Developers switch (size) { 115510037SARM gem5 Developers case 0x0: 115610037SARM gem5 Developers return new LDXRB64(machInst, rt, rnsp, rs); 115710037SARM gem5 Developers case 0x1: 115810037SARM gem5 Developers return new LDXRH64(machInst, rt, rnsp, rs); 115910037SARM gem5 Developers case 0x2: 116010037SARM gem5 Developers return new LDXRW64(machInst, rt, rnsp, rs); 116110037SARM gem5 Developers case 0x3: 116210037SARM gem5 Developers return new LDXRX64(machInst, rt, rnsp, rs); 116312595Ssiddhesh.poyarekar@gmail.com default: 116412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 116510037SARM gem5 Developers } 116610037SARM gem5 Developers case 0x5: 116710037SARM gem5 Developers switch (size) { 116810037SARM gem5 Developers case 0x0: 116910037SARM gem5 Developers return new LDAXRB64(machInst, rt, rnsp, rs); 117010037SARM gem5 Developers case 0x1: 117110037SARM gem5 Developers return new LDAXRH64(machInst, rt, rnsp, rs); 117210037SARM gem5 Developers case 0x2: 117310037SARM gem5 Developers return new LDAXRW64(machInst, rt, rnsp, rs); 117410037SARM gem5 Developers case 0x3: 117510037SARM gem5 Developers return new LDAXRX64(machInst, rt, rnsp, rs); 117612595Ssiddhesh.poyarekar@gmail.com default: 117712595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 117810037SARM gem5 Developers } 117910037SARM gem5 Developers case 0x6: 118010037SARM gem5 Developers switch (size) { 118110037SARM gem5 Developers case 0x0: 118214150Sjordi.vaquero@metempsy.com return new CASPA32(machInst, rt, rnsp, rs); 118310037SARM gem5 Developers case 0x1: 118414150Sjordi.vaquero@metempsy.com return new CASPA64(machInst, rt, rnsp, rs); 118510037SARM gem5 Developers case 0x2: 118610037SARM gem5 Developers return new LDXPW64(machInst, rt, rt2, rnsp); 118710037SARM gem5 Developers case 0x3: 118810037SARM gem5 Developers return new LDXPX64(machInst, rt, rt2, rnsp); 118912595Ssiddhesh.poyarekar@gmail.com default: 119012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 119110037SARM gem5 Developers } 119210037SARM gem5 Developers case 0x7: 119310037SARM gem5 Developers switch (size) { 119410037SARM gem5 Developers case 0x0: 119514150Sjordi.vaquero@metempsy.com return new CASPAL32(machInst, rt, rnsp, rs); 119610037SARM gem5 Developers case 0x1: 119714150Sjordi.vaquero@metempsy.com return new CASPAL64(machInst, rt, rnsp, rs); 119810037SARM gem5 Developers case 0x2: 119910037SARM gem5 Developers return new LDAXPW64(machInst, rt, rt2, rnsp); 120010037SARM gem5 Developers case 0x3: 120110037SARM gem5 Developers return new LDAXPX64(machInst, rt, rt2, rnsp); 120212595Ssiddhesh.poyarekar@gmail.com default: 120312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 120410037SARM gem5 Developers } 120510037SARM gem5 Developers case 0x9: 120610037SARM gem5 Developers switch (size) { 120710037SARM gem5 Developers case 0x0: 120810037SARM gem5 Developers return new STLRB64(machInst, rt, rnsp); 120910037SARM gem5 Developers case 0x1: 121010037SARM gem5 Developers return new STLRH64(machInst, rt, rnsp); 121110037SARM gem5 Developers case 0x2: 121210037SARM gem5 Developers return new STLRW64(machInst, rt, rnsp); 121310037SARM gem5 Developers case 0x3: 121410037SARM gem5 Developers return new STLRX64(machInst, rt, rnsp); 121512595Ssiddhesh.poyarekar@gmail.com default: 121612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 121710037SARM gem5 Developers } 121814150Sjordi.vaquero@metempsy.com case 0xa: 121914150Sjordi.vaquero@metempsy.com switch (size) { 122014150Sjordi.vaquero@metempsy.com case 0x0: 122114150Sjordi.vaquero@metempsy.com return new CASB(machInst, rt, rnsp, rs); 122214150Sjordi.vaquero@metempsy.com case 0x1: 122314150Sjordi.vaquero@metempsy.com return new CASH(machInst, rt, rnsp, rs); 122414150Sjordi.vaquero@metempsy.com case 0x2: 122514150Sjordi.vaquero@metempsy.com return new CAS32(machInst, rt, rnsp, rs); 122614150Sjordi.vaquero@metempsy.com case 0x3: 122714150Sjordi.vaquero@metempsy.com return new CAS64(machInst, rt, rnsp, rs); 122814150Sjordi.vaquero@metempsy.com default: 122914150Sjordi.vaquero@metempsy.com M5_UNREACHABLE; 123014150Sjordi.vaquero@metempsy.com } 123114150Sjordi.vaquero@metempsy.com case 0xb: 123214150Sjordi.vaquero@metempsy.com switch (size) { 123314150Sjordi.vaquero@metempsy.com case 0x0: 123414150Sjordi.vaquero@metempsy.com return new CASLB(machInst, rt, rnsp, rs); 123514150Sjordi.vaquero@metempsy.com case 0x1: 123614150Sjordi.vaquero@metempsy.com return new CASLH(machInst, rt, rnsp, rs); 123714150Sjordi.vaquero@metempsy.com case 0x2: 123814150Sjordi.vaquero@metempsy.com return new CASL32(machInst, rt, rnsp, rs); 123914150Sjordi.vaquero@metempsy.com case 0x3: 124014150Sjordi.vaquero@metempsy.com return new CASL64(machInst, rt, rnsp, rs); 124114150Sjordi.vaquero@metempsy.com default: 124214150Sjordi.vaquero@metempsy.com M5_UNREACHABLE; 124314150Sjordi.vaquero@metempsy.com } 124410037SARM gem5 Developers case 0xd: 124510037SARM gem5 Developers switch (size) { 124610037SARM gem5 Developers case 0x0: 124710037SARM gem5 Developers return new LDARB64(machInst, rt, rnsp); 124810037SARM gem5 Developers case 0x1: 124910037SARM gem5 Developers return new LDARH64(machInst, rt, rnsp); 125010037SARM gem5 Developers case 0x2: 125110037SARM gem5 Developers return new LDARW64(machInst, rt, rnsp); 125210037SARM gem5 Developers case 0x3: 125310037SARM gem5 Developers return new LDARX64(machInst, rt, rnsp); 125412595Ssiddhesh.poyarekar@gmail.com default: 125512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 125610037SARM gem5 Developers } 125714150Sjordi.vaquero@metempsy.com case 0xe: 125814150Sjordi.vaquero@metempsy.com switch (size) { 125914150Sjordi.vaquero@metempsy.com case 0x0: 126014150Sjordi.vaquero@metempsy.com return new CASAB(machInst, rt, rnsp, rs); 126114150Sjordi.vaquero@metempsy.com case 0x1: 126214150Sjordi.vaquero@metempsy.com return new CASAH(machInst, rt, rnsp, rs); 126314150Sjordi.vaquero@metempsy.com case 0x2: 126414150Sjordi.vaquero@metempsy.com return new CASA32(machInst, rt, rnsp, rs); 126514150Sjordi.vaquero@metempsy.com case 0x3: 126614150Sjordi.vaquero@metempsy.com return new CASA64(machInst, rt, rnsp, rs); 126714150Sjordi.vaquero@metempsy.com default: 126814150Sjordi.vaquero@metempsy.com M5_UNREACHABLE; 126914150Sjordi.vaquero@metempsy.com } 127014150Sjordi.vaquero@metempsy.com case 0xf: 127114150Sjordi.vaquero@metempsy.com switch (size) { 127214150Sjordi.vaquero@metempsy.com case 0x0: 127314150Sjordi.vaquero@metempsy.com return new CASALB(machInst, rt, rnsp, rs); 127414150Sjordi.vaquero@metempsy.com case 0x1: 127514150Sjordi.vaquero@metempsy.com return new CASALH(machInst, rt, rnsp, rs); 127614150Sjordi.vaquero@metempsy.com case 0x2: 127714150Sjordi.vaquero@metempsy.com return new CASAL32(machInst, rt, rnsp, rs); 127814150Sjordi.vaquero@metempsy.com case 0x3: 127914150Sjordi.vaquero@metempsy.com return new CASAL64(machInst, rt, rnsp, rs); 128014150Sjordi.vaquero@metempsy.com default: 128114150Sjordi.vaquero@metempsy.com M5_UNREACHABLE; 128214150Sjordi.vaquero@metempsy.com } 128310037SARM gem5 Developers default: 128410037SARM gem5 Developers return new Unknown64(machInst); 128510037SARM gem5 Developers } 128610037SARM gem5 Developers } else if (bits(machInst, 31)) { 128710037SARM gem5 Developers return new Unknown64(machInst); 128810037SARM gem5 Developers } else { 128910037SARM gem5 Developers return decodeNeonMem(machInst); 129010037SARM gem5 Developers } 129110037SARM gem5 Developers case 0x1: 129210037SARM gem5 Developers { 129310037SARM gem5 Developers if (bits(machInst, 24) != 0) 129410037SARM gem5 Developers return new Unknown64(machInst); 129510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 26) << 0) | 129610037SARM gem5 Developers (bits(machInst, 31, 30) << 1); 129710037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 129810037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 129910037SARM gem5 Developers switch (switchVal) { 130010037SARM gem5 Developers case 0x0: 130110037SARM gem5 Developers return new LDRWL64_LIT(machInst, rt, imm); 130210037SARM gem5 Developers case 0x1: 130310037SARM gem5 Developers return new LDRSFP64_LIT(machInst, rt, imm); 130410037SARM gem5 Developers case 0x2: 130510037SARM gem5 Developers return new LDRXL64_LIT(machInst, rt, imm); 130610037SARM gem5 Developers case 0x3: 130710037SARM gem5 Developers return new LDRDFP64_LIT(machInst, rt, imm); 130810037SARM gem5 Developers case 0x4: 130910037SARM gem5 Developers return new LDRSWL64_LIT(machInst, rt, imm); 131010037SARM gem5 Developers case 0x5: 131110037SARM gem5 Developers return new BigFpMemLit("ldr", machInst, rt, imm); 131210037SARM gem5 Developers case 0x6: 131310037SARM gem5 Developers return new PRFM64_LIT(machInst, rt, imm); 131410037SARM gem5 Developers default: 131510037SARM gem5 Developers return new Unknown64(machInst); 131610037SARM gem5 Developers } 131710037SARM gem5 Developers } 131810037SARM gem5 Developers case 0x2: 131910037SARM gem5 Developers { 132010037SARM gem5 Developers uint8_t opc = bits(machInst, 31, 30); 132110037SARM gem5 Developers if (opc >= 3) 132210037SARM gem5 Developers return new Unknown64(machInst); 132310037SARM gem5 Developers uint32_t size = 0; 132410037SARM gem5 Developers bool fp = bits(machInst, 26); 132510037SARM gem5 Developers bool load = bits(machInst, 22); 132610037SARM gem5 Developers if (fp) { 132710037SARM gem5 Developers size = 4 << opc; 132810037SARM gem5 Developers } else { 132910037SARM gem5 Developers if ((opc == 1) && !load) 133010037SARM gem5 Developers return new Unknown64(machInst); 133110037SARM gem5 Developers size = (opc == 0 || opc == 1) ? 4 : 8; 133210037SARM gem5 Developers } 133310037SARM gem5 Developers uint8_t type = bits(machInst, 24, 23); 133410037SARM gem5 Developers int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 133510037SARM gem5 Developers 133610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 133710037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 133810037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 133910037SARM gem5 Developers 134010037SARM gem5 Developers bool noAlloc = (type == 0); 134110037SARM gem5 Developers bool signExt = !noAlloc && !fp && opc == 1; 134210037SARM gem5 Developers PairMemOp::AddrMode mode; 134310037SARM gem5 Developers const char *mnemonic = NULL; 134410037SARM gem5 Developers switch (type) { 134510037SARM gem5 Developers case 0x0: 134610037SARM gem5 Developers case 0x2: 134710037SARM gem5 Developers mode = PairMemOp::AddrMd_Offset; 134810037SARM gem5 Developers break; 134910037SARM gem5 Developers case 0x1: 135010037SARM gem5 Developers mode = PairMemOp::AddrMd_PostIndex; 135110037SARM gem5 Developers break; 135210037SARM gem5 Developers case 0x3: 135310037SARM gem5 Developers mode = PairMemOp::AddrMd_PreIndex; 135410037SARM gem5 Developers break; 135510037SARM gem5 Developers default: 135610037SARM gem5 Developers return new Unknown64(machInst); 135710037SARM gem5 Developers } 135810037SARM gem5 Developers if (load) { 135910037SARM gem5 Developers if (noAlloc) 136010037SARM gem5 Developers mnemonic = "ldnp"; 136110037SARM gem5 Developers else if (signExt) 136210037SARM gem5 Developers mnemonic = "ldpsw"; 136310037SARM gem5 Developers else 136410037SARM gem5 Developers mnemonic = "ldp"; 136510037SARM gem5 Developers } else { 136610037SARM gem5 Developers if (noAlloc) 136710037SARM gem5 Developers mnemonic = "stnp"; 136810037SARM gem5 Developers else 136910037SARM gem5 Developers mnemonic = "stp"; 137010037SARM gem5 Developers } 137110037SARM gem5 Developers 137210037SARM gem5 Developers return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 137310037SARM gem5 Developers signExt, false, false, imm, mode, rn, rt, rt2); 137410037SARM gem5 Developers } 137510037SARM gem5 Developers // bit 29:27=111, 25=0 137610037SARM gem5 Developers case 0x3: 137710037SARM gem5 Developers { 137810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 137910037SARM gem5 Developers (bits(machInst, 26) << 2) | 138010037SARM gem5 Developers (bits(machInst, 31, 30) << 3); 138110037SARM gem5 Developers if (bits(machInst, 24) == 1) { 138210037SARM gem5 Developers uint64_t imm12 = bits(machInst, 21, 10); 138310037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 138410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 138510037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 138610037SARM gem5 Developers switch (switchVal) { 138710037SARM gem5 Developers case 0x00: 138810037SARM gem5 Developers return new STRB64_IMM(machInst, rt, rnsp, imm12); 138910037SARM gem5 Developers case 0x01: 139010037SARM gem5 Developers return new LDRB64_IMM(machInst, rt, rnsp, imm12); 139110037SARM gem5 Developers case 0x02: 139210037SARM gem5 Developers return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 139310037SARM gem5 Developers case 0x03: 139410037SARM gem5 Developers return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 139510037SARM gem5 Developers case 0x04: 139610037SARM gem5 Developers return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 139710037SARM gem5 Developers case 0x05: 139810037SARM gem5 Developers return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 139910037SARM gem5 Developers case 0x06: 140010037SARM gem5 Developers return new BigFpMemImm("str", machInst, false, 140110037SARM gem5 Developers rt, rnsp, imm12 << 4); 140210037SARM gem5 Developers case 0x07: 140310037SARM gem5 Developers return new BigFpMemImm("ldr", machInst, true, 140410037SARM gem5 Developers rt, rnsp, imm12 << 4); 140510037SARM gem5 Developers case 0x08: 140610037SARM gem5 Developers return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 140710037SARM gem5 Developers case 0x09: 140810037SARM gem5 Developers return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 140910037SARM gem5 Developers case 0x0a: 141010037SARM gem5 Developers return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 141110037SARM gem5 Developers case 0x0b: 141210037SARM gem5 Developers return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 141310037SARM gem5 Developers case 0x0c: 141410037SARM gem5 Developers return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 141510037SARM gem5 Developers case 0x0d: 141610037SARM gem5 Developers return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 141710037SARM gem5 Developers case 0x10: 141810037SARM gem5 Developers return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 141910037SARM gem5 Developers case 0x11: 142010037SARM gem5 Developers return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 142110037SARM gem5 Developers case 0x12: 142210037SARM gem5 Developers return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 142310037SARM gem5 Developers case 0x14: 142410037SARM gem5 Developers return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 142510037SARM gem5 Developers case 0x15: 142610037SARM gem5 Developers return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 142710037SARM gem5 Developers case 0x18: 142810037SARM gem5 Developers return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 142910037SARM gem5 Developers case 0x19: 143010037SARM gem5 Developers return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 143110037SARM gem5 Developers case 0x1a: 143210037SARM gem5 Developers return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 143310037SARM gem5 Developers case 0x1c: 143410037SARM gem5 Developers return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 143510037SARM gem5 Developers case 0x1d: 143610037SARM gem5 Developers return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 143710037SARM gem5 Developers default: 143810037SARM gem5 Developers return new Unknown64(machInst); 143910037SARM gem5 Developers } 144010037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 144112856Sgiacomo.gabrielli@arm.com uint8_t group = bits(machInst, 11, 10); 144212856Sgiacomo.gabrielli@arm.com switch (group) { 144312856Sgiacomo.gabrielli@arm.com case 0x0: 144412856Sgiacomo.gabrielli@arm.com { 144512856Sgiacomo.gabrielli@arm.com if ((switchVal & 0x7) == 0x2 && 144612856Sgiacomo.gabrielli@arm.com bits(machInst, 20, 12) == 0x1fc) { 144712856Sgiacomo.gabrielli@arm.com IntRegIndex rt = (IntRegIndex)(uint32_t) 144812856Sgiacomo.gabrielli@arm.com bits(machInst, 4, 0); 144912856Sgiacomo.gabrielli@arm.com IntRegIndex rn = (IntRegIndex)(uint32_t) 145012856Sgiacomo.gabrielli@arm.com bits(machInst, 9, 5); 145112856Sgiacomo.gabrielli@arm.com IntRegIndex rnsp = makeSP(rn); 145212856Sgiacomo.gabrielli@arm.com uint8_t size = bits(machInst, 31, 30); 145312856Sgiacomo.gabrielli@arm.com switch (size) { 145412856Sgiacomo.gabrielli@arm.com case 0x0: 145512856Sgiacomo.gabrielli@arm.com return new LDAPRB64(machInst, rt, rnsp); 145612856Sgiacomo.gabrielli@arm.com case 0x1: 145712856Sgiacomo.gabrielli@arm.com return new LDAPRH64(machInst, rt, rnsp); 145812856Sgiacomo.gabrielli@arm.com case 0x2: 145912856Sgiacomo.gabrielli@arm.com return new LDAPRW64(machInst, rt, rnsp); 146012856Sgiacomo.gabrielli@arm.com case 0x3: 146112856Sgiacomo.gabrielli@arm.com return new LDAPRX64(machInst, rt, rnsp); 146212856Sgiacomo.gabrielli@arm.com default: 146312856Sgiacomo.gabrielli@arm.com M5_UNREACHABLE; 146412856Sgiacomo.gabrielli@arm.com } 146512856Sgiacomo.gabrielli@arm.com } else { 146614157Sjordi.vaquero@metempsy.com return decodeAtomicArithOp(machInst); 146712856Sgiacomo.gabrielli@arm.com } 146812856Sgiacomo.gabrielli@arm.com } 146912856Sgiacomo.gabrielli@arm.com case 0x2: 147012856Sgiacomo.gabrielli@arm.com { 147112856Sgiacomo.gabrielli@arm.com if (!bits(machInst, 14)) 147212856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 147312856Sgiacomo.gabrielli@arm.com IntRegIndex rt = (IntRegIndex)(uint32_t) 147412856Sgiacomo.gabrielli@arm.com bits(machInst, 4, 0); 147512856Sgiacomo.gabrielli@arm.com IntRegIndex rn = (IntRegIndex)(uint32_t) 147612856Sgiacomo.gabrielli@arm.com bits(machInst, 9, 5); 147712856Sgiacomo.gabrielli@arm.com IntRegIndex rnsp = makeSP(rn); 147812856Sgiacomo.gabrielli@arm.com IntRegIndex rm = (IntRegIndex)(uint32_t) 147912856Sgiacomo.gabrielli@arm.com bits(machInst, 20, 16); 148012856Sgiacomo.gabrielli@arm.com ArmExtendType type = 148112856Sgiacomo.gabrielli@arm.com (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 148212856Sgiacomo.gabrielli@arm.com uint8_t s = bits(machInst, 12); 148312856Sgiacomo.gabrielli@arm.com switch (switchVal) { 148412856Sgiacomo.gabrielli@arm.com case 0x00: 148512856Sgiacomo.gabrielli@arm.com return new STRB64_REG(machInst, rt, rnsp, rm, 148612856Sgiacomo.gabrielli@arm.com type, 0); 148712856Sgiacomo.gabrielli@arm.com case 0x01: 148812856Sgiacomo.gabrielli@arm.com return new LDRB64_REG(machInst, rt, rnsp, rm, 148912856Sgiacomo.gabrielli@arm.com type, 0); 149012856Sgiacomo.gabrielli@arm.com case 0x02: 149112856Sgiacomo.gabrielli@arm.com return new LDRSBX64_REG(machInst, rt, rnsp, rm, 149212856Sgiacomo.gabrielli@arm.com type, 0); 149312856Sgiacomo.gabrielli@arm.com case 0x03: 149412856Sgiacomo.gabrielli@arm.com return new LDRSBW64_REG(machInst, rt, rnsp, rm, 149512856Sgiacomo.gabrielli@arm.com type, 0); 149612856Sgiacomo.gabrielli@arm.com case 0x04: 149712856Sgiacomo.gabrielli@arm.com return new STRBFP64_REG(machInst, rt, rnsp, rm, 149812856Sgiacomo.gabrielli@arm.com type, 0); 149912856Sgiacomo.gabrielli@arm.com case 0x05: 150012856Sgiacomo.gabrielli@arm.com return new LDRBFP64_REG(machInst, rt, rnsp, rm, 150112856Sgiacomo.gabrielli@arm.com type, 0); 150212856Sgiacomo.gabrielli@arm.com case 0x6: 150312856Sgiacomo.gabrielli@arm.com return new BigFpMemReg("str", machInst, false, 150412856Sgiacomo.gabrielli@arm.com rt, rnsp, rm, type, s * 4); 150512856Sgiacomo.gabrielli@arm.com case 0x7: 150612856Sgiacomo.gabrielli@arm.com return new BigFpMemReg("ldr", machInst, true, 150712856Sgiacomo.gabrielli@arm.com rt, rnsp, rm, type, s * 4); 150812856Sgiacomo.gabrielli@arm.com case 0x08: 150912856Sgiacomo.gabrielli@arm.com return new STRH64_REG(machInst, rt, rnsp, rm, 151012856Sgiacomo.gabrielli@arm.com type, s); 151112856Sgiacomo.gabrielli@arm.com case 0x09: 151212856Sgiacomo.gabrielli@arm.com return new LDRH64_REG(machInst, rt, rnsp, rm, 151312856Sgiacomo.gabrielli@arm.com type, s); 151412856Sgiacomo.gabrielli@arm.com case 0x0a: 151512856Sgiacomo.gabrielli@arm.com return new LDRSHX64_REG(machInst, rt, rnsp, rm, 151612856Sgiacomo.gabrielli@arm.com type, s); 151712856Sgiacomo.gabrielli@arm.com case 0x0b: 151812856Sgiacomo.gabrielli@arm.com return new LDRSHW64_REG(machInst, rt, rnsp, rm, 151912856Sgiacomo.gabrielli@arm.com type, s); 152012856Sgiacomo.gabrielli@arm.com case 0x0c: 152112856Sgiacomo.gabrielli@arm.com return new STRHFP64_REG(machInst, rt, rnsp, rm, 152212856Sgiacomo.gabrielli@arm.com type, s); 152312856Sgiacomo.gabrielli@arm.com case 0x0d: 152412856Sgiacomo.gabrielli@arm.com return new LDRHFP64_REG(machInst, rt, rnsp, rm, 152512856Sgiacomo.gabrielli@arm.com type, s); 152612856Sgiacomo.gabrielli@arm.com case 0x10: 152712856Sgiacomo.gabrielli@arm.com return new STRW64_REG(machInst, rt, rnsp, rm, 152812856Sgiacomo.gabrielli@arm.com type, s * 2); 152912856Sgiacomo.gabrielli@arm.com case 0x11: 153012856Sgiacomo.gabrielli@arm.com return new LDRW64_REG(machInst, rt, rnsp, rm, 153112856Sgiacomo.gabrielli@arm.com type, s * 2); 153212856Sgiacomo.gabrielli@arm.com case 0x12: 153312856Sgiacomo.gabrielli@arm.com return new LDRSW64_REG(machInst, rt, rnsp, rm, 153412856Sgiacomo.gabrielli@arm.com type, s * 2); 153512856Sgiacomo.gabrielli@arm.com case 0x14: 153612856Sgiacomo.gabrielli@arm.com return new STRSFP64_REG(machInst, rt, rnsp, rm, 153712856Sgiacomo.gabrielli@arm.com type, s * 2); 153812856Sgiacomo.gabrielli@arm.com case 0x15: 153912856Sgiacomo.gabrielli@arm.com return new LDRSFP64_REG(machInst, rt, rnsp, rm, 154012856Sgiacomo.gabrielli@arm.com type, s * 2); 154112856Sgiacomo.gabrielli@arm.com case 0x18: 154212856Sgiacomo.gabrielli@arm.com return new STRX64_REG(machInst, rt, rnsp, rm, 154312856Sgiacomo.gabrielli@arm.com type, s * 3); 154412856Sgiacomo.gabrielli@arm.com case 0x19: 154512856Sgiacomo.gabrielli@arm.com return new LDRX64_REG(machInst, rt, rnsp, rm, 154612856Sgiacomo.gabrielli@arm.com type, s * 3); 154712856Sgiacomo.gabrielli@arm.com case 0x1a: 154812856Sgiacomo.gabrielli@arm.com return new PRFM64_REG(machInst, rt, rnsp, rm, 154912856Sgiacomo.gabrielli@arm.com type, s * 3); 155012856Sgiacomo.gabrielli@arm.com case 0x1c: 155112856Sgiacomo.gabrielli@arm.com return new STRDFP64_REG(machInst, rt, rnsp, rm, 155212856Sgiacomo.gabrielli@arm.com type, s * 3); 155312856Sgiacomo.gabrielli@arm.com case 0x1d: 155412856Sgiacomo.gabrielli@arm.com return new LDRDFP64_REG(machInst, rt, rnsp, rm, 155512856Sgiacomo.gabrielli@arm.com type, s * 3); 155612856Sgiacomo.gabrielli@arm.com default: 155712856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 155812856Sgiacomo.gabrielli@arm.com 155912856Sgiacomo.gabrielli@arm.com } 156012856Sgiacomo.gabrielli@arm.com } 156110037SARM gem5 Developers default: 156210037SARM gem5 Developers return new Unknown64(machInst); 156310037SARM gem5 Developers } 156410037SARM gem5 Developers } else { 156510037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0 156610037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 156710037SARM gem5 Developers case 0x0: 156810037SARM gem5 Developers { 156910037SARM gem5 Developers IntRegIndex rt = 157010037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 157110037SARM gem5 Developers IntRegIndex rn = 157210037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 157310037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 157410037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 157510037SARM gem5 Developers switch (switchVal) { 157610037SARM gem5 Developers case 0x00: 157710037SARM gem5 Developers return new STURB64_IMM(machInst, rt, rnsp, imm); 157810037SARM gem5 Developers case 0x01: 157910037SARM gem5 Developers return new LDURB64_IMM(machInst, rt, rnsp, imm); 158010037SARM gem5 Developers case 0x02: 158110037SARM gem5 Developers return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 158210037SARM gem5 Developers case 0x03: 158310037SARM gem5 Developers return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 158410037SARM gem5 Developers case 0x04: 158510037SARM gem5 Developers return new STURBFP64_IMM(machInst, rt, rnsp, imm); 158610037SARM gem5 Developers case 0x05: 158710037SARM gem5 Developers return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 158810037SARM gem5 Developers case 0x06: 158910037SARM gem5 Developers return new BigFpMemImm("stur", machInst, false, 159010037SARM gem5 Developers rt, rnsp, imm); 159110037SARM gem5 Developers case 0x07: 159210037SARM gem5 Developers return new BigFpMemImm("ldur", machInst, true, 159310037SARM gem5 Developers rt, rnsp, imm); 159410037SARM gem5 Developers case 0x08: 159510037SARM gem5 Developers return new STURH64_IMM(machInst, rt, rnsp, imm); 159610037SARM gem5 Developers case 0x09: 159710037SARM gem5 Developers return new LDURH64_IMM(machInst, rt, rnsp, imm); 159810037SARM gem5 Developers case 0x0a: 159910037SARM gem5 Developers return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 160010037SARM gem5 Developers case 0x0b: 160110037SARM gem5 Developers return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 160210037SARM gem5 Developers case 0x0c: 160310037SARM gem5 Developers return new STURHFP64_IMM(machInst, rt, rnsp, imm); 160410037SARM gem5 Developers case 0x0d: 160510037SARM gem5 Developers return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 160610037SARM gem5 Developers case 0x10: 160710037SARM gem5 Developers return new STURW64_IMM(machInst, rt, rnsp, imm); 160810037SARM gem5 Developers case 0x11: 160910037SARM gem5 Developers return new LDURW64_IMM(machInst, rt, rnsp, imm); 161010037SARM gem5 Developers case 0x12: 161110037SARM gem5 Developers return new LDURSW64_IMM(machInst, rt, rnsp, imm); 161210037SARM gem5 Developers case 0x14: 161310037SARM gem5 Developers return new STURSFP64_IMM(machInst, rt, rnsp, imm); 161410037SARM gem5 Developers case 0x15: 161510037SARM gem5 Developers return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 161610037SARM gem5 Developers case 0x18: 161710037SARM gem5 Developers return new STURX64_IMM(machInst, rt, rnsp, imm); 161810037SARM gem5 Developers case 0x19: 161910037SARM gem5 Developers return new LDURX64_IMM(machInst, rt, rnsp, imm); 162010037SARM gem5 Developers case 0x1a: 162110037SARM gem5 Developers return new PRFUM64_IMM(machInst, rt, rnsp, imm); 162210037SARM gem5 Developers case 0x1c: 162310037SARM gem5 Developers return new STURDFP64_IMM(machInst, rt, rnsp, imm); 162410037SARM gem5 Developers case 0x1d: 162510037SARM gem5 Developers return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 162610037SARM gem5 Developers default: 162710037SARM gem5 Developers return new Unknown64(machInst); 162810037SARM gem5 Developers } 162910037SARM gem5 Developers } 163010037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0, 11:10=01 163110037SARM gem5 Developers case 0x1: 163210037SARM gem5 Developers { 163310037SARM gem5 Developers IntRegIndex rt = 163410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 163510037SARM gem5 Developers IntRegIndex rn = 163610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 163710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 163810037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 163910037SARM gem5 Developers switch (switchVal) { 164010037SARM gem5 Developers case 0x00: 164110037SARM gem5 Developers return new STRB64_POST(machInst, rt, rnsp, imm); 164210037SARM gem5 Developers case 0x01: 164310037SARM gem5 Developers return new LDRB64_POST(machInst, rt, rnsp, imm); 164410037SARM gem5 Developers case 0x02: 164510037SARM gem5 Developers return new LDRSBX64_POST(machInst, rt, rnsp, imm); 164610037SARM gem5 Developers case 0x03: 164710037SARM gem5 Developers return new LDRSBW64_POST(machInst, rt, rnsp, imm); 164810037SARM gem5 Developers case 0x04: 164910037SARM gem5 Developers return new STRBFP64_POST(machInst, rt, rnsp, imm); 165010037SARM gem5 Developers case 0x05: 165110037SARM gem5 Developers return new LDRBFP64_POST(machInst, rt, rnsp, imm); 165210037SARM gem5 Developers case 0x06: 165310037SARM gem5 Developers return new BigFpMemPost("str", machInst, false, 165410037SARM gem5 Developers rt, rnsp, imm); 165510037SARM gem5 Developers case 0x07: 165610037SARM gem5 Developers return new BigFpMemPost("ldr", machInst, true, 165710037SARM gem5 Developers rt, rnsp, imm); 165810037SARM gem5 Developers case 0x08: 165910037SARM gem5 Developers return new STRH64_POST(machInst, rt, rnsp, imm); 166010037SARM gem5 Developers case 0x09: 166110037SARM gem5 Developers return new LDRH64_POST(machInst, rt, rnsp, imm); 166210037SARM gem5 Developers case 0x0a: 166310037SARM gem5 Developers return new LDRSHX64_POST(machInst, rt, rnsp, imm); 166410037SARM gem5 Developers case 0x0b: 166510037SARM gem5 Developers return new LDRSHW64_POST(machInst, rt, rnsp, imm); 166610037SARM gem5 Developers case 0x0c: 166710037SARM gem5 Developers return new STRHFP64_POST(machInst, rt, rnsp, imm); 166810037SARM gem5 Developers case 0x0d: 166910037SARM gem5 Developers return new LDRHFP64_POST(machInst, rt, rnsp, imm); 167010037SARM gem5 Developers case 0x10: 167110037SARM gem5 Developers return new STRW64_POST(machInst, rt, rnsp, imm); 167210037SARM gem5 Developers case 0x11: 167310037SARM gem5 Developers return new LDRW64_POST(machInst, rt, rnsp, imm); 167410037SARM gem5 Developers case 0x12: 167510037SARM gem5 Developers return new LDRSW64_POST(machInst, rt, rnsp, imm); 167610037SARM gem5 Developers case 0x14: 167710037SARM gem5 Developers return new STRSFP64_POST(machInst, rt, rnsp, imm); 167810037SARM gem5 Developers case 0x15: 167910037SARM gem5 Developers return new LDRSFP64_POST(machInst, rt, rnsp, imm); 168010037SARM gem5 Developers case 0x18: 168110037SARM gem5 Developers return new STRX64_POST(machInst, rt, rnsp, imm); 168210037SARM gem5 Developers case 0x19: 168310037SARM gem5 Developers return new LDRX64_POST(machInst, rt, rnsp, imm); 168410037SARM gem5 Developers case 0x1c: 168510037SARM gem5 Developers return new STRDFP64_POST(machInst, rt, rnsp, imm); 168610037SARM gem5 Developers case 0x1d: 168710037SARM gem5 Developers return new LDRDFP64_POST(machInst, rt, rnsp, imm); 168810037SARM gem5 Developers default: 168910037SARM gem5 Developers return new Unknown64(machInst); 169010037SARM gem5 Developers } 169110037SARM gem5 Developers } 169210037SARM gem5 Developers case 0x2: 169310037SARM gem5 Developers { 169410037SARM gem5 Developers IntRegIndex rt = 169510037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 169610037SARM gem5 Developers IntRegIndex rn = 169710037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 169810037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 169910037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 170010037SARM gem5 Developers switch (switchVal) { 170110037SARM gem5 Developers case 0x00: 170210037SARM gem5 Developers return new STTRB64_IMM(machInst, rt, rnsp, imm); 170310037SARM gem5 Developers case 0x01: 170410037SARM gem5 Developers return new LDTRB64_IMM(machInst, rt, rnsp, imm); 170510037SARM gem5 Developers case 0x02: 170610037SARM gem5 Developers return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 170710037SARM gem5 Developers case 0x03: 170810037SARM gem5 Developers return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 170910037SARM gem5 Developers case 0x08: 171010037SARM gem5 Developers return new STTRH64_IMM(machInst, rt, rnsp, imm); 171110037SARM gem5 Developers case 0x09: 171210037SARM gem5 Developers return new LDTRH64_IMM(machInst, rt, rnsp, imm); 171310037SARM gem5 Developers case 0x0a: 171410037SARM gem5 Developers return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 171510037SARM gem5 Developers case 0x0b: 171610037SARM gem5 Developers return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 171710037SARM gem5 Developers case 0x10: 171810037SARM gem5 Developers return new STTRW64_IMM(machInst, rt, rnsp, imm); 171910037SARM gem5 Developers case 0x11: 172010037SARM gem5 Developers return new LDTRW64_IMM(machInst, rt, rnsp, imm); 172110037SARM gem5 Developers case 0x12: 172210037SARM gem5 Developers return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 172310037SARM gem5 Developers case 0x18: 172410037SARM gem5 Developers return new STTRX64_IMM(machInst, rt, rnsp, imm); 172510037SARM gem5 Developers case 0x19: 172610037SARM gem5 Developers return new LDTRX64_IMM(machInst, rt, rnsp, imm); 172710037SARM gem5 Developers default: 172810037SARM gem5 Developers return new Unknown64(machInst); 172910037SARM gem5 Developers } 173010037SARM gem5 Developers } 173110037SARM gem5 Developers case 0x3: 173210037SARM gem5 Developers { 173310037SARM gem5 Developers IntRegIndex rt = 173410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 173510037SARM gem5 Developers IntRegIndex rn = 173610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 173710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 173810037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 173910037SARM gem5 Developers switch (switchVal) { 174010037SARM gem5 Developers case 0x00: 174110037SARM gem5 Developers return new STRB64_PRE(machInst, rt, rnsp, imm); 174210037SARM gem5 Developers case 0x01: 174310037SARM gem5 Developers return new LDRB64_PRE(machInst, rt, rnsp, imm); 174410037SARM gem5 Developers case 0x02: 174510037SARM gem5 Developers return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 174610037SARM gem5 Developers case 0x03: 174710037SARM gem5 Developers return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 174810037SARM gem5 Developers case 0x04: 174910037SARM gem5 Developers return new STRBFP64_PRE(machInst, rt, rnsp, imm); 175010037SARM gem5 Developers case 0x05: 175110037SARM gem5 Developers return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 175210037SARM gem5 Developers case 0x06: 175310037SARM gem5 Developers return new BigFpMemPre("str", machInst, false, 175410037SARM gem5 Developers rt, rnsp, imm); 175510037SARM gem5 Developers case 0x07: 175610037SARM gem5 Developers return new BigFpMemPre("ldr", machInst, true, 175710037SARM gem5 Developers rt, rnsp, imm); 175810037SARM gem5 Developers case 0x08: 175910037SARM gem5 Developers return new STRH64_PRE(machInst, rt, rnsp, imm); 176010037SARM gem5 Developers case 0x09: 176110037SARM gem5 Developers return new LDRH64_PRE(machInst, rt, rnsp, imm); 176210037SARM gem5 Developers case 0x0a: 176310037SARM gem5 Developers return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 176410037SARM gem5 Developers case 0x0b: 176510037SARM gem5 Developers return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 176610037SARM gem5 Developers case 0x0c: 176710037SARM gem5 Developers return new STRHFP64_PRE(machInst, rt, rnsp, imm); 176810037SARM gem5 Developers case 0x0d: 176910037SARM gem5 Developers return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 177010037SARM gem5 Developers case 0x10: 177110037SARM gem5 Developers return new STRW64_PRE(machInst, rt, rnsp, imm); 177210037SARM gem5 Developers case 0x11: 177310037SARM gem5 Developers return new LDRW64_PRE(machInst, rt, rnsp, imm); 177410037SARM gem5 Developers case 0x12: 177510037SARM gem5 Developers return new LDRSW64_PRE(machInst, rt, rnsp, imm); 177610037SARM gem5 Developers case 0x14: 177710037SARM gem5 Developers return new STRSFP64_PRE(machInst, rt, rnsp, imm); 177810037SARM gem5 Developers case 0x15: 177910037SARM gem5 Developers return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 178010037SARM gem5 Developers case 0x18: 178110037SARM gem5 Developers return new STRX64_PRE(machInst, rt, rnsp, imm); 178210037SARM gem5 Developers case 0x19: 178310037SARM gem5 Developers return new LDRX64_PRE(machInst, rt, rnsp, imm); 178410037SARM gem5 Developers case 0x1c: 178510037SARM gem5 Developers return new STRDFP64_PRE(machInst, rt, rnsp, imm); 178610037SARM gem5 Developers case 0x1d: 178710037SARM gem5 Developers return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 178810037SARM gem5 Developers default: 178910037SARM gem5 Developers return new Unknown64(machInst); 179010037SARM gem5 Developers } 179110037SARM gem5 Developers } 179212595Ssiddhesh.poyarekar@gmail.com default: 179312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 179410037SARM gem5 Developers } 179510037SARM gem5 Developers } 179610037SARM gem5 Developers } 179712595Ssiddhesh.poyarekar@gmail.com default: 179812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 179910037SARM gem5 Developers } 180010037SARM gem5 Developers return new FailUnimplemented("Unhandled Case1", machInst); 180110037SARM gem5 Developers } 180210037SARM gem5 Developers} 180310037SARM gem5 Developers}}; 180410037SARM gem5 Developers 180510037SARM gem5 Developersoutput decoder {{ 180610037SARM gem5 Developersnamespace Aarch64 180710037SARM gem5 Developers{ 180810037SARM gem5 Developers StaticInstPtr 180910037SARM gem5 Developers decodeDataProcReg(ExtMachInst machInst) 181010037SARM gem5 Developers { 181110037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 28) << 1) | 181210037SARM gem5 Developers (bits(machInst, 24) << 0); 181310037SARM gem5 Developers switch (switchVal) { 181410037SARM gem5 Developers case 0x0: 181510037SARM gem5 Developers { 181610037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 21) << 0) | 181710037SARM gem5 Developers (bits(machInst, 30, 29) << 1); 181810037SARM gem5 Developers ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 181910037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 182010037SARM gem5 Developers bool sf = bits(machInst, 31); 182110037SARM gem5 Developers if (!sf && (imm6 & 0x20)) 182210037SARM gem5 Developers return new Unknown64(machInst); 182310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 182410337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 182510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 182610037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 182710037SARM gem5 Developers 182810037SARM gem5 Developers switch (switchVal) { 182910037SARM gem5 Developers case 0x0: 183010337SAndrew.Bardsley@arm.com return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 183110037SARM gem5 Developers case 0x1: 183210337SAndrew.Bardsley@arm.com return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 183310037SARM gem5 Developers case 0x2: 183410337SAndrew.Bardsley@arm.com return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 183510037SARM gem5 Developers case 0x3: 183610337SAndrew.Bardsley@arm.com return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 183710037SARM gem5 Developers case 0x4: 183810337SAndrew.Bardsley@arm.com return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 183910037SARM gem5 Developers case 0x5: 184010337SAndrew.Bardsley@arm.com return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 184110037SARM gem5 Developers case 0x6: 184210337SAndrew.Bardsley@arm.com return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 184310037SARM gem5 Developers case 0x7: 184410337SAndrew.Bardsley@arm.com return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 184512595Ssiddhesh.poyarekar@gmail.com default: 184612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 184710037SARM gem5 Developers } 184810037SARM gem5 Developers } 184910037SARM gem5 Developers case 0x1: 185010037SARM gem5 Developers { 185110037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 185210037SARM gem5 Developers if (bits(machInst, 21) == 0) { 185310037SARM gem5 Developers ArmShiftType type = 185410037SARM gem5 Developers (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 185510037SARM gem5 Developers if (type == ROR) 185610037SARM gem5 Developers return new Unknown64(machInst); 185710037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 185810037SARM gem5 Developers if (!bits(machInst, 31) && bits(imm6, 5)) 185910037SARM gem5 Developers return new Unknown64(machInst); 186010037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 186110337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 186210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 186310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 186410037SARM gem5 Developers switch (switchVal) { 186510037SARM gem5 Developers case 0x0: 186610337SAndrew.Bardsley@arm.com return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 186710037SARM gem5 Developers case 0x1: 186810337SAndrew.Bardsley@arm.com return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 186910037SARM gem5 Developers case 0x2: 187010337SAndrew.Bardsley@arm.com return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 187110037SARM gem5 Developers case 0x3: 187210337SAndrew.Bardsley@arm.com return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 187312595Ssiddhesh.poyarekar@gmail.com default: 187412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 187510037SARM gem5 Developers } 187610037SARM gem5 Developers } else { 187710037SARM gem5 Developers if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 187810037SARM gem5 Developers return new Unknown64(machInst); 187910037SARM gem5 Developers ArmExtendType type = 188010037SARM gem5 Developers (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 188110037SARM gem5 Developers uint8_t imm3 = bits(machInst, 12, 10); 188210037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 188310037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 188410337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 188510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 188610037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 188710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 188810037SARM gem5 Developers 188910037SARM gem5 Developers switch (switchVal) { 189010037SARM gem5 Developers case 0x0: 189110037SARM gem5 Developers return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 189210037SARM gem5 Developers case 0x1: 189310337SAndrew.Bardsley@arm.com return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 189410037SARM gem5 Developers case 0x2: 189510037SARM gem5 Developers return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 189610037SARM gem5 Developers case 0x3: 189710337SAndrew.Bardsley@arm.com return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 189812595Ssiddhesh.poyarekar@gmail.com default: 189912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 190010037SARM gem5 Developers } 190110037SARM gem5 Developers } 190210037SARM gem5 Developers } 190310037SARM gem5 Developers case 0x2: 190410037SARM gem5 Developers { 190510037SARM gem5 Developers if (bits(machInst, 21) == 1) 190610037SARM gem5 Developers return new Unknown64(machInst); 190710037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 190810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 190910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 191010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 191110037SARM gem5 Developers switch (bits(machInst, 23, 22)) { 191210037SARM gem5 Developers case 0x0: 191310037SARM gem5 Developers { 191410037SARM gem5 Developers if (bits(machInst, 15, 10)) 191510037SARM gem5 Developers return new Unknown64(machInst); 191610037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 191710037SARM gem5 Developers switch (switchVal) { 191810037SARM gem5 Developers case 0x0: 191910337SAndrew.Bardsley@arm.com return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 192010037SARM gem5 Developers case 0x1: 192110337SAndrew.Bardsley@arm.com return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 192210037SARM gem5 Developers case 0x2: 192310337SAndrew.Bardsley@arm.com return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 192410037SARM gem5 Developers case 0x3: 192510337SAndrew.Bardsley@arm.com return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 192612595Ssiddhesh.poyarekar@gmail.com default: 192712595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 192810037SARM gem5 Developers } 192910037SARM gem5 Developers } 193010037SARM gem5 Developers case 0x1: 193110037SARM gem5 Developers { 193210037SARM gem5 Developers if ((bits(machInst, 4) == 1) || 193310037SARM gem5 Developers (bits(machInst, 10) == 1) || 193410037SARM gem5 Developers (bits(machInst, 29) == 0)) { 193510037SARM gem5 Developers return new Unknown64(machInst); 193610037SARM gem5 Developers } 193710037SARM gem5 Developers ConditionCode cond = 193810037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 193910037SARM gem5 Developers uint8_t flags = bits(machInst, 3, 0); 194010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 194110037SARM gem5 Developers if (bits(machInst, 11) == 0) { 194210037SARM gem5 Developers IntRegIndex rm = 194310037SARM gem5 Developers (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 194410037SARM gem5 Developers if (bits(machInst, 30) == 0) { 194510037SARM gem5 Developers return new CcmnReg64(machInst, rn, rm, cond, flags); 194610037SARM gem5 Developers } else { 194710037SARM gem5 Developers return new CcmpReg64(machInst, rn, rm, cond, flags); 194810037SARM gem5 Developers } 194910037SARM gem5 Developers } else { 195010037SARM gem5 Developers uint8_t imm5 = bits(machInst, 20, 16); 195110037SARM gem5 Developers if (bits(machInst, 30) == 0) { 195210037SARM gem5 Developers return new CcmnImm64(machInst, rn, imm5, cond, flags); 195310037SARM gem5 Developers } else { 195410037SARM gem5 Developers return new CcmpImm64(machInst, rn, imm5, cond, flags); 195510037SARM gem5 Developers } 195610037SARM gem5 Developers } 195710037SARM gem5 Developers } 195810037SARM gem5 Developers case 0x2: 195910037SARM gem5 Developers { 196010037SARM gem5 Developers if (bits(machInst, 29) == 1 || 196110037SARM gem5 Developers bits(machInst, 11) == 1) { 196210037SARM gem5 Developers return new Unknown64(machInst); 196310037SARM gem5 Developers } 196410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 10) << 0) | 196510037SARM gem5 Developers (bits(machInst, 30) << 1); 196610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 196710337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 196810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 196910037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 197010037SARM gem5 Developers ConditionCode cond = 197110037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 197210037SARM gem5 Developers switch (switchVal) { 197310037SARM gem5 Developers case 0x0: 197410337SAndrew.Bardsley@arm.com return new Csel64(machInst, rdzr, rn, rm, cond); 197510037SARM gem5 Developers case 0x1: 197610337SAndrew.Bardsley@arm.com return new Csinc64(machInst, rdzr, rn, rm, cond); 197710037SARM gem5 Developers case 0x2: 197810337SAndrew.Bardsley@arm.com return new Csinv64(machInst, rdzr, rn, rm, cond); 197910037SARM gem5 Developers case 0x3: 198010337SAndrew.Bardsley@arm.com return new Csneg64(machInst, rdzr, rn, rm, cond); 198112595Ssiddhesh.poyarekar@gmail.com default: 198212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 198310037SARM gem5 Developers } 198410037SARM gem5 Developers } 198510037SARM gem5 Developers case 0x3: 198610037SARM gem5 Developers if (bits(machInst, 30) == 0) { 198710037SARM gem5 Developers if (bits(machInst, 29) != 0) 198810037SARM gem5 Developers return new Unknown64(machInst); 198910037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 199010037SARM gem5 Developers switch (switchVal) { 199110037SARM gem5 Developers case 0x2: 199210337SAndrew.Bardsley@arm.com return new Udiv64(machInst, rdzr, rn, rm); 199310037SARM gem5 Developers case 0x3: 199410337SAndrew.Bardsley@arm.com return new Sdiv64(machInst, rdzr, rn, rm); 199510037SARM gem5 Developers case 0x8: 199610337SAndrew.Bardsley@arm.com return new Lslv64(machInst, rdzr, rn, rm); 199710037SARM gem5 Developers case 0x9: 199810337SAndrew.Bardsley@arm.com return new Lsrv64(machInst, rdzr, rn, rm); 199910037SARM gem5 Developers case 0xa: 200010337SAndrew.Bardsley@arm.com return new Asrv64(machInst, rdzr, rn, rm); 200110037SARM gem5 Developers case 0xb: 200210337SAndrew.Bardsley@arm.com return new Rorv64(machInst, rdzr, rn, rm); 200312258Sgiacomo.travaglini@arm.com case 0x10: 200412258Sgiacomo.travaglini@arm.com return new Crc32b64(machInst, rdzr, rn, rm); 200512258Sgiacomo.travaglini@arm.com case 0x11: 200612258Sgiacomo.travaglini@arm.com return new Crc32h64(machInst, rdzr, rn, rm); 200712258Sgiacomo.travaglini@arm.com case 0x12: 200812258Sgiacomo.travaglini@arm.com return new Crc32w64(machInst, rdzr, rn, rm); 200912258Sgiacomo.travaglini@arm.com case 0x13: 201012258Sgiacomo.travaglini@arm.com return new Crc32x64(machInst, rdzr, rn, rm); 201112258Sgiacomo.travaglini@arm.com case 0x14: 201212258Sgiacomo.travaglini@arm.com return new Crc32cb64(machInst, rdzr, rn, rm); 201312258Sgiacomo.travaglini@arm.com case 0x15: 201412258Sgiacomo.travaglini@arm.com return new Crc32ch64(machInst, rdzr, rn, rm); 201512258Sgiacomo.travaglini@arm.com case 0x16: 201612258Sgiacomo.travaglini@arm.com return new Crc32cw64(machInst, rdzr, rn, rm); 201712258Sgiacomo.travaglini@arm.com case 0x17: 201812258Sgiacomo.travaglini@arm.com return new Crc32cx64(machInst, rdzr, rn, rm); 201910037SARM gem5 Developers default: 202010037SARM gem5 Developers return new Unknown64(machInst); 202110037SARM gem5 Developers } 202210037SARM gem5 Developers } else { 202310037SARM gem5 Developers if (bits(machInst, 20, 16) != 0 || 202410037SARM gem5 Developers bits(machInst, 29) != 0) { 202510037SARM gem5 Developers return new Unknown64(machInst); 202610037SARM gem5 Developers } 202710037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 202810037SARM gem5 Developers switch (switchVal) { 202910037SARM gem5 Developers case 0x0: 203010337SAndrew.Bardsley@arm.com return new Rbit64(machInst, rdzr, rn); 203110037SARM gem5 Developers case 0x1: 203210337SAndrew.Bardsley@arm.com return new Rev1664(machInst, rdzr, rn); 203310037SARM gem5 Developers case 0x2: 203410037SARM gem5 Developers if (bits(machInst, 31) == 0) 203510337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 203610037SARM gem5 Developers else 203710337SAndrew.Bardsley@arm.com return new Rev3264(machInst, rdzr, rn); 203810037SARM gem5 Developers case 0x3: 203910037SARM gem5 Developers if (bits(machInst, 31) != 1) 204010037SARM gem5 Developers return new Unknown64(machInst); 204110337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 204210037SARM gem5 Developers case 0x4: 204310337SAndrew.Bardsley@arm.com return new Clz64(machInst, rdzr, rn); 204410037SARM gem5 Developers case 0x5: 204510337SAndrew.Bardsley@arm.com return new Cls64(machInst, rdzr, rn); 204612595Ssiddhesh.poyarekar@gmail.com default: 204712595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 204810037SARM gem5 Developers } 204910037SARM gem5 Developers } 205012595Ssiddhesh.poyarekar@gmail.com default: 205112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 205210037SARM gem5 Developers } 205310037SARM gem5 Developers } 205410037SARM gem5 Developers case 0x3: 205510037SARM gem5 Developers { 205610037SARM gem5 Developers if (bits(machInst, 30, 29) != 0x0 || 205710037SARM gem5 Developers (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 205810037SARM gem5 Developers return new Unknown64(machInst); 205910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 206010337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 206110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 206210037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 206310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 206410037SARM gem5 Developers switch (bits(machInst, 23, 21)) { 206510037SARM gem5 Developers case 0x0: 206610037SARM gem5 Developers if (bits(machInst, 15) == 0) 206710337SAndrew.Bardsley@arm.com return new Madd64(machInst, rdzr, ra, rn, rm); 206810037SARM gem5 Developers else 206910337SAndrew.Bardsley@arm.com return new Msub64(machInst, rdzr, ra, rn, rm); 207010037SARM gem5 Developers case 0x1: 207110037SARM gem5 Developers if (bits(machInst, 15) == 0) 207210337SAndrew.Bardsley@arm.com return new Smaddl64(machInst, rdzr, ra, rn, rm); 207310037SARM gem5 Developers else 207410337SAndrew.Bardsley@arm.com return new Smsubl64(machInst, rdzr, ra, rn, rm); 207510037SARM gem5 Developers case 0x2: 207610037SARM gem5 Developers if (bits(machInst, 15) != 0) 207710037SARM gem5 Developers return new Unknown64(machInst); 207810337SAndrew.Bardsley@arm.com return new Smulh64(machInst, rdzr, rn, rm); 207910037SARM gem5 Developers case 0x5: 208010037SARM gem5 Developers if (bits(machInst, 15) == 0) 208110337SAndrew.Bardsley@arm.com return new Umaddl64(machInst, rdzr, ra, rn, rm); 208210037SARM gem5 Developers else 208310337SAndrew.Bardsley@arm.com return new Umsubl64(machInst, rdzr, ra, rn, rm); 208410037SARM gem5 Developers case 0x6: 208510037SARM gem5 Developers if (bits(machInst, 15) != 0) 208610037SARM gem5 Developers return new Unknown64(machInst); 208710337SAndrew.Bardsley@arm.com return new Umulh64(machInst, rdzr, rn, rm); 208810037SARM gem5 Developers default: 208910037SARM gem5 Developers return new Unknown64(machInst); 209010037SARM gem5 Developers } 209110037SARM gem5 Developers } 209212595Ssiddhesh.poyarekar@gmail.com default: 209312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 209410037SARM gem5 Developers } 209510037SARM gem5 Developers return new FailUnimplemented("Unhandled Case2", machInst); 209610037SARM gem5 Developers } 209710037SARM gem5 Developers} 209810037SARM gem5 Developers}}; 209910037SARM gem5 Developers 210010037SARM gem5 Developersoutput decoder {{ 210110037SARM gem5 Developersnamespace Aarch64 210210037SARM gem5 Developers{ 210311165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 210410037SARM gem5 Developers StaticInstPtr 210510037SARM gem5 Developers decodeAdvSIMD(ExtMachInst machInst) 210610037SARM gem5 Developers { 210710037SARM gem5 Developers if (bits(machInst, 24) == 1) { 210810037SARM gem5 Developers if (bits(machInst, 10) == 0) { 210911165SRekai.GonzalezAlberquilla@arm.com return decodeNeonIndexedElem<DecoderFeatures>(machInst); 211010037SARM gem5 Developers } else if (bits(machInst, 23) == 1) { 211110037SARM gem5 Developers return new Unknown64(machInst); 211210037SARM gem5 Developers } else { 211310037SARM gem5 Developers if (bits(machInst, 22, 19)) { 211410037SARM gem5 Developers return decodeNeonShiftByImm(machInst); 211510037SARM gem5 Developers } else { 211610037SARM gem5 Developers return decodeNeonModImm(machInst); 211710037SARM gem5 Developers } 211810037SARM gem5 Developers } 211910037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 212010037SARM gem5 Developers if (bits(machInst, 10) == 1) { 212111165SRekai.GonzalezAlberquilla@arm.com return decodeNeon3Same<DecoderFeatures>(machInst); 212210037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 212310037SARM gem5 Developers return decodeNeon3Diff(machInst); 212410037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 212510037SARM gem5 Developers return decodeNeon2RegMisc(machInst); 212613171Sgiacomo.travaglini@arm.com } else if (bits(machInst, 20, 17) == 0x4) { 212713171Sgiacomo.travaglini@arm.com return decodeCryptoAES(machInst); 212810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 212910037SARM gem5 Developers return decodeNeonAcrossLanes(machInst); 213010037SARM gem5 Developers } else { 213110037SARM gem5 Developers return new Unknown64(machInst); 213210037SARM gem5 Developers } 213310037SARM gem5 Developers } else if (bits(machInst, 24) || 213410037SARM gem5 Developers bits(machInst, 21) || 213510037SARM gem5 Developers bits(machInst, 15)) { 213610037SARM gem5 Developers return new Unknown64(machInst); 213710037SARM gem5 Developers } else if (bits(machInst, 10) == 1) { 213810037SARM gem5 Developers if (bits(machInst, 23, 22)) 213910037SARM gem5 Developers return new Unknown64(machInst); 214010037SARM gem5 Developers return decodeNeonCopy(machInst); 214110037SARM gem5 Developers } else if (bits(machInst, 29) == 1) { 214210037SARM gem5 Developers return decodeNeonExt(machInst); 214310037SARM gem5 Developers } else if (bits(machInst, 11) == 1) { 214410037SARM gem5 Developers return decodeNeonZipUzpTrn(machInst); 214510037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0x0) { 214610037SARM gem5 Developers return decodeNeonTblTbx(machInst); 214710037SARM gem5 Developers } else { 214810037SARM gem5 Developers return new Unknown64(machInst); 214910037SARM gem5 Developers } 215010037SARM gem5 Developers return new FailUnimplemented("Unhandled Case3", machInst); 215110037SARM gem5 Developers } 215210037SARM gem5 Developers} 215310037SARM gem5 Developers}}; 215410037SARM gem5 Developers 215510037SARM gem5 Developers 215610037SARM gem5 Developersoutput decoder {{ 215710037SARM gem5 Developersnamespace Aarch64 215810037SARM gem5 Developers{ 215910037SARM gem5 Developers StaticInstPtr 216010037SARM gem5 Developers // bit 30=0, 28:25=1111 216110037SARM gem5 Developers decodeFp(ExtMachInst machInst) 216210037SARM gem5 Developers { 216310037SARM gem5 Developers if (bits(machInst, 24) == 1) { 216410037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 216510037SARM gem5 Developers return new Unknown64(machInst); 216610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 216710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 216810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 216910037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 217010037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 217110037SARM gem5 Developers (bits(machInst, 15) << 0); 217210037SARM gem5 Developers switch (switchVal) { 217310037SARM gem5 Developers case 0x0: // FMADD Sd = Sa + Sn*Sm 217410037SARM gem5 Developers return new FMAddS(machInst, rd, rn, rm, ra); 217510037SARM gem5 Developers case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 217610037SARM gem5 Developers return new FMSubS(machInst, rd, rn, rm, ra); 217710037SARM gem5 Developers case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 217810037SARM gem5 Developers return new FNMAddS(machInst, rd, rn, rm, ra); 217910037SARM gem5 Developers case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 218010037SARM gem5 Developers return new FNMSubS(machInst, rd, rn, rm, ra); 218110037SARM gem5 Developers case 0x4: // FMADD Dd = Da + Dn*Dm 218210037SARM gem5 Developers return new FMAddD(machInst, rd, rn, rm, ra); 218310037SARM gem5 Developers case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 218410037SARM gem5 Developers return new FMSubD(machInst, rd, rn, rm, ra); 218510037SARM gem5 Developers case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 218610037SARM gem5 Developers return new FNMAddD(machInst, rd, rn, rm, ra); 218710037SARM gem5 Developers case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 218810037SARM gem5 Developers return new FNMSubD(machInst, rd, rn, rm, ra); 218910037SARM gem5 Developers default: 219010037SARM gem5 Developers return new Unknown64(machInst); 219110037SARM gem5 Developers } 219210037SARM gem5 Developers } else if (bits(machInst, 21) == 0) { 219310037SARM gem5 Developers bool s = bits(machInst, 29); 219410037SARM gem5 Developers if (s) 219510037SARM gem5 Developers return new Unknown64(machInst); 219610037SARM gem5 Developers uint8_t switchVal = bits(machInst, 20, 16); 219710037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 219810037SARM gem5 Developers uint8_t scale = bits(machInst, 15, 10); 219910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 220010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 220110037SARM gem5 Developers if (bits(machInst, 18, 17) == 3 && scale != 0) 220210037SARM gem5 Developers return new Unknown64(machInst); 220310037SARM gem5 Developers // 30:24=0011110, 21=0 220410037SARM gem5 Developers switch (switchVal) { 220510037SARM gem5 Developers case 0x00: 220610037SARM gem5 Developers return new FailUnimplemented("fcvtns", machInst); 220710037SARM gem5 Developers case 0x01: 220810037SARM gem5 Developers return new FailUnimplemented("fcvtnu", machInst); 220910037SARM gem5 Developers case 0x02: 221010037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 221110037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 221210037SARM gem5 Developers return new FcvtSFixedFpSW(machInst, rd, rn, scale); 221310037SARM gem5 Developers case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 221410037SARM gem5 Developers return new FcvtSFixedFpDW(machInst, rd, rn, scale); 221510037SARM gem5 Developers case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 221610037SARM gem5 Developers return new FcvtSFixedFpSX(machInst, rd, rn, scale); 221710037SARM gem5 Developers case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 221810037SARM gem5 Developers return new FcvtSFixedFpDX(machInst, rd, rn, scale); 221910037SARM gem5 Developers default: 222010037SARM gem5 Developers return new Unknown64(machInst); 222110037SARM gem5 Developers } 222210037SARM gem5 Developers case 0x03: 222310037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 222410037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 222510037SARM gem5 Developers return new FcvtUFixedFpSW(machInst, rd, rn, scale); 222610037SARM gem5 Developers case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 222710037SARM gem5 Developers return new FcvtUFixedFpDW(machInst, rd, rn, scale); 222810037SARM gem5 Developers case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 222910037SARM gem5 Developers return new FcvtUFixedFpSX(machInst, rd, rn, scale); 223010037SARM gem5 Developers case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 223110037SARM gem5 Developers return new FcvtUFixedFpDX(machInst, rd, rn, scale); 223210037SARM gem5 Developers default: 223310037SARM gem5 Developers return new Unknown64(machInst); 223410037SARM gem5 Developers } 223510037SARM gem5 Developers case 0x04: 223610037SARM gem5 Developers return new FailUnimplemented("fcvtas", machInst); 223710037SARM gem5 Developers case 0x05: 223810037SARM gem5 Developers return new FailUnimplemented("fcvtau", machInst); 223910037SARM gem5 Developers case 0x08: 224010037SARM gem5 Developers return new FailUnimplemented("fcvtps", machInst); 224110037SARM gem5 Developers case 0x09: 224210037SARM gem5 Developers return new FailUnimplemented("fcvtpu", machInst); 224310037SARM gem5 Developers case 0x0e: 224410037SARM gem5 Developers return new FailUnimplemented("fmov elem. to 64", machInst); 224510037SARM gem5 Developers case 0x0f: 224610037SARM gem5 Developers return new FailUnimplemented("fmov 64 bit", machInst); 224710037SARM gem5 Developers case 0x10: 224810037SARM gem5 Developers return new FailUnimplemented("fcvtms", machInst); 224910037SARM gem5 Developers case 0x11: 225010037SARM gem5 Developers return new FailUnimplemented("fcvtmu", machInst); 225110037SARM gem5 Developers case 0x18: 225210037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 225310037SARM gem5 Developers case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 225410037SARM gem5 Developers return new FcvtFpSFixedSW(machInst, rd, rn, scale); 225510037SARM gem5 Developers case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 225610037SARM gem5 Developers return new FcvtFpSFixedDW(machInst, rd, rn, scale); 225710037SARM gem5 Developers case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 225810037SARM gem5 Developers return new FcvtFpSFixedSX(machInst, rd, rn, scale); 225910037SARM gem5 Developers case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 226010037SARM gem5 Developers return new FcvtFpSFixedDX(machInst, rd, rn, scale); 226110037SARM gem5 Developers default: 226210037SARM gem5 Developers return new Unknown64(machInst); 226310037SARM gem5 Developers } 226410037SARM gem5 Developers case 0x19: 226510037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 226610037SARM gem5 Developers case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 226710037SARM gem5 Developers return new FcvtFpUFixedSW(machInst, rd, rn, scale); 226810037SARM gem5 Developers case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 226910037SARM gem5 Developers return new FcvtFpUFixedDW(machInst, rd, rn, scale); 227010037SARM gem5 Developers case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 227110037SARM gem5 Developers return new FcvtFpUFixedSX(machInst, rd, rn, scale); 227210037SARM gem5 Developers case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 227310037SARM gem5 Developers return new FcvtFpUFixedDX(machInst, rd, rn, scale); 227410037SARM gem5 Developers default: 227510037SARM gem5 Developers return new Unknown64(machInst); 227610037SARM gem5 Developers } 227712595Ssiddhesh.poyarekar@gmail.com default: 227812595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 227910037SARM gem5 Developers } 228010037SARM gem5 Developers } else { 228110037SARM gem5 Developers // 30=0, 28:24=11110, 21=1 228210037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 228310037SARM gem5 Developers uint8_t imm8 = bits(machInst, 20, 13); 228410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 228510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 228610037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 228710037SARM gem5 Developers case 0x0: 228810037SARM gem5 Developers if (bits(machInst, 12) == 1) { 228910037SARM gem5 Developers if (bits(machInst, 31) || 229010037SARM gem5 Developers bits(machInst, 29) || 229110037SARM gem5 Developers bits(machInst, 9, 5)) { 229210037SARM gem5 Developers return new Unknown64(machInst); 229310037SARM gem5 Developers } 229410037SARM gem5 Developers // 31:29=000, 28:24=11110, 21=1, 12:10=100 229510037SARM gem5 Developers if (type == 0) { 229610037SARM gem5 Developers // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 229710037SARM gem5 Developers // :imm8<5:0>:Zeros(19) 229813120SEdmund.Grimley-Evans@arm.com uint32_t imm = vfp_modified_imm(imm8, 229913120SEdmund.Grimley-Evans@arm.com FpDataType::Fp32); 230010037SARM gem5 Developers return new FmovImmS(machInst, rd, imm); 230110037SARM gem5 Developers } else if (type == 1) { 230210037SARM gem5 Developers // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 230310037SARM gem5 Developers // :imm8<5:0>:Zeros(48) 230413120SEdmund.Grimley-Evans@arm.com uint64_t imm = vfp_modified_imm(imm8, 230513120SEdmund.Grimley-Evans@arm.com FpDataType::Fp64); 230610037SARM gem5 Developers return new FmovImmD(machInst, rd, imm); 230710037SARM gem5 Developers } else { 230810037SARM gem5 Developers return new Unknown64(machInst); 230910037SARM gem5 Developers } 231010037SARM gem5 Developers } else if (bits(machInst, 13) == 1) { 231110037SARM gem5 Developers if (bits(machInst, 31) || 231210037SARM gem5 Developers bits(machInst, 29) || 231310037SARM gem5 Developers bits(machInst, 15, 14) || 231410037SARM gem5 Developers bits(machInst, 23) || 231510037SARM gem5 Developers bits(machInst, 2, 0)) { 231610037SARM gem5 Developers return new Unknown64(machInst); 231710037SARM gem5 Developers } 231810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 231910037SARM gem5 Developers (bits(machInst, 22) << 2); 232010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) 232110037SARM gem5 Developers bits(machInst, 20, 16); 232210037SARM gem5 Developers // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 232310037SARM gem5 Developers switch (switchVal) { 232410037SARM gem5 Developers case 0x0: 232510037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,Sm) 232610037SARM gem5 Developers return new FCmpRegS(machInst, rn, rm); 232710037SARM gem5 Developers case 0x1: 232810037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,0.0) 232910037SARM gem5 Developers return new FCmpImmS(machInst, rn, 0); 233010037SARM gem5 Developers case 0x2: 233110037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,Sm) 233210037SARM gem5 Developers return new FCmpERegS(machInst, rn, rm); 233310037SARM gem5 Developers case 0x3: 233410037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,0.0) 233510037SARM gem5 Developers return new FCmpEImmS(machInst, rn, 0); 233610037SARM gem5 Developers case 0x4: 233710037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,Dm) 233810037SARM gem5 Developers return new FCmpRegD(machInst, rn, rm); 233910037SARM gem5 Developers case 0x5: 234010037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,0.0) 234110037SARM gem5 Developers return new FCmpImmD(machInst, rn, 0); 234210037SARM gem5 Developers case 0x6: 234310037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,Dm) 234410037SARM gem5 Developers return new FCmpERegD(machInst, rn, rm); 234510037SARM gem5 Developers case 0x7: 234610037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,0.0) 234710037SARM gem5 Developers return new FCmpEImmD(machInst, rn, 0); 234810037SARM gem5 Developers default: 234910037SARM gem5 Developers return new Unknown64(machInst); 235010037SARM gem5 Developers } 235110037SARM gem5 Developers } else if (bits(machInst, 14) == 1) { 235210037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 235310037SARM gem5 Developers return new Unknown64(machInst); 235410037SARM gem5 Developers uint8_t opcode = bits(machInst, 20, 15); 235510037SARM gem5 Developers // Bits 31:24=00011110, 21=1, 14:10=10000 235610037SARM gem5 Developers switch (opcode) { 235710037SARM gem5 Developers case 0x0: 235810037SARM gem5 Developers if (type == 0) 235910037SARM gem5 Developers // FMOV Sd = Sn 236010037SARM gem5 Developers return new FmovRegS(machInst, rd, rn); 236110037SARM gem5 Developers else if (type == 1) 236210037SARM gem5 Developers // FMOV Dd = Dn 236310037SARM gem5 Developers return new FmovRegD(machInst, rd, rn); 236410037SARM gem5 Developers break; 236510037SARM gem5 Developers case 0x1: 236610037SARM gem5 Developers if (type == 0) 236710037SARM gem5 Developers // FABS Sd = abs(Sn) 236810037SARM gem5 Developers return new FAbsS(machInst, rd, rn); 236910037SARM gem5 Developers else if (type == 1) 237010037SARM gem5 Developers // FABS Dd = abs(Dn) 237110037SARM gem5 Developers return new FAbsD(machInst, rd, rn); 237210037SARM gem5 Developers break; 237310037SARM gem5 Developers case 0x2: 237410037SARM gem5 Developers if (type == 0) 237510037SARM gem5 Developers // FNEG Sd = -Sn 237610037SARM gem5 Developers return new FNegS(machInst, rd, rn); 237710037SARM gem5 Developers else if (type == 1) 237810037SARM gem5 Developers // FNEG Dd = -Dn 237910037SARM gem5 Developers return new FNegD(machInst, rd, rn); 238010037SARM gem5 Developers break; 238110037SARM gem5 Developers case 0x3: 238210037SARM gem5 Developers if (type == 0) 238310037SARM gem5 Developers // FSQRT Sd = sqrt(Sn) 238410037SARM gem5 Developers return new FSqrtS(machInst, rd, rn); 238510037SARM gem5 Developers else if (type == 1) 238610037SARM gem5 Developers // FSQRT Dd = sqrt(Dn) 238710037SARM gem5 Developers return new FSqrtD(machInst, rd, rn); 238810037SARM gem5 Developers break; 238910037SARM gem5 Developers case 0x4: 239010037SARM gem5 Developers if (type == 1) 239110037SARM gem5 Developers // FCVT Sd = convertFormat(Dn) 239210037SARM gem5 Developers return new FcvtFpDFpS(machInst, rd, rn); 239310037SARM gem5 Developers else if (type == 3) 239410037SARM gem5 Developers // FCVT Sd = convertFormat(Hn) 239510037SARM gem5 Developers return new FcvtFpHFpS(machInst, rd, rn); 239610037SARM gem5 Developers break; 239710037SARM gem5 Developers case 0x5: 239810037SARM gem5 Developers if (type == 0) 239910037SARM gem5 Developers // FCVT Dd = convertFormat(Sn) 240010037SARM gem5 Developers return new FCvtFpSFpD(machInst, rd, rn); 240110037SARM gem5 Developers else if (type == 3) 240210037SARM gem5 Developers // FCVT Dd = convertFormat(Hn) 240310037SARM gem5 Developers return new FcvtFpHFpD(machInst, rd, rn); 240410037SARM gem5 Developers break; 240510037SARM gem5 Developers case 0x7: 240610037SARM gem5 Developers if (type == 0) 240710037SARM gem5 Developers // FCVT Hd = convertFormat(Sn) 240810037SARM gem5 Developers return new FcvtFpSFpH(machInst, rd, rn); 240910037SARM gem5 Developers else if (type == 1) 241010037SARM gem5 Developers // FCVT Hd = convertFormat(Dn) 241110037SARM gem5 Developers return new FcvtFpDFpH(machInst, rd, rn); 241210037SARM gem5 Developers break; 241310037SARM gem5 Developers case 0x8: 241410037SARM gem5 Developers if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 241510037SARM gem5 Developers return new FRIntNS(machInst, rd, rn); 241610037SARM gem5 Developers else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 241710037SARM gem5 Developers return new FRIntND(machInst, rd, rn); 241810037SARM gem5 Developers break; 241910037SARM gem5 Developers case 0x9: 242010037SARM gem5 Developers if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 242110037SARM gem5 Developers return new FRIntPS(machInst, rd, rn); 242210037SARM gem5 Developers else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 242310037SARM gem5 Developers return new FRIntPD(machInst, rd, rn); 242410037SARM gem5 Developers break; 242510037SARM gem5 Developers case 0xa: 242610037SARM gem5 Developers if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 242710037SARM gem5 Developers return new FRIntMS(machInst, rd, rn); 242810037SARM gem5 Developers else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 242910037SARM gem5 Developers return new FRIntMD(machInst, rd, rn); 243010037SARM gem5 Developers break; 243110037SARM gem5 Developers case 0xb: 243210037SARM gem5 Developers if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 243310037SARM gem5 Developers return new FRIntZS(machInst, rd, rn); 243410037SARM gem5 Developers else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 243510037SARM gem5 Developers return new FRIntZD(machInst, rd, rn); 243610037SARM gem5 Developers break; 243710037SARM gem5 Developers case 0xc: 243810037SARM gem5 Developers if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 243910037SARM gem5 Developers return new FRIntAS(machInst, rd, rn); 244010037SARM gem5 Developers else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 244110037SARM gem5 Developers return new FRIntAD(machInst, rd, rn); 244210037SARM gem5 Developers break; 244310037SARM gem5 Developers case 0xe: 244410037SARM gem5 Developers if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 244510037SARM gem5 Developers return new FRIntXS(machInst, rd, rn); 244610037SARM gem5 Developers else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 244710037SARM gem5 Developers return new FRIntXD(machInst, rd, rn); 244810037SARM gem5 Developers break; 244910037SARM gem5 Developers case 0xf: 245010037SARM gem5 Developers if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 245110037SARM gem5 Developers return new FRIntIS(machInst, rd, rn); 245210037SARM gem5 Developers else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 245310037SARM gem5 Developers return new FRIntID(machInst, rd, rn); 245410037SARM gem5 Developers break; 245510037SARM gem5 Developers default: 245610037SARM gem5 Developers return new Unknown64(machInst); 245710037SARM gem5 Developers } 245810037SARM gem5 Developers return new Unknown64(machInst); 245910037SARM gem5 Developers } else if (bits(machInst, 15) == 1) { 246010037SARM gem5 Developers return new Unknown64(machInst); 246110037SARM gem5 Developers } else { 246210037SARM gem5 Developers if (bits(machInst, 29)) 246310037SARM gem5 Developers return new Unknown64(machInst); 246410037SARM gem5 Developers uint8_t rmode = bits(machInst, 20, 19); 246510037SARM gem5 Developers uint8_t switchVal1 = bits(machInst, 18, 16); 246610037SARM gem5 Developers uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 246710037SARM gem5 Developers // 30:24=0011110, 21=1, 15:10=000000 246810037SARM gem5 Developers switch (switchVal1) { 246910037SARM gem5 Developers case 0x0: 247010037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 247110037SARM gem5 Developers case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 247210037SARM gem5 Developers return new FcvtFpSIntWSN(machInst, rd, rn); 247310037SARM gem5 Developers case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 247410037SARM gem5 Developers return new FcvtFpSIntWSP(machInst, rd, rn); 247510037SARM gem5 Developers case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 247610037SARM gem5 Developers return new FcvtFpSIntWSM(machInst, rd, rn); 247710037SARM gem5 Developers case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 247810037SARM gem5 Developers return new FcvtFpSIntWSZ(machInst, rd, rn); 247910037SARM gem5 Developers case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 248010037SARM gem5 Developers return new FcvtFpSIntXSN(machInst, rd, rn); 248110037SARM gem5 Developers case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 248210037SARM gem5 Developers return new FcvtFpSIntXSP(machInst, rd, rn); 248310037SARM gem5 Developers case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 248410037SARM gem5 Developers return new FcvtFpSIntXSM(machInst, rd, rn); 248510037SARM gem5 Developers case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 248610037SARM gem5 Developers return new FcvtFpSIntXSZ(machInst, rd, rn); 248710037SARM gem5 Developers case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 248810037SARM gem5 Developers return new FcvtFpSIntWDN(machInst, rd, rn); 248910037SARM gem5 Developers case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 249010037SARM gem5 Developers return new FcvtFpSIntWDP(machInst, rd, rn); 249110037SARM gem5 Developers case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 249210037SARM gem5 Developers return new FcvtFpSIntWDM(machInst, rd, rn); 249310037SARM gem5 Developers case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 249410037SARM gem5 Developers return new FcvtFpSIntWDZ(machInst, rd, rn); 249510037SARM gem5 Developers case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 249610037SARM gem5 Developers return new FcvtFpSIntXDN(machInst, rd, rn); 249710037SARM gem5 Developers case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 249810037SARM gem5 Developers return new FcvtFpSIntXDP(machInst, rd, rn); 249910037SARM gem5 Developers case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 250010037SARM gem5 Developers return new FcvtFpSIntXDM(machInst, rd, rn); 250110037SARM gem5 Developers case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 250210037SARM gem5 Developers return new FcvtFpSIntXDZ(machInst, rd, rn); 250310037SARM gem5 Developers default: 250410037SARM gem5 Developers return new Unknown64(machInst); 250510037SARM gem5 Developers } 250610037SARM gem5 Developers case 0x1: 250710037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 250810037SARM gem5 Developers case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 250910037SARM gem5 Developers return new FcvtFpUIntWSN(machInst, rd, rn); 251010037SARM gem5 Developers case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 251110037SARM gem5 Developers return new FcvtFpUIntWSP(machInst, rd, rn); 251210037SARM gem5 Developers case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 251310037SARM gem5 Developers return new FcvtFpUIntWSM(machInst, rd, rn); 251410037SARM gem5 Developers case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 251510037SARM gem5 Developers return new FcvtFpUIntWSZ(machInst, rd, rn); 251610037SARM gem5 Developers case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 251710037SARM gem5 Developers return new FcvtFpUIntXSN(machInst, rd, rn); 251810037SARM gem5 Developers case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 251910037SARM gem5 Developers return new FcvtFpUIntXSP(machInst, rd, rn); 252010037SARM gem5 Developers case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 252110037SARM gem5 Developers return new FcvtFpUIntXSM(machInst, rd, rn); 252210037SARM gem5 Developers case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 252310037SARM gem5 Developers return new FcvtFpUIntXSZ(machInst, rd, rn); 252410037SARM gem5 Developers case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 252510037SARM gem5 Developers return new FcvtFpUIntWDN(machInst, rd, rn); 252610037SARM gem5 Developers case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 252710037SARM gem5 Developers return new FcvtFpUIntWDP(machInst, rd, rn); 252810037SARM gem5 Developers case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 252910037SARM gem5 Developers return new FcvtFpUIntWDM(machInst, rd, rn); 253010037SARM gem5 Developers case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 253110037SARM gem5 Developers return new FcvtFpUIntWDZ(machInst, rd, rn); 253210037SARM gem5 Developers case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 253310037SARM gem5 Developers return new FcvtFpUIntXDN(machInst, rd, rn); 253410037SARM gem5 Developers case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 253510037SARM gem5 Developers return new FcvtFpUIntXDP(machInst, rd, rn); 253610037SARM gem5 Developers case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 253710037SARM gem5 Developers return new FcvtFpUIntXDM(machInst, rd, rn); 253810037SARM gem5 Developers case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 253910037SARM gem5 Developers return new FcvtFpUIntXDZ(machInst, rd, rn); 254010037SARM gem5 Developers default: 254110037SARM gem5 Developers return new Unknown64(machInst); 254210037SARM gem5 Developers } 254310037SARM gem5 Developers case 0x2: 254410037SARM gem5 Developers if (rmode != 0) 254510037SARM gem5 Developers return new Unknown64(machInst); 254610037SARM gem5 Developers switch (switchVal2) { 254710037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn) 254810037SARM gem5 Developers return new FcvtWSIntFpS(machInst, rd, rn); 254910037SARM gem5 Developers case 1: // SCVTF Sd = convertFromInt(Xn) 255010037SARM gem5 Developers return new FcvtXSIntFpS(machInst, rd, rn); 255110037SARM gem5 Developers case 2: // SCVTF Dd = convertFromInt(Wn) 255210037SARM gem5 Developers return new FcvtWSIntFpD(machInst, rd, rn); 255310037SARM gem5 Developers case 3: // SCVTF Dd = convertFromInt(Xn) 255410037SARM gem5 Developers return new FcvtXSIntFpD(machInst, rd, rn); 255510037SARM gem5 Developers default: 255610037SARM gem5 Developers return new Unknown64(machInst); 255710037SARM gem5 Developers } 255810037SARM gem5 Developers case 0x3: 255910037SARM gem5 Developers switch (switchVal2) { 256010037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn) 256110037SARM gem5 Developers return new FcvtWUIntFpS(machInst, rd, rn); 256210037SARM gem5 Developers case 1: // UCVTF Sd = convertFromInt(Xn) 256310037SARM gem5 Developers return new FcvtXUIntFpS(machInst, rd, rn); 256410037SARM gem5 Developers case 2: // UCVTF Dd = convertFromInt(Wn) 256510037SARM gem5 Developers return new FcvtWUIntFpD(machInst, rd, rn); 256610037SARM gem5 Developers case 3: // UCVTF Dd = convertFromInt(Xn) 256710037SARM gem5 Developers return new FcvtXUIntFpD(machInst, rd, rn); 256810037SARM gem5 Developers default: 256910037SARM gem5 Developers return new Unknown64(machInst); 257010037SARM gem5 Developers } 257110037SARM gem5 Developers case 0x4: 257210037SARM gem5 Developers if (rmode != 0) 257310037SARM gem5 Developers return new Unknown64(machInst); 257410037SARM gem5 Developers switch (switchVal2) { 257510037SARM gem5 Developers case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 257610037SARM gem5 Developers return new FcvtFpSIntWSA(machInst, rd, rn); 257710037SARM gem5 Developers case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 257810037SARM gem5 Developers return new FcvtFpSIntXSA(machInst, rd, rn); 257910037SARM gem5 Developers case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 258010037SARM gem5 Developers return new FcvtFpSIntWDA(machInst, rd, rn); 258110037SARM gem5 Developers case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 258210037SARM gem5 Developers return new FcvtFpSIntXDA(machInst, rd, rn); 258310037SARM gem5 Developers default: 258410037SARM gem5 Developers return new Unknown64(machInst); 258510037SARM gem5 Developers } 258610037SARM gem5 Developers case 0x5: 258710037SARM gem5 Developers switch (switchVal2) { 258810037SARM gem5 Developers case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 258910037SARM gem5 Developers return new FcvtFpUIntWSA(machInst, rd, rn); 259010037SARM gem5 Developers case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 259110037SARM gem5 Developers return new FcvtFpUIntXSA(machInst, rd, rn); 259210037SARM gem5 Developers case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 259310037SARM gem5 Developers return new FcvtFpUIntWDA(machInst, rd, rn); 259410037SARM gem5 Developers case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 259510037SARM gem5 Developers return new FcvtFpUIntXDA(machInst, rd, rn); 259610037SARM gem5 Developers default: 259710037SARM gem5 Developers return new Unknown64(machInst); 259810037SARM gem5 Developers } 259910037SARM gem5 Developers case 0x06: 260010037SARM gem5 Developers switch (switchVal2) { 260110037SARM gem5 Developers case 0: // FMOV Wd = Sn 260210037SARM gem5 Developers if (rmode != 0) 260310037SARM gem5 Developers return new Unknown64(machInst); 260410037SARM gem5 Developers return new FmovRegCoreW(machInst, rd, rn); 260510037SARM gem5 Developers case 3: // FMOV Xd = Dn 260610037SARM gem5 Developers if (rmode != 0) 260710037SARM gem5 Developers return new Unknown64(machInst); 260810037SARM gem5 Developers return new FmovRegCoreX(machInst, rd, rn); 260910037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 261010037SARM gem5 Developers if (rmode != 1) 261110037SARM gem5 Developers return new Unknown64(machInst); 261210037SARM gem5 Developers return new FmovURegCoreX(machInst, rd, rn); 261310037SARM gem5 Developers default: 261410037SARM gem5 Developers return new Unknown64(machInst); 261510037SARM gem5 Developers } 261610037SARM gem5 Developers break; 261710037SARM gem5 Developers case 0x07: 261810037SARM gem5 Developers switch (switchVal2) { 261910037SARM gem5 Developers case 0: // FMOV Sd = Wn 262010037SARM gem5 Developers if (rmode != 0) 262110037SARM gem5 Developers return new Unknown64(machInst); 262210037SARM gem5 Developers return new FmovCoreRegW(machInst, rd, rn); 262310037SARM gem5 Developers case 3: // FMOV Xd = Dn 262410037SARM gem5 Developers if (rmode != 0) 262510037SARM gem5 Developers return new Unknown64(machInst); 262610037SARM gem5 Developers return new FmovCoreRegX(machInst, rd, rn); 262710037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 262810037SARM gem5 Developers if (rmode != 1) 262910037SARM gem5 Developers return new Unknown64(machInst); 263010037SARM gem5 Developers return new FmovUCoreRegX(machInst, rd, rn); 263110037SARM gem5 Developers default: 263210037SARM gem5 Developers return new Unknown64(machInst); 263310037SARM gem5 Developers } 263410037SARM gem5 Developers break; 263510037SARM gem5 Developers default: // Warning! missing cases in switch statement above, that still need to be added 263610037SARM gem5 Developers return new Unknown64(machInst); 263710037SARM gem5 Developers } 263810037SARM gem5 Developers } 263912597Schunchenhsu@google.com M5_UNREACHABLE; 264010037SARM gem5 Developers case 0x1: 264110037SARM gem5 Developers { 264210037SARM gem5 Developers if (bits(machInst, 31) || 264310037SARM gem5 Developers bits(machInst, 29) || 264410037SARM gem5 Developers bits(machInst, 23)) { 264510037SARM gem5 Developers return new Unknown64(machInst); 264610037SARM gem5 Developers } 264710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 264810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 264910037SARM gem5 Developers uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 265010037SARM gem5 Developers ConditionCode cond = 265110037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 265210037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4) << 0) | 265310037SARM gem5 Developers (bits(machInst, 22) << 1); 265410037SARM gem5 Developers // 31:23=000111100, 21=1, 11:10=01 265510037SARM gem5 Developers switch (switchVal) { 265610037SARM gem5 Developers case 0x0: 265710037SARM gem5 Developers // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 265810037SARM gem5 Developers return new FCCmpRegS(machInst, rn, rm, cond, imm); 265910037SARM gem5 Developers case 0x1: 266010037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Sn,Sm) 266110037SARM gem5 Developers // else #nzcv 266210037SARM gem5 Developers return new FCCmpERegS(machInst, rn, rm, cond, imm); 266310037SARM gem5 Developers case 0x2: 266410037SARM gem5 Developers // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 266510037SARM gem5 Developers return new FCCmpRegD(machInst, rn, rm, cond, imm); 266610037SARM gem5 Developers case 0x3: 266710037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Dn,Dm) 266810037SARM gem5 Developers // else #nzcv 266910037SARM gem5 Developers return new FCCmpERegD(machInst, rn, rm, cond, imm); 267010037SARM gem5 Developers default: 267110037SARM gem5 Developers return new Unknown64(machInst); 267210037SARM gem5 Developers } 267310037SARM gem5 Developers } 267410037SARM gem5 Developers case 0x2: 267510037SARM gem5 Developers { 267610037SARM gem5 Developers if (bits(machInst, 31) || 267710037SARM gem5 Developers bits(machInst, 29) || 267810037SARM gem5 Developers bits(machInst, 23)) { 267910037SARM gem5 Developers return new Unknown64(machInst); 268010037SARM gem5 Developers } 268110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 268210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 268310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 268410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 268510037SARM gem5 Developers (bits(machInst, 22) << 4); 268610037SARM gem5 Developers switch (switchVal) { 268710037SARM gem5 Developers case 0x00: // FMUL Sd = Sn * Sm 268810037SARM gem5 Developers return new FMulS(machInst, rd, rn, rm); 268910037SARM gem5 Developers case 0x10: // FMUL Dd = Dn * Dm 269010037SARM gem5 Developers return new FMulD(machInst, rd, rn, rm); 269110037SARM gem5 Developers case 0x01: // FDIV Sd = Sn / Sm 269210037SARM gem5 Developers return new FDivS(machInst, rd, rn, rm); 269310037SARM gem5 Developers case 0x11: // FDIV Dd = Dn / Dm 269410037SARM gem5 Developers return new FDivD(machInst, rd, rn, rm); 269510037SARM gem5 Developers case 0x02: // FADD Sd = Sn + Sm 269610037SARM gem5 Developers return new FAddS(machInst, rd, rn, rm); 269710037SARM gem5 Developers case 0x12: // FADD Dd = Dn + Dm 269810037SARM gem5 Developers return new FAddD(machInst, rd, rn, rm); 269910037SARM gem5 Developers case 0x03: // FSUB Sd = Sn - Sm 270010037SARM gem5 Developers return new FSubS(machInst, rd, rn, rm); 270110037SARM gem5 Developers case 0x13: // FSUB Dd = Dn - Dm 270210037SARM gem5 Developers return new FSubD(machInst, rd, rn, rm); 270310037SARM gem5 Developers case 0x04: // FMAX Sd = max(Sn, Sm) 270410037SARM gem5 Developers return new FMaxS(machInst, rd, rn, rm); 270510037SARM gem5 Developers case 0x14: // FMAX Dd = max(Dn, Dm) 270610037SARM gem5 Developers return new FMaxD(machInst, rd, rn, rm); 270710037SARM gem5 Developers case 0x05: // FMIN Sd = min(Sn, Sm) 270810037SARM gem5 Developers return new FMinS(machInst, rd, rn, rm); 270910037SARM gem5 Developers case 0x15: // FMIN Dd = min(Dn, Dm) 271010037SARM gem5 Developers return new FMinD(machInst, rd, rn, rm); 271110037SARM gem5 Developers case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 271210037SARM gem5 Developers return new FMaxNMS(machInst, rd, rn, rm); 271310037SARM gem5 Developers case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 271410037SARM gem5 Developers return new FMaxNMD(machInst, rd, rn, rm); 271510037SARM gem5 Developers case 0x07: // FMINNM Sd = minNum(Sn, Sm) 271610037SARM gem5 Developers return new FMinNMS(machInst, rd, rn, rm); 271710037SARM gem5 Developers case 0x17: // FMINNM Dd = minNum(Dn, Dm) 271810037SARM gem5 Developers return new FMinNMD(machInst, rd, rn, rm); 271910037SARM gem5 Developers case 0x08: // FNMUL Sd = -(Sn * Sm) 272010037SARM gem5 Developers return new FNMulS(machInst, rd, rn, rm); 272110037SARM gem5 Developers case 0x18: // FNMUL Dd = -(Dn * Dm) 272210037SARM gem5 Developers return new FNMulD(machInst, rd, rn, rm); 272310037SARM gem5 Developers default: 272410037SARM gem5 Developers return new Unknown64(machInst); 272510037SARM gem5 Developers } 272610037SARM gem5 Developers } 272710037SARM gem5 Developers case 0x3: 272810037SARM gem5 Developers { 272910037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 273010037SARM gem5 Developers return new Unknown64(machInst); 273110037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 273210037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 273310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 273410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 273510037SARM gem5 Developers ConditionCode cond = 273610037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 273710037SARM gem5 Developers if (type == 0) // FCSEL Sd = if cond then Sn else Sm 273810037SARM gem5 Developers return new FCSelS(machInst, rd, rn, rm, cond); 273910037SARM gem5 Developers else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 274010037SARM gem5 Developers return new FCSelD(machInst, rd, rn, rm, cond); 274110037SARM gem5 Developers else 274210037SARM gem5 Developers return new Unknown64(machInst); 274310037SARM gem5 Developers } 274412595Ssiddhesh.poyarekar@gmail.com default: 274512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 274610037SARM gem5 Developers } 274710037SARM gem5 Developers } 274812597Schunchenhsu@google.com M5_UNREACHABLE; 274910037SARM gem5 Developers } 275010037SARM gem5 Developers} 275110037SARM gem5 Developers}}; 275210037SARM gem5 Developers 275310037SARM gem5 Developersoutput decoder {{ 275410037SARM gem5 Developersnamespace Aarch64 275510037SARM gem5 Developers{ 275610037SARM gem5 Developers StaticInstPtr 275710037SARM gem5 Developers decodeAdvSIMDScalar(ExtMachInst machInst) 275810037SARM gem5 Developers { 275910037SARM gem5 Developers if (bits(machInst, 24) == 1) { 276010037SARM gem5 Developers if (bits(machInst, 10) == 0) { 276110037SARM gem5 Developers return decodeNeonScIndexedElem(machInst); 276210037SARM gem5 Developers } else if (bits(machInst, 23) == 0) { 276310037SARM gem5 Developers return decodeNeonScShiftByImm(machInst); 276410037SARM gem5 Developers } 276510037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 276610037SARM gem5 Developers if (bits(machInst, 10) == 1) { 276710037SARM gem5 Developers return decodeNeonSc3Same(machInst); 276810037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 276910037SARM gem5 Developers return decodeNeonSc3Diff(machInst); 277010037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 277110037SARM gem5 Developers return decodeNeonSc2RegMisc(machInst); 277213170Sgiacomo.travaglini@arm.com } else if (bits(machInst, 20, 17) == 0x4) { 277313170Sgiacomo.travaglini@arm.com return decodeCryptoTwoRegSHA(machInst); 277410037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 277510037SARM gem5 Developers return decodeNeonScPwise(machInst); 277610037SARM gem5 Developers } else { 277710037SARM gem5 Developers return new Unknown64(machInst); 277810037SARM gem5 Developers } 277910037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0 && 278013170Sgiacomo.travaglini@arm.com bits(machInst, 15) == 0) { 278113170Sgiacomo.travaglini@arm.com if (bits(machInst, 10) == 1) { 278213170Sgiacomo.travaglini@arm.com return decodeNeonScCopy(machInst); 278313170Sgiacomo.travaglini@arm.com } else { 278413170Sgiacomo.travaglini@arm.com return decodeCryptoThreeRegSHA(machInst); 278513170Sgiacomo.travaglini@arm.com } 278610037SARM gem5 Developers } else { 278710037SARM gem5 Developers return new Unknown64(machInst); 278810037SARM gem5 Developers } 278910037SARM gem5 Developers return new FailUnimplemented("Unhandled Case6", machInst); 279010037SARM gem5 Developers } 279110037SARM gem5 Developers} 279210037SARM gem5 Developers}}; 279310037SARM gem5 Developers 279410037SARM gem5 Developersoutput decoder {{ 279510037SARM gem5 Developersnamespace Aarch64 279610037SARM gem5 Developers{ 279711165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 279810037SARM gem5 Developers StaticInstPtr 279910037SARM gem5 Developers decodeFpAdvSIMD(ExtMachInst machInst) 280010037SARM gem5 Developers { 280110037SARM gem5 Developers 280210037SARM gem5 Developers if (bits(machInst, 28) == 0) { 280310037SARM gem5 Developers if (bits(machInst, 31) == 0) { 280411165SRekai.GonzalezAlberquilla@arm.com return decodeAdvSIMD<DecoderFeatures>(machInst); 280510037SARM gem5 Developers } else { 280610037SARM gem5 Developers return new Unknown64(machInst); 280710037SARM gem5 Developers } 280810037SARM gem5 Developers } else if (bits(machInst, 30) == 0) { 280910037SARM gem5 Developers return decodeFp(machInst); 281010037SARM gem5 Developers } else if (bits(machInst, 31) == 0) { 281110037SARM gem5 Developers return decodeAdvSIMDScalar(machInst); 281210037SARM gem5 Developers } else { 281310037SARM gem5 Developers return new Unknown64(machInst); 281410037SARM gem5 Developers } 281510037SARM gem5 Developers } 281610037SARM gem5 Developers} 281710037SARM gem5 Developers}}; 281810037SARM gem5 Developers 281911165SRekai.GonzalezAlberquilla@arm.comlet {{ 282011165SRekai.GonzalezAlberquilla@arm.com decoder_output =''' 282111165SRekai.GonzalezAlberquilla@arm.comnamespace Aarch64 282211165SRekai.GonzalezAlberquilla@arm.com{''' 282311165SRekai.GonzalezAlberquilla@arm.com for decoderFlavour, type_dict in decoders.iteritems(): 282411165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 282511165SRekai.GonzalezAlberquilla@arm.comtemplate StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); 282611165SRekai.GonzalezAlberquilla@arm.com''' % { "df" : decoderFlavour } 282711165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 282811165SRekai.GonzalezAlberquilla@arm.com}''' 282911165SRekai.GonzalezAlberquilla@arm.com}}; 283011165SRekai.GonzalezAlberquilla@arm.com 283110037SARM gem5 Developersoutput decoder {{ 283210037SARM gem5 Developersnamespace Aarch64 283310037SARM gem5 Developers{ 283410037SARM gem5 Developers StaticInstPtr 283510037SARM gem5 Developers decodeGem5Ops(ExtMachInst machInst) 283610037SARM gem5 Developers { 283710037SARM gem5 Developers const uint32_t m5func = bits(machInst, 23, 16); 283810037SARM gem5 Developers switch (m5func) { 283912159Sandreas.sandberg@arm.com case M5OP_ARM: return new Arm(machInst); 284012159Sandreas.sandberg@arm.com case M5OP_QUIESCE: return new Quiesce(machInst); 284112159Sandreas.sandberg@arm.com case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst); 284212159Sandreas.sandberg@arm.com case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst); 284312159Sandreas.sandberg@arm.com case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst); 284412159Sandreas.sandberg@arm.com case M5OP_RPNS: return new Rpns64(machInst); 284512159Sandreas.sandberg@arm.com case M5OP_WAKE_CPU: return new WakeCPU64(machInst); 284612159Sandreas.sandberg@arm.com case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); 284712159Sandreas.sandberg@arm.com case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); 284812159Sandreas.sandberg@arm.com case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); 284912159Sandreas.sandberg@arm.com case M5OP_EXIT: return new M5exit64(machInst); 285012159Sandreas.sandberg@arm.com case M5OP_FAIL: return new M5fail64(machInst); 285112159Sandreas.sandberg@arm.com case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); 285212159Sandreas.sandberg@arm.com case M5OP_INIT_PARAM: return new Initparam64(machInst); 285312159Sandreas.sandberg@arm.com case M5OP_RESET_STATS: return new Resetstats64(machInst); 285412159Sandreas.sandberg@arm.com case M5OP_DUMP_STATS: return new Dumpstats64(machInst); 285512159Sandreas.sandberg@arm.com case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst); 285612159Sandreas.sandberg@arm.com case M5OP_CHECKPOINT: return new M5checkpoint64(machInst); 285712159Sandreas.sandberg@arm.com case M5OP_WRITE_FILE: return new M5writefile64(machInst); 285812159Sandreas.sandberg@arm.com case M5OP_READ_FILE: return new M5readfile64(machInst); 285912159Sandreas.sandberg@arm.com case M5OP_DEBUG_BREAK: return new M5break(machInst); 286012159Sandreas.sandberg@arm.com case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); 286112159Sandreas.sandberg@arm.com case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst); 286212159Sandreas.sandberg@arm.com case M5OP_PANIC: return new M5panic(machInst); 286312159Sandreas.sandberg@arm.com case M5OP_WORK_BEGIN: return new M5workbegin64(machInst); 286412159Sandreas.sandberg@arm.com case M5OP_WORK_END: return new M5workend64(machInst); 286510037SARM gem5 Developers default: return new Unknown64(machInst); 286610037SARM gem5 Developers } 286710037SARM gem5 Developers } 286810037SARM gem5 Developers} 286910037SARM gem5 Developers}}; 287010037SARM gem5 Developers 287110037SARM gem5 Developersdef format Aarch64() {{ 287210037SARM gem5 Developers decode_block = ''' 287310037SARM gem5 Developers { 287410037SARM gem5 Developers using namespace Aarch64; 287510037SARM gem5 Developers if (bits(machInst, 27) == 0x0) { 287613759Sgiacomo.gabrielli@arm.com if (bits(machInst, 28) == 0x0) { 287713759Sgiacomo.gabrielli@arm.com if (bits(machInst, 26, 25) != 0x2) { 287813759Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 287913759Sgiacomo.gabrielli@arm.com } 288013759Sgiacomo.gabrielli@arm.com if (bits(machInst, 31) == 0x0) { 288113759Sgiacomo.gabrielli@arm.com switch (bits(machInst, 30, 29)) { 288213759Sgiacomo.gabrielli@arm.com case 0x0: 288313759Sgiacomo.gabrielli@arm.com case 0x1: 288413759Sgiacomo.gabrielli@arm.com case 0x2: 288513759Sgiacomo.gabrielli@arm.com return decodeSveInt(machInst); 288613759Sgiacomo.gabrielli@arm.com case 0x3: 288713759Sgiacomo.gabrielli@arm.com return decodeSveFp(machInst); 288813759Sgiacomo.gabrielli@arm.com } 288913759Sgiacomo.gabrielli@arm.com } else { 289013759Sgiacomo.gabrielli@arm.com return decodeSveMem(machInst); 289113759Sgiacomo.gabrielli@arm.com } 289213759Sgiacomo.gabrielli@arm.com } else if (bits(machInst, 26) == 0) 289310037SARM gem5 Developers // bit 28:26=100 289410037SARM gem5 Developers return decodeDataProcImm(machInst); 289510037SARM gem5 Developers else 289610037SARM gem5 Developers // bit 28:26=101 289710037SARM gem5 Developers return decodeBranchExcSys(machInst); 289810037SARM gem5 Developers } else if (bits(machInst, 25) == 0) { 289910037SARM gem5 Developers // bit 27=1, 25=0 290010037SARM gem5 Developers return decodeLoadsStores(machInst); 290110037SARM gem5 Developers } else if (bits(machInst, 26) == 0) { 290210037SARM gem5 Developers // bit 27:25=101 290310037SARM gem5 Developers return decodeDataProcReg(machInst); 290410037SARM gem5 Developers } else if (bits(machInst, 24) == 1 && 290510037SARM gem5 Developers bits(machInst, 31, 28) == 0xF) { 290610037SARM gem5 Developers return decodeGem5Ops(machInst); 290710037SARM gem5 Developers } else { 290810037SARM gem5 Developers // bit 27:25=111 290911165SRekai.GonzalezAlberquilla@arm.com switch(decoderFlavour){ 291011165SRekai.GonzalezAlberquilla@arm.com default: 291111165SRekai.GonzalezAlberquilla@arm.com return decodeFpAdvSIMD<GenericDecoder>(machInst); 291211165SRekai.GonzalezAlberquilla@arm.com } 291310037SARM gem5 Developers } 291410037SARM gem5 Developers } 291510037SARM gem5 Developers ''' 291610037SARM gem5 Developers}}; 2917