aarch64.isa revision 13365
112531Sandreas.sandberg@arm.com// Copyright (c) 2011-2018 ARM Limited 210037SARM gem5 Developers// All rights reserved 310037SARM gem5 Developers// 410037SARM gem5 Developers// The license below extends only to copyright in the software and shall 510037SARM gem5 Developers// not be construed as granting a license to any other intellectual 610037SARM gem5 Developers// property including but not limited to intellectual property relating 710037SARM gem5 Developers// to a hardware implementation of the functionality of the software 810037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers// 1310037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1410037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1510037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1610037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1710037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1910037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2010037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2110037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2210037SARM gem5 Developers// this software without specific prior written permission. 2310037SARM gem5 Developers// 2410037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510037SARM gem5 Developers// 3610037SARM gem5 Developers// Authors: Gabe Black 3710037SARM gem5 Developers// Thomas Grocutt 3810037SARM gem5 Developers// Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developersoutput header {{ 4210037SARM gem5 Developersnamespace Aarch64 4310037SARM gem5 Developers{ 4410037SARM gem5 Developers StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 4510037SARM gem5 Developers StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 4610037SARM gem5 Developers StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 4710037SARM gem5 Developers StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 4810037SARM gem5 Developers 4911165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5010037SARM gem5 Developers StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 5110037SARM gem5 Developers StaticInstPtr decodeFp(ExtMachInst machInst); 5211165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5310037SARM gem5 Developers StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 5410037SARM gem5 Developers StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 5510037SARM gem5 Developers 5610037SARM gem5 Developers StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 5710037SARM gem5 Developers} 5810037SARM gem5 Developers}}; 5910037SARM gem5 Developers 6010037SARM gem5 Developersoutput decoder {{ 6110037SARM gem5 Developersnamespace Aarch64 6210037SARM gem5 Developers{ 6310037SARM gem5 Developers StaticInstPtr 6410037SARM gem5 Developers decodeDataProcImm(ExtMachInst machInst) 6510037SARM gem5 Developers { 6610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 6710037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 6810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 6910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 7010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 7110037SARM gem5 Developers 7210037SARM gem5 Developers uint8_t opc = bits(machInst, 30, 29); 7310037SARM gem5 Developers bool sf = bits(machInst, 31); 7410037SARM gem5 Developers bool n = bits(machInst, 22); 7510037SARM gem5 Developers uint8_t immr = bits(machInst, 21, 16); 7610037SARM gem5 Developers uint8_t imms = bits(machInst, 15, 10); 7710037SARM gem5 Developers switch (bits(machInst, 25, 23)) { 7810037SARM gem5 Developers case 0x0: 7910037SARM gem5 Developers case 0x1: 8010037SARM gem5 Developers { 8110037SARM gem5 Developers uint64_t immlo = bits(machInst, 30, 29); 8210037SARM gem5 Developers uint64_t immhi = bits(machInst, 23, 5); 8310037SARM gem5 Developers uint64_t imm = (immlo << 0) | (immhi << 2); 8410037SARM gem5 Developers if (bits(machInst, 31) == 0) 8510337SAndrew.Bardsley@arm.com return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 8610037SARM gem5 Developers else 8710337SAndrew.Bardsley@arm.com return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 8810037SARM gem5 Developers sext<33>(imm << 12)); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers case 0x2: 9110037SARM gem5 Developers case 0x3: 9210037SARM gem5 Developers { 9310037SARM gem5 Developers uint32_t imm12 = bits(machInst, 21, 10); 9410037SARM gem5 Developers uint8_t shift = bits(machInst, 23, 22); 9510037SARM gem5 Developers uint32_t imm; 9610037SARM gem5 Developers if (shift == 0x0) 9710037SARM gem5 Developers imm = imm12 << 0; 9810037SARM gem5 Developers else if (shift == 0x1) 9910037SARM gem5 Developers imm = imm12 << 12; 10010037SARM gem5 Developers else 10110037SARM gem5 Developers return new Unknown64(machInst); 10210037SARM gem5 Developers switch (opc) { 10310037SARM gem5 Developers case 0x0: 10410037SARM gem5 Developers return new AddXImm(machInst, rdsp, rnsp, imm); 10510037SARM gem5 Developers case 0x1: 10610337SAndrew.Bardsley@arm.com return new AddXImmCc(machInst, rdzr, rnsp, imm); 10710037SARM gem5 Developers case 0x2: 10810037SARM gem5 Developers return new SubXImm(machInst, rdsp, rnsp, imm); 10910037SARM gem5 Developers case 0x3: 11010337SAndrew.Bardsley@arm.com return new SubXImmCc(machInst, rdzr, rnsp, imm); 11112595Ssiddhesh.poyarekar@gmail.com default: 11212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 11310037SARM gem5 Developers } 11410037SARM gem5 Developers } 11510037SARM gem5 Developers case 0x4: 11610037SARM gem5 Developers { 11710037SARM gem5 Developers if (!sf && n) 11810037SARM gem5 Developers return new Unknown64(machInst); 11910037SARM gem5 Developers // len = MSB(n:NOT(imms)), len < 1 is undefined. 12010037SARM gem5 Developers uint8_t len = 0; 12110037SARM gem5 Developers if (n) { 12210037SARM gem5 Developers len = 6; 12310037SARM gem5 Developers } else if (imms == 0x3f || imms == 0x3e) { 12410037SARM gem5 Developers return new Unknown64(machInst); 12510037SARM gem5 Developers } else { 12610037SARM gem5 Developers len = findMsbSet(imms ^ 0x3f); 12710037SARM gem5 Developers } 12810037SARM gem5 Developers // Generate r, s, and size. 12910037SARM gem5 Developers uint64_t r = bits(immr, len - 1, 0); 13010037SARM gem5 Developers uint64_t s = bits(imms, len - 1, 0); 13110037SARM gem5 Developers uint8_t size = 1 << len; 13210037SARM gem5 Developers if (s == size - 1) 13310037SARM gem5 Developers return new Unknown64(machInst); 13410037SARM gem5 Developers // Generate the pattern with s 1s, rotated by r, with size bits. 13510037SARM gem5 Developers uint64_t pattern = mask(s + 1); 13610037SARM gem5 Developers if (r) { 13710037SARM gem5 Developers pattern = (pattern >> r) | (pattern << (size - r)); 13810037SARM gem5 Developers pattern &= mask(size); 13910037SARM gem5 Developers } 14010037SARM gem5 Developers uint8_t width = sf ? 64 : 32; 14110037SARM gem5 Developers // Replicate that to fill up the immediate. 14210037SARM gem5 Developers for (unsigned i = 1; i < (width / size); i *= 2) 14310037SARM gem5 Developers pattern |= (pattern << (i * size)); 14410037SARM gem5 Developers uint64_t imm = pattern; 14510037SARM gem5 Developers 14610037SARM gem5 Developers switch (opc) { 14710037SARM gem5 Developers case 0x0: 14810037SARM gem5 Developers return new AndXImm(machInst, rdsp, rn, imm); 14910037SARM gem5 Developers case 0x1: 15010037SARM gem5 Developers return new OrrXImm(machInst, rdsp, rn, imm); 15110037SARM gem5 Developers case 0x2: 15210037SARM gem5 Developers return new EorXImm(machInst, rdsp, rn, imm); 15310037SARM gem5 Developers case 0x3: 15410337SAndrew.Bardsley@arm.com return new AndXImmCc(machInst, rdzr, rn, imm); 15512595Ssiddhesh.poyarekar@gmail.com default: 15612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 15710037SARM gem5 Developers } 15810037SARM gem5 Developers } 15910037SARM gem5 Developers case 0x5: 16010037SARM gem5 Developers { 16110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 16210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 16310037SARM gem5 Developers uint32_t imm16 = bits(machInst, 20, 5); 16410037SARM gem5 Developers uint32_t hw = bits(machInst, 22, 21); 16510037SARM gem5 Developers switch (opc) { 16610037SARM gem5 Developers case 0x0: 16710337SAndrew.Bardsley@arm.com return new Movn(machInst, rdzr, imm16, hw * 16); 16810037SARM gem5 Developers case 0x1: 16910037SARM gem5 Developers return new Unknown64(machInst); 17010037SARM gem5 Developers case 0x2: 17110337SAndrew.Bardsley@arm.com return new Movz(machInst, rdzr, imm16, hw * 16); 17210037SARM gem5 Developers case 0x3: 17310337SAndrew.Bardsley@arm.com return new Movk(machInst, rdzr, imm16, hw * 16); 17412595Ssiddhesh.poyarekar@gmail.com default: 17512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 17610037SARM gem5 Developers } 17710037SARM gem5 Developers } 17810037SARM gem5 Developers case 0x6: 17910037SARM gem5 Developers if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 18010037SARM gem5 Developers return new Unknown64(machInst); 18110037SARM gem5 Developers switch (opc) { 18210037SARM gem5 Developers case 0x0: 18310337SAndrew.Bardsley@arm.com return new Sbfm64(machInst, rdzr, rn, immr, imms); 18410037SARM gem5 Developers case 0x1: 18510337SAndrew.Bardsley@arm.com return new Bfm64(machInst, rdzr, rn, immr, imms); 18610037SARM gem5 Developers case 0x2: 18710337SAndrew.Bardsley@arm.com return new Ubfm64(machInst, rdzr, rn, immr, imms); 18810037SARM gem5 Developers case 0x3: 18910037SARM gem5 Developers return new Unknown64(machInst); 19012595Ssiddhesh.poyarekar@gmail.com default: 19112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 19210037SARM gem5 Developers } 19310037SARM gem5 Developers case 0x7: 19410037SARM gem5 Developers { 19510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 19610037SARM gem5 Developers if (opc || bits(machInst, 21)) 19710037SARM gem5 Developers return new Unknown64(machInst); 19810037SARM gem5 Developers else 19910337SAndrew.Bardsley@arm.com return new Extr64(machInst, rdzr, rn, rm, imms); 20010037SARM gem5 Developers } 20110037SARM gem5 Developers } 20210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case8", machInst); 20310037SARM gem5 Developers } 20410037SARM gem5 Developers} 20510037SARM gem5 Developers}}; 20610037SARM gem5 Developers 20710037SARM gem5 Developersoutput decoder {{ 20810037SARM gem5 Developersnamespace Aarch64 20910037SARM gem5 Developers{ 21010037SARM gem5 Developers StaticInstPtr 21110037SARM gem5 Developers decodeBranchExcSys(ExtMachInst machInst) 21210037SARM gem5 Developers { 21310037SARM gem5 Developers switch (bits(machInst, 30, 29)) { 21410037SARM gem5 Developers case 0x0: 21510037SARM gem5 Developers { 21610037SARM gem5 Developers int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 21710037SARM gem5 Developers if (bits(machInst, 31) == 0) 21810037SARM gem5 Developers return new B64(machInst, imm); 21910037SARM gem5 Developers else 22010037SARM gem5 Developers return new Bl64(machInst, imm); 22110037SARM gem5 Developers } 22210037SARM gem5 Developers case 0x1: 22310037SARM gem5 Developers { 22410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 22510037SARM gem5 Developers if (bits(machInst, 25) == 0) { 22610037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 22710037SARM gem5 Developers if (bits(machInst, 24) == 0) 22810037SARM gem5 Developers return new Cbz64(machInst, imm, rt); 22910037SARM gem5 Developers else 23010037SARM gem5 Developers return new Cbnz64(machInst, imm, rt); 23110037SARM gem5 Developers } else { 23210037SARM gem5 Developers uint64_t bitmask = 0x1; 23310037SARM gem5 Developers bitmask <<= bits(machInst, 23, 19); 23410037SARM gem5 Developers int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 23510037SARM gem5 Developers if (bits(machInst, 31)) 23610037SARM gem5 Developers bitmask <<= 32; 23710037SARM gem5 Developers if (bits(machInst, 24) == 0) 23810037SARM gem5 Developers return new Tbz64(machInst, bitmask, imm, rt); 23910037SARM gem5 Developers else 24010037SARM gem5 Developers return new Tbnz64(machInst, bitmask, imm, rt); 24110037SARM gem5 Developers } 24210037SARM gem5 Developers } 24310037SARM gem5 Developers case 0x2: 24410037SARM gem5 Developers // bit 30:26=10101 24510037SARM gem5 Developers if (bits(machInst, 31) == 0) { 24610037SARM gem5 Developers if (bits(machInst, 25, 24) || bits(machInst, 4)) 24710037SARM gem5 Developers return new Unknown64(machInst); 24810037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 24910037SARM gem5 Developers ConditionCode condCode = 25010037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 25110037SARM gem5 Developers return new BCond64(machInst, imm, condCode); 25210037SARM gem5 Developers } else if (bits(machInst, 25, 24) == 0x0) { 25312538Sgiacomo.travaglini@arm.com 25410037SARM gem5 Developers if (bits(machInst, 4, 2)) 25510037SARM gem5 Developers return new Unknown64(machInst); 25612538Sgiacomo.travaglini@arm.com 25712538Sgiacomo.travaglini@arm.com auto imm16 = bits(machInst, 20, 5); 25810037SARM gem5 Developers uint8_t decVal = (bits(machInst, 1, 0) << 0) | 25910037SARM gem5 Developers (bits(machInst, 23, 21) << 2); 26012538Sgiacomo.travaglini@arm.com 26110037SARM gem5 Developers switch (decVal) { 26210037SARM gem5 Developers case 0x01: 26312538Sgiacomo.travaglini@arm.com return new Svc64(machInst, imm16); 26410037SARM gem5 Developers case 0x02: 26512538Sgiacomo.travaglini@arm.com return new Hvc64(machInst, imm16); 26610037SARM gem5 Developers case 0x03: 26712538Sgiacomo.travaglini@arm.com return new Smc64(machInst, imm16); 26810037SARM gem5 Developers case 0x04: 26912538Sgiacomo.travaglini@arm.com return new Brk64(machInst, imm16); 27010037SARM gem5 Developers case 0x08: 27112538Sgiacomo.travaglini@arm.com return new Hlt64(machInst, imm16); 27210037SARM gem5 Developers case 0x15: 27310037SARM gem5 Developers return new FailUnimplemented("dcps1", machInst); 27410037SARM gem5 Developers case 0x16: 27510037SARM gem5 Developers return new FailUnimplemented("dcps2", machInst); 27610037SARM gem5 Developers case 0x17: 27710037SARM gem5 Developers return new FailUnimplemented("dcps3", machInst); 27810037SARM gem5 Developers default: 27910037SARM gem5 Developers return new Unknown64(machInst); 28010037SARM gem5 Developers } 28110037SARM gem5 Developers } else if (bits(machInst, 25, 22) == 0x4) { 28210037SARM gem5 Developers // bit 31:22=1101010100 28310037SARM gem5 Developers bool l = bits(machInst, 21); 28410037SARM gem5 Developers uint8_t op0 = bits(machInst, 20, 19); 28510037SARM gem5 Developers uint8_t op1 = bits(machInst, 18, 16); 28610037SARM gem5 Developers uint8_t crn = bits(machInst, 15, 12); 28710037SARM gem5 Developers uint8_t crm = bits(machInst, 11, 8); 28810037SARM gem5 Developers uint8_t op2 = bits(machInst, 7, 5); 28910037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 29010037SARM gem5 Developers switch (op0) { 29110037SARM gem5 Developers case 0x0: 29210037SARM gem5 Developers if (rt != 0x1f || l) 29310037SARM gem5 Developers return new Unknown64(machInst); 29410037SARM gem5 Developers if (crn == 0x2 && op1 == 0x3) { 29513354Sciro.santilli@arm.com switch (crm) { 29610037SARM gem5 Developers case 0x0: 29713354Sciro.santilli@arm.com switch (op2) { 29813354Sciro.santilli@arm.com case 0x0: 29913354Sciro.santilli@arm.com return new NopInst(machInst); 30013354Sciro.santilli@arm.com case 0x1: 30113354Sciro.santilli@arm.com return new YieldInst(machInst); 30213354Sciro.santilli@arm.com case 0x2: 30313354Sciro.santilli@arm.com return new WfeInst(machInst); 30413354Sciro.santilli@arm.com case 0x3: 30513354Sciro.santilli@arm.com return new WfiInst(machInst); 30613354Sciro.santilli@arm.com case 0x4: 30713354Sciro.santilli@arm.com return new SevInst(machInst); 30813354Sciro.santilli@arm.com case 0x5: 30913354Sciro.santilli@arm.com return new SevlInst(machInst); 31013354Sciro.santilli@arm.com } 31113354Sciro.santilli@arm.com break; 31210037SARM gem5 Developers case 0x1: 31313354Sciro.santilli@arm.com switch (op2) { 31413354Sciro.santilli@arm.com case 0x0: 31513354Sciro.santilli@arm.com return new WarnUnimplemented( 31613354Sciro.santilli@arm.com "pacia", machInst); 31713354Sciro.santilli@arm.com case 0x2: 31813354Sciro.santilli@arm.com return new WarnUnimplemented( 31913354Sciro.santilli@arm.com "pacib", machInst); 32013354Sciro.santilli@arm.com case 0x4: 32113354Sciro.santilli@arm.com return new WarnUnimplemented( 32213354Sciro.santilli@arm.com "autia", machInst); 32313354Sciro.santilli@arm.com case 0x6: 32413354Sciro.santilli@arm.com return new WarnUnimplemented( 32513354Sciro.santilli@arm.com "autib", machInst); 32613354Sciro.santilli@arm.com } 32713354Sciro.santilli@arm.com break; 32810037SARM gem5 Developers case 0x2: 32913354Sciro.santilli@arm.com switch (op2) { 33013354Sciro.santilli@arm.com case 0x0: 33113354Sciro.santilli@arm.com return new WarnUnimplemented( 33213354Sciro.santilli@arm.com "esb", machInst); 33313354Sciro.santilli@arm.com case 0x1: 33413354Sciro.santilli@arm.com return new WarnUnimplemented( 33513354Sciro.santilli@arm.com "psb csync", machInst); 33613354Sciro.santilli@arm.com case 0x2: 33713354Sciro.santilli@arm.com return new WarnUnimplemented( 33813354Sciro.santilli@arm.com "tsb csync", machInst); 33913354Sciro.santilli@arm.com case 0x4: 34013354Sciro.santilli@arm.com return new WarnUnimplemented( 34113354Sciro.santilli@arm.com "csdb", machInst); 34213354Sciro.santilli@arm.com } 34313354Sciro.santilli@arm.com break; 34410037SARM gem5 Developers case 0x3: 34513354Sciro.santilli@arm.com switch (op2) { 34613354Sciro.santilli@arm.com case 0x0: 34713354Sciro.santilli@arm.com case 0x1: 34813354Sciro.santilli@arm.com return new WarnUnimplemented( 34913354Sciro.santilli@arm.com "pacia", machInst); 35013354Sciro.santilli@arm.com case 0x2: 35113354Sciro.santilli@arm.com case 0x3: 35213354Sciro.santilli@arm.com return new WarnUnimplemented( 35313354Sciro.santilli@arm.com "pacib", machInst); 35413354Sciro.santilli@arm.com case 0x4: 35513354Sciro.santilli@arm.com case 0x5: 35613354Sciro.santilli@arm.com return new WarnUnimplemented( 35713354Sciro.santilli@arm.com "autia", machInst); 35813354Sciro.santilli@arm.com case 0x6: 35913354Sciro.santilli@arm.com case 0x7: 36013354Sciro.santilli@arm.com return new WarnUnimplemented( 36113354Sciro.santilli@arm.com "autib", machInst); 36213354Sciro.santilli@arm.com } 36313354Sciro.santilli@arm.com break; 36410037SARM gem5 Developers case 0x4: 36513354Sciro.santilli@arm.com switch (op2 & 0x1) { 36613354Sciro.santilli@arm.com case 0x0: 36713354Sciro.santilli@arm.com return new WarnUnimplemented( 36813354Sciro.santilli@arm.com "bti", machInst); 36913354Sciro.santilli@arm.com } 37013354Sciro.santilli@arm.com break; 37110037SARM gem5 Developers } 37213355Sciro.santilli@arm.com return new WarnUnimplemented( 37313355Sciro.santilli@arm.com "unallocated_hint", machInst); 37410037SARM gem5 Developers } else if (crn == 0x3 && op1 == 0x3) { 37510037SARM gem5 Developers switch (op2) { 37610037SARM gem5 Developers case 0x2: 37710037SARM gem5 Developers return new Clrex64(machInst); 37810037SARM gem5 Developers case 0x4: 37910037SARM gem5 Developers return new Dsb64(machInst); 38010037SARM gem5 Developers case 0x5: 38110037SARM gem5 Developers return new Dmb64(machInst); 38210037SARM gem5 Developers case 0x6: 38310037SARM gem5 Developers return new Isb64(machInst); 38410037SARM gem5 Developers default: 38510037SARM gem5 Developers return new Unknown64(machInst); 38610037SARM gem5 Developers } 38710037SARM gem5 Developers } else if (crn == 0x4) { 38810037SARM gem5 Developers // MSR immediate 38910037SARM gem5 Developers switch (op1 << 3 | op2) { 39010037SARM gem5 Developers case 0x5: 39110037SARM gem5 Developers // SP 39210037SARM gem5 Developers return new MsrSP64(machInst, 39310037SARM gem5 Developers (IntRegIndex) MISCREG_SPSEL, 39410037SARM gem5 Developers INTREG_ZERO, 39510037SARM gem5 Developers crm & 0x1); 39610037SARM gem5 Developers case 0x1e: 39710037SARM gem5 Developers // DAIFSet 39810037SARM gem5 Developers return new MsrDAIFSet64( 39910037SARM gem5 Developers machInst, 40010037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 40110037SARM gem5 Developers INTREG_ZERO, 40210037SARM gem5 Developers crm); 40310037SARM gem5 Developers case 0x1f: 40410037SARM gem5 Developers // DAIFClr 40510037SARM gem5 Developers return new MsrDAIFClr64( 40610037SARM gem5 Developers machInst, 40710037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 40810037SARM gem5 Developers INTREG_ZERO, 40910037SARM gem5 Developers crm); 41010037SARM gem5 Developers default: 41110037SARM gem5 Developers return new Unknown64(machInst); 41210037SARM gem5 Developers } 41310037SARM gem5 Developers } else { 41410037SARM gem5 Developers return new Unknown64(machInst); 41510037SARM gem5 Developers } 41610037SARM gem5 Developers break; 41710037SARM gem5 Developers case 0x1: 41810037SARM gem5 Developers case 0x2: 41910037SARM gem5 Developers case 0x3: 42010037SARM gem5 Developers { 42110037SARM gem5 Developers // bit 31:22=1101010100, 20:19=11 42210037SARM gem5 Developers bool read = l; 42310037SARM gem5 Developers MiscRegIndex miscReg = 42410037SARM gem5 Developers decodeAArch64SysReg(op0, op1, crn, crm, op2); 42510037SARM gem5 Developers if (read) { 42610037SARM gem5 Developers if ((miscReg == MISCREG_DC_CIVAC_Xt) || 42710037SARM gem5 Developers (miscReg == MISCREG_DC_CVAC_Xt) || 42812359Snikos.nikoleris@arm.com (miscReg == MISCREG_DC_IVAC_Xt) || 42910037SARM gem5 Developers (miscReg == MISCREG_DC_ZVA_Xt)) { 43010037SARM gem5 Developers return new Unknown64(machInst); 43110037SARM gem5 Developers } 43210037SARM gem5 Developers } 43310037SARM gem5 Developers // Check for invalid registers 43410037SARM gem5 Developers if (miscReg == MISCREG_UNKNOWN) { 43512673Sgiacomo.travaglini@arm.com auto full_mnemonic = 43612673Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 43712673Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 43812673Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 43912673Sgiacomo.travaglini@arm.com 44012673Sgiacomo.travaglini@arm.com return new FailUnimplemented(read ? "mrs" : "msr", 44112673Sgiacomo.travaglini@arm.com machInst, full_mnemonic); 44212673Sgiacomo.travaglini@arm.com 44312714Sgiacomo.travaglini@arm.com } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { 44412714Sgiacomo.travaglini@arm.com auto full_mnemonic = 44512714Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 44612714Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 44712714Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 44812714Sgiacomo.travaglini@arm.com 44913365Sgiacomo.travaglini@arm.com uint32_t iss = msrMrs64IssBuild( 45013365Sgiacomo.travaglini@arm.com read, op0, op1, crn, crm, op2, rt); 45113365Sgiacomo.travaglini@arm.com 45213365Sgiacomo.travaglini@arm.com return new MiscRegImplDefined64( 45313365Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 45413365Sgiacomo.travaglini@arm.com machInst, miscReg, read, iss, full_mnemonic, 45513365Sgiacomo.travaglini@arm.com miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]); 45612714Sgiacomo.travaglini@arm.com 45710037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 45810037SARM gem5 Developers if (miscReg == MISCREG_NZCV) { 45910037SARM gem5 Developers if (read) 46010037SARM gem5 Developers return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 46110037SARM gem5 Developers else 46210037SARM gem5 Developers return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 46310037SARM gem5 Developers } 46410037SARM gem5 Developers uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 46510506SAli.Saidi@ARM.com if (read) { 46612280Sgiacomo.travaglini@arm.com StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); 46710506SAli.Saidi@ARM.com if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 46810506SAli.Saidi@ARM.com si->setFlag(StaticInst::IsUnverifiable); 46910506SAli.Saidi@ARM.com return si; 47012280Sgiacomo.travaglini@arm.com } else { 47112359Snikos.nikoleris@arm.com switch (miscReg) { 47212359Snikos.nikoleris@arm.com case MISCREG_DC_ZVA_Xt: 47312359Snikos.nikoleris@arm.com return new Dczva(machInst, rt, miscReg, iss); 47412359Snikos.nikoleris@arm.com case MISCREG_DC_CVAU_Xt: 47512359Snikos.nikoleris@arm.com return new Dccvau(machInst, rt, miscReg, iss); 47612359Snikos.nikoleris@arm.com case MISCREG_DC_CVAC_Xt: 47712359Snikos.nikoleris@arm.com return new Dccvac(machInst, rt, miscReg, iss); 47812359Snikos.nikoleris@arm.com case MISCREG_DC_CIVAC_Xt: 47912359Snikos.nikoleris@arm.com return new Dccivac(machInst, rt, miscReg, iss); 48012359Snikos.nikoleris@arm.com case MISCREG_DC_IVAC_Xt: 48112359Snikos.nikoleris@arm.com return new Dcivac(machInst, rt, miscReg, iss); 48212359Snikos.nikoleris@arm.com default: 48312359Snikos.nikoleris@arm.com return new Msr64(machInst, miscReg, rt, iss); 48412359Snikos.nikoleris@arm.com } 48512280Sgiacomo.travaglini@arm.com } 48610037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 48710037SARM gem5 Developers std::string full_mnem = csprintf("%s %s", 48810037SARM gem5 Developers read ? "mrs" : "msr", miscRegName[miscReg]); 48910037SARM gem5 Developers return new WarnUnimplemented(read ? "mrs" : "msr", 49010037SARM gem5 Developers machInst, full_mnem); 49110037SARM gem5 Developers } else { 49210173SMitchell.Hayenga@ARM.com return new FailUnimplemented(read ? "mrs" : "msr", 49310173SMitchell.Hayenga@ARM.com machInst, 49410173SMitchell.Hayenga@ARM.com csprintf("%s %s", 49510173SMitchell.Hayenga@ARM.com read ? "mrs" : "msr", 49610173SMitchell.Hayenga@ARM.com miscRegName[miscReg])); 49710037SARM gem5 Developers } 49810037SARM gem5 Developers } 49910037SARM gem5 Developers break; 50012595Ssiddhesh.poyarekar@gmail.com default: 50112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 50210037SARM gem5 Developers } 50310037SARM gem5 Developers } else if (bits(machInst, 25) == 0x1) { 50410037SARM gem5 Developers uint8_t opc = bits(machInst, 24, 21); 50510037SARM gem5 Developers uint8_t op2 = bits(machInst, 20, 16); 50610037SARM gem5 Developers uint8_t op3 = bits(machInst, 15, 10); 50710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 50810037SARM gem5 Developers uint8_t op4 = bits(machInst, 4, 0); 50910037SARM gem5 Developers if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 51010037SARM gem5 Developers return new Unknown64(machInst); 51110037SARM gem5 Developers switch (opc) { 51210037SARM gem5 Developers case 0x0: 51310037SARM gem5 Developers return new Br64(machInst, rn); 51410037SARM gem5 Developers case 0x1: 51510037SARM gem5 Developers return new Blr64(machInst, rn); 51610037SARM gem5 Developers case 0x2: 51710037SARM gem5 Developers return new Ret64(machInst, rn); 51810037SARM gem5 Developers case 0x4: 51910037SARM gem5 Developers if (rn != 0x1f) 52010037SARM gem5 Developers return new Unknown64(machInst); 52110037SARM gem5 Developers return new Eret64(machInst); 52210037SARM gem5 Developers case 0x5: 52310037SARM gem5 Developers if (rn != 0x1f) 52410037SARM gem5 Developers return new Unknown64(machInst); 52510037SARM gem5 Developers return new FailUnimplemented("dret", machInst); 52612595Ssiddhesh.poyarekar@gmail.com default: 52712595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 52810037SARM gem5 Developers } 52910037SARM gem5 Developers } 53012595Ssiddhesh.poyarekar@gmail.com M5_FALLTHROUGH; 53110037SARM gem5 Developers default: 53210037SARM gem5 Developers return new Unknown64(machInst); 53310037SARM gem5 Developers } 53410037SARM gem5 Developers return new FailUnimplemented("Unhandled Case7", machInst); 53510037SARM gem5 Developers } 53610037SARM gem5 Developers} 53710037SARM gem5 Developers}}; 53810037SARM gem5 Developers 53910037SARM gem5 Developersoutput decoder {{ 54010037SARM gem5 Developersnamespace Aarch64 54110037SARM gem5 Developers{ 54210037SARM gem5 Developers StaticInstPtr 54310037SARM gem5 Developers decodeLoadsStores(ExtMachInst machInst) 54410037SARM gem5 Developers { 54510037SARM gem5 Developers // bit 27,25=10 54610037SARM gem5 Developers switch (bits(machInst, 29, 28)) { 54710037SARM gem5 Developers case 0x0: 54810037SARM gem5 Developers if (bits(machInst, 26) == 0) { 54910037SARM gem5 Developers if (bits(machInst, 24) != 0) 55010037SARM gem5 Developers return new Unknown64(machInst); 55110037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 55210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 55310037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 55410037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 55510037SARM gem5 Developers IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 55610037SARM gem5 Developers uint8_t opc = (bits(machInst, 15) << 0) | 55710037SARM gem5 Developers (bits(machInst, 23, 21) << 1); 55810037SARM gem5 Developers uint8_t size = bits(machInst, 31, 30); 55910037SARM gem5 Developers switch (opc) { 56010037SARM gem5 Developers case 0x0: 56110037SARM gem5 Developers switch (size) { 56210037SARM gem5 Developers case 0x0: 56310037SARM gem5 Developers return new STXRB64(machInst, rt, rnsp, rs); 56410037SARM gem5 Developers case 0x1: 56510037SARM gem5 Developers return new STXRH64(machInst, rt, rnsp, rs); 56610037SARM gem5 Developers case 0x2: 56710037SARM gem5 Developers return new STXRW64(machInst, rt, rnsp, rs); 56810037SARM gem5 Developers case 0x3: 56910037SARM gem5 Developers return new STXRX64(machInst, rt, rnsp, rs); 57012595Ssiddhesh.poyarekar@gmail.com default: 57112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 57210037SARM gem5 Developers } 57310037SARM gem5 Developers case 0x1: 57410037SARM gem5 Developers switch (size) { 57510037SARM gem5 Developers case 0x0: 57610037SARM gem5 Developers return new STLXRB64(machInst, rt, rnsp, rs); 57710037SARM gem5 Developers case 0x1: 57810037SARM gem5 Developers return new STLXRH64(machInst, rt, rnsp, rs); 57910037SARM gem5 Developers case 0x2: 58010037SARM gem5 Developers return new STLXRW64(machInst, rt, rnsp, rs); 58110037SARM gem5 Developers case 0x3: 58210037SARM gem5 Developers return new STLXRX64(machInst, rt, rnsp, rs); 58312595Ssiddhesh.poyarekar@gmail.com default: 58412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 58510037SARM gem5 Developers } 58610037SARM gem5 Developers case 0x2: 58710037SARM gem5 Developers switch (size) { 58810037SARM gem5 Developers case 0x0: 58910037SARM gem5 Developers case 0x1: 59010037SARM gem5 Developers return new Unknown64(machInst); 59110037SARM gem5 Developers case 0x2: 59210037SARM gem5 Developers return new STXPW64(machInst, rs, rt, rt2, rnsp); 59310037SARM gem5 Developers case 0x3: 59410037SARM gem5 Developers return new STXPX64(machInst, rs, rt, rt2, rnsp); 59512595Ssiddhesh.poyarekar@gmail.com default: 59612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 59710037SARM gem5 Developers } 59810037SARM gem5 Developers 59910037SARM gem5 Developers case 0x3: 60010037SARM gem5 Developers switch (size) { 60110037SARM gem5 Developers case 0x0: 60210037SARM gem5 Developers case 0x1: 60310037SARM gem5 Developers return new Unknown64(machInst); 60410037SARM gem5 Developers case 0x2: 60510037SARM gem5 Developers return new STLXPW64(machInst, rs, rt, rt2, rnsp); 60610037SARM gem5 Developers case 0x3: 60710037SARM gem5 Developers return new STLXPX64(machInst, rs, rt, rt2, rnsp); 60812595Ssiddhesh.poyarekar@gmail.com default: 60912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 61010037SARM gem5 Developers } 61110037SARM gem5 Developers 61210037SARM gem5 Developers case 0x4: 61310037SARM gem5 Developers switch (size) { 61410037SARM gem5 Developers case 0x0: 61510037SARM gem5 Developers return new LDXRB64(machInst, rt, rnsp, rs); 61610037SARM gem5 Developers case 0x1: 61710037SARM gem5 Developers return new LDXRH64(machInst, rt, rnsp, rs); 61810037SARM gem5 Developers case 0x2: 61910037SARM gem5 Developers return new LDXRW64(machInst, rt, rnsp, rs); 62010037SARM gem5 Developers case 0x3: 62110037SARM gem5 Developers return new LDXRX64(machInst, rt, rnsp, rs); 62212595Ssiddhesh.poyarekar@gmail.com default: 62312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 62410037SARM gem5 Developers } 62510037SARM gem5 Developers case 0x5: 62610037SARM gem5 Developers switch (size) { 62710037SARM gem5 Developers case 0x0: 62810037SARM gem5 Developers return new LDAXRB64(machInst, rt, rnsp, rs); 62910037SARM gem5 Developers case 0x1: 63010037SARM gem5 Developers return new LDAXRH64(machInst, rt, rnsp, rs); 63110037SARM gem5 Developers case 0x2: 63210037SARM gem5 Developers return new LDAXRW64(machInst, rt, rnsp, rs); 63310037SARM gem5 Developers case 0x3: 63410037SARM gem5 Developers return new LDAXRX64(machInst, rt, rnsp, rs); 63512595Ssiddhesh.poyarekar@gmail.com default: 63612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 63710037SARM gem5 Developers } 63810037SARM gem5 Developers case 0x6: 63910037SARM gem5 Developers switch (size) { 64010037SARM gem5 Developers case 0x0: 64110037SARM gem5 Developers case 0x1: 64210037SARM gem5 Developers return new Unknown64(machInst); 64310037SARM gem5 Developers case 0x2: 64410037SARM gem5 Developers return new LDXPW64(machInst, rt, rt2, rnsp); 64510037SARM gem5 Developers case 0x3: 64610037SARM gem5 Developers return new LDXPX64(machInst, rt, rt2, rnsp); 64712595Ssiddhesh.poyarekar@gmail.com default: 64812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 64910037SARM gem5 Developers } 65010037SARM gem5 Developers 65110037SARM gem5 Developers case 0x7: 65210037SARM gem5 Developers switch (size) { 65310037SARM gem5 Developers case 0x0: 65410037SARM gem5 Developers case 0x1: 65510037SARM gem5 Developers return new Unknown64(machInst); 65610037SARM gem5 Developers case 0x2: 65710037SARM gem5 Developers return new LDAXPW64(machInst, rt, rt2, rnsp); 65810037SARM gem5 Developers case 0x3: 65910037SARM gem5 Developers return new LDAXPX64(machInst, rt, rt2, rnsp); 66012595Ssiddhesh.poyarekar@gmail.com default: 66112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 66210037SARM gem5 Developers } 66310037SARM gem5 Developers 66410037SARM gem5 Developers case 0x9: 66510037SARM gem5 Developers switch (size) { 66610037SARM gem5 Developers case 0x0: 66710037SARM gem5 Developers return new STLRB64(machInst, rt, rnsp); 66810037SARM gem5 Developers case 0x1: 66910037SARM gem5 Developers return new STLRH64(machInst, rt, rnsp); 67010037SARM gem5 Developers case 0x2: 67110037SARM gem5 Developers return new STLRW64(machInst, rt, rnsp); 67210037SARM gem5 Developers case 0x3: 67310037SARM gem5 Developers return new STLRX64(machInst, rt, rnsp); 67412595Ssiddhesh.poyarekar@gmail.com default: 67512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 67610037SARM gem5 Developers } 67710037SARM gem5 Developers case 0xd: 67810037SARM gem5 Developers switch (size) { 67910037SARM gem5 Developers case 0x0: 68010037SARM gem5 Developers return new LDARB64(machInst, rt, rnsp); 68110037SARM gem5 Developers case 0x1: 68210037SARM gem5 Developers return new LDARH64(machInst, rt, rnsp); 68310037SARM gem5 Developers case 0x2: 68410037SARM gem5 Developers return new LDARW64(machInst, rt, rnsp); 68510037SARM gem5 Developers case 0x3: 68610037SARM gem5 Developers return new LDARX64(machInst, rt, rnsp); 68712595Ssiddhesh.poyarekar@gmail.com default: 68812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 68910037SARM gem5 Developers } 69010037SARM gem5 Developers default: 69110037SARM gem5 Developers return new Unknown64(machInst); 69210037SARM gem5 Developers } 69310037SARM gem5 Developers } else if (bits(machInst, 31)) { 69410037SARM gem5 Developers return new Unknown64(machInst); 69510037SARM gem5 Developers } else { 69610037SARM gem5 Developers return decodeNeonMem(machInst); 69710037SARM gem5 Developers } 69810037SARM gem5 Developers case 0x1: 69910037SARM gem5 Developers { 70010037SARM gem5 Developers if (bits(machInst, 24) != 0) 70110037SARM gem5 Developers return new Unknown64(machInst); 70210037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 26) << 0) | 70310037SARM gem5 Developers (bits(machInst, 31, 30) << 1); 70410037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 70510037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 70610037SARM gem5 Developers switch (switchVal) { 70710037SARM gem5 Developers case 0x0: 70810037SARM gem5 Developers return new LDRWL64_LIT(machInst, rt, imm); 70910037SARM gem5 Developers case 0x1: 71010037SARM gem5 Developers return new LDRSFP64_LIT(machInst, rt, imm); 71110037SARM gem5 Developers case 0x2: 71210037SARM gem5 Developers return new LDRXL64_LIT(machInst, rt, imm); 71310037SARM gem5 Developers case 0x3: 71410037SARM gem5 Developers return new LDRDFP64_LIT(machInst, rt, imm); 71510037SARM gem5 Developers case 0x4: 71610037SARM gem5 Developers return new LDRSWL64_LIT(machInst, rt, imm); 71710037SARM gem5 Developers case 0x5: 71810037SARM gem5 Developers return new BigFpMemLit("ldr", machInst, rt, imm); 71910037SARM gem5 Developers case 0x6: 72010037SARM gem5 Developers return new PRFM64_LIT(machInst, rt, imm); 72110037SARM gem5 Developers default: 72210037SARM gem5 Developers return new Unknown64(machInst); 72310037SARM gem5 Developers } 72410037SARM gem5 Developers } 72510037SARM gem5 Developers case 0x2: 72610037SARM gem5 Developers { 72710037SARM gem5 Developers uint8_t opc = bits(machInst, 31, 30); 72810037SARM gem5 Developers if (opc >= 3) 72910037SARM gem5 Developers return new Unknown64(machInst); 73010037SARM gem5 Developers uint32_t size = 0; 73110037SARM gem5 Developers bool fp = bits(machInst, 26); 73210037SARM gem5 Developers bool load = bits(machInst, 22); 73310037SARM gem5 Developers if (fp) { 73410037SARM gem5 Developers size = 4 << opc; 73510037SARM gem5 Developers } else { 73610037SARM gem5 Developers if ((opc == 1) && !load) 73710037SARM gem5 Developers return new Unknown64(machInst); 73810037SARM gem5 Developers size = (opc == 0 || opc == 1) ? 4 : 8; 73910037SARM gem5 Developers } 74010037SARM gem5 Developers uint8_t type = bits(machInst, 24, 23); 74110037SARM gem5 Developers int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 74210037SARM gem5 Developers 74310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 74410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 74510037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 74610037SARM gem5 Developers 74710037SARM gem5 Developers bool noAlloc = (type == 0); 74810037SARM gem5 Developers bool signExt = !noAlloc && !fp && opc == 1; 74910037SARM gem5 Developers PairMemOp::AddrMode mode; 75010037SARM gem5 Developers const char *mnemonic = NULL; 75110037SARM gem5 Developers switch (type) { 75210037SARM gem5 Developers case 0x0: 75310037SARM gem5 Developers case 0x2: 75410037SARM gem5 Developers mode = PairMemOp::AddrMd_Offset; 75510037SARM gem5 Developers break; 75610037SARM gem5 Developers case 0x1: 75710037SARM gem5 Developers mode = PairMemOp::AddrMd_PostIndex; 75810037SARM gem5 Developers break; 75910037SARM gem5 Developers case 0x3: 76010037SARM gem5 Developers mode = PairMemOp::AddrMd_PreIndex; 76110037SARM gem5 Developers break; 76210037SARM gem5 Developers default: 76310037SARM gem5 Developers return new Unknown64(machInst); 76410037SARM gem5 Developers } 76510037SARM gem5 Developers if (load) { 76610037SARM gem5 Developers if (noAlloc) 76710037SARM gem5 Developers mnemonic = "ldnp"; 76810037SARM gem5 Developers else if (signExt) 76910037SARM gem5 Developers mnemonic = "ldpsw"; 77010037SARM gem5 Developers else 77110037SARM gem5 Developers mnemonic = "ldp"; 77210037SARM gem5 Developers } else { 77310037SARM gem5 Developers if (noAlloc) 77410037SARM gem5 Developers mnemonic = "stnp"; 77510037SARM gem5 Developers else 77610037SARM gem5 Developers mnemonic = "stp"; 77710037SARM gem5 Developers } 77810037SARM gem5 Developers 77910037SARM gem5 Developers return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 78010037SARM gem5 Developers signExt, false, false, imm, mode, rn, rt, rt2); 78110037SARM gem5 Developers } 78210037SARM gem5 Developers // bit 29:27=111, 25=0 78310037SARM gem5 Developers case 0x3: 78410037SARM gem5 Developers { 78510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 78610037SARM gem5 Developers (bits(machInst, 26) << 2) | 78710037SARM gem5 Developers (bits(machInst, 31, 30) << 3); 78810037SARM gem5 Developers if (bits(machInst, 24) == 1) { 78910037SARM gem5 Developers uint64_t imm12 = bits(machInst, 21, 10); 79010037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 79110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 79210037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 79310037SARM gem5 Developers switch (switchVal) { 79410037SARM gem5 Developers case 0x00: 79510037SARM gem5 Developers return new STRB64_IMM(machInst, rt, rnsp, imm12); 79610037SARM gem5 Developers case 0x01: 79710037SARM gem5 Developers return new LDRB64_IMM(machInst, rt, rnsp, imm12); 79810037SARM gem5 Developers case 0x02: 79910037SARM gem5 Developers return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 80010037SARM gem5 Developers case 0x03: 80110037SARM gem5 Developers return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 80210037SARM gem5 Developers case 0x04: 80310037SARM gem5 Developers return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 80410037SARM gem5 Developers case 0x05: 80510037SARM gem5 Developers return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 80610037SARM gem5 Developers case 0x06: 80710037SARM gem5 Developers return new BigFpMemImm("str", machInst, false, 80810037SARM gem5 Developers rt, rnsp, imm12 << 4); 80910037SARM gem5 Developers case 0x07: 81010037SARM gem5 Developers return new BigFpMemImm("ldr", machInst, true, 81110037SARM gem5 Developers rt, rnsp, imm12 << 4); 81210037SARM gem5 Developers case 0x08: 81310037SARM gem5 Developers return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 81410037SARM gem5 Developers case 0x09: 81510037SARM gem5 Developers return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 81610037SARM gem5 Developers case 0x0a: 81710037SARM gem5 Developers return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 81810037SARM gem5 Developers case 0x0b: 81910037SARM gem5 Developers return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 82010037SARM gem5 Developers case 0x0c: 82110037SARM gem5 Developers return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 82210037SARM gem5 Developers case 0x0d: 82310037SARM gem5 Developers return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 82410037SARM gem5 Developers case 0x10: 82510037SARM gem5 Developers return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 82610037SARM gem5 Developers case 0x11: 82710037SARM gem5 Developers return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 82810037SARM gem5 Developers case 0x12: 82910037SARM gem5 Developers return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 83010037SARM gem5 Developers case 0x14: 83110037SARM gem5 Developers return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 83210037SARM gem5 Developers case 0x15: 83310037SARM gem5 Developers return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 83410037SARM gem5 Developers case 0x18: 83510037SARM gem5 Developers return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 83610037SARM gem5 Developers case 0x19: 83710037SARM gem5 Developers return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 83810037SARM gem5 Developers case 0x1a: 83910037SARM gem5 Developers return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 84010037SARM gem5 Developers case 0x1c: 84110037SARM gem5 Developers return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 84210037SARM gem5 Developers case 0x1d: 84310037SARM gem5 Developers return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 84410037SARM gem5 Developers default: 84510037SARM gem5 Developers return new Unknown64(machInst); 84610037SARM gem5 Developers } 84710037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 84812856Sgiacomo.gabrielli@arm.com uint8_t group = bits(machInst, 11, 10); 84912856Sgiacomo.gabrielli@arm.com switch (group) { 85012856Sgiacomo.gabrielli@arm.com case 0x0: 85112856Sgiacomo.gabrielli@arm.com { 85212856Sgiacomo.gabrielli@arm.com if ((switchVal & 0x7) == 0x2 && 85312856Sgiacomo.gabrielli@arm.com bits(machInst, 20, 12) == 0x1fc) { 85412856Sgiacomo.gabrielli@arm.com IntRegIndex rt = (IntRegIndex)(uint32_t) 85512856Sgiacomo.gabrielli@arm.com bits(machInst, 4, 0); 85612856Sgiacomo.gabrielli@arm.com IntRegIndex rn = (IntRegIndex)(uint32_t) 85712856Sgiacomo.gabrielli@arm.com bits(machInst, 9, 5); 85812856Sgiacomo.gabrielli@arm.com IntRegIndex rnsp = makeSP(rn); 85912856Sgiacomo.gabrielli@arm.com uint8_t size = bits(machInst, 31, 30); 86012856Sgiacomo.gabrielli@arm.com switch (size) { 86112856Sgiacomo.gabrielli@arm.com case 0x0: 86212856Sgiacomo.gabrielli@arm.com return new LDAPRB64(machInst, rt, rnsp); 86312856Sgiacomo.gabrielli@arm.com case 0x1: 86412856Sgiacomo.gabrielli@arm.com return new LDAPRH64(machInst, rt, rnsp); 86512856Sgiacomo.gabrielli@arm.com case 0x2: 86612856Sgiacomo.gabrielli@arm.com return new LDAPRW64(machInst, rt, rnsp); 86712856Sgiacomo.gabrielli@arm.com case 0x3: 86812856Sgiacomo.gabrielli@arm.com return new LDAPRX64(machInst, rt, rnsp); 86912856Sgiacomo.gabrielli@arm.com default: 87012856Sgiacomo.gabrielli@arm.com M5_UNREACHABLE; 87112856Sgiacomo.gabrielli@arm.com } 87212856Sgiacomo.gabrielli@arm.com } else { 87312856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 87412856Sgiacomo.gabrielli@arm.com } 87512856Sgiacomo.gabrielli@arm.com } 87612856Sgiacomo.gabrielli@arm.com case 0x2: 87712856Sgiacomo.gabrielli@arm.com { 87812856Sgiacomo.gabrielli@arm.com if (!bits(machInst, 14)) 87912856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 88012856Sgiacomo.gabrielli@arm.com IntRegIndex rt = (IntRegIndex)(uint32_t) 88112856Sgiacomo.gabrielli@arm.com bits(machInst, 4, 0); 88212856Sgiacomo.gabrielli@arm.com IntRegIndex rn = (IntRegIndex)(uint32_t) 88312856Sgiacomo.gabrielli@arm.com bits(machInst, 9, 5); 88412856Sgiacomo.gabrielli@arm.com IntRegIndex rnsp = makeSP(rn); 88512856Sgiacomo.gabrielli@arm.com IntRegIndex rm = (IntRegIndex)(uint32_t) 88612856Sgiacomo.gabrielli@arm.com bits(machInst, 20, 16); 88712856Sgiacomo.gabrielli@arm.com ArmExtendType type = 88812856Sgiacomo.gabrielli@arm.com (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 88912856Sgiacomo.gabrielli@arm.com uint8_t s = bits(machInst, 12); 89012856Sgiacomo.gabrielli@arm.com switch (switchVal) { 89112856Sgiacomo.gabrielli@arm.com case 0x00: 89212856Sgiacomo.gabrielli@arm.com return new STRB64_REG(machInst, rt, rnsp, rm, 89312856Sgiacomo.gabrielli@arm.com type, 0); 89412856Sgiacomo.gabrielli@arm.com case 0x01: 89512856Sgiacomo.gabrielli@arm.com return new LDRB64_REG(machInst, rt, rnsp, rm, 89612856Sgiacomo.gabrielli@arm.com type, 0); 89712856Sgiacomo.gabrielli@arm.com case 0x02: 89812856Sgiacomo.gabrielli@arm.com return new LDRSBX64_REG(machInst, rt, rnsp, rm, 89912856Sgiacomo.gabrielli@arm.com type, 0); 90012856Sgiacomo.gabrielli@arm.com case 0x03: 90112856Sgiacomo.gabrielli@arm.com return new LDRSBW64_REG(machInst, rt, rnsp, rm, 90212856Sgiacomo.gabrielli@arm.com type, 0); 90312856Sgiacomo.gabrielli@arm.com case 0x04: 90412856Sgiacomo.gabrielli@arm.com return new STRBFP64_REG(machInst, rt, rnsp, rm, 90512856Sgiacomo.gabrielli@arm.com type, 0); 90612856Sgiacomo.gabrielli@arm.com case 0x05: 90712856Sgiacomo.gabrielli@arm.com return new LDRBFP64_REG(machInst, rt, rnsp, rm, 90812856Sgiacomo.gabrielli@arm.com type, 0); 90912856Sgiacomo.gabrielli@arm.com case 0x6: 91012856Sgiacomo.gabrielli@arm.com return new BigFpMemReg("str", machInst, false, 91112856Sgiacomo.gabrielli@arm.com rt, rnsp, rm, type, s * 4); 91212856Sgiacomo.gabrielli@arm.com case 0x7: 91312856Sgiacomo.gabrielli@arm.com return new BigFpMemReg("ldr", machInst, true, 91412856Sgiacomo.gabrielli@arm.com rt, rnsp, rm, type, s * 4); 91512856Sgiacomo.gabrielli@arm.com case 0x08: 91612856Sgiacomo.gabrielli@arm.com return new STRH64_REG(machInst, rt, rnsp, rm, 91712856Sgiacomo.gabrielli@arm.com type, s); 91812856Sgiacomo.gabrielli@arm.com case 0x09: 91912856Sgiacomo.gabrielli@arm.com return new LDRH64_REG(machInst, rt, rnsp, rm, 92012856Sgiacomo.gabrielli@arm.com type, s); 92112856Sgiacomo.gabrielli@arm.com case 0x0a: 92212856Sgiacomo.gabrielli@arm.com return new LDRSHX64_REG(machInst, rt, rnsp, rm, 92312856Sgiacomo.gabrielli@arm.com type, s); 92412856Sgiacomo.gabrielli@arm.com case 0x0b: 92512856Sgiacomo.gabrielli@arm.com return new LDRSHW64_REG(machInst, rt, rnsp, rm, 92612856Sgiacomo.gabrielli@arm.com type, s); 92712856Sgiacomo.gabrielli@arm.com case 0x0c: 92812856Sgiacomo.gabrielli@arm.com return new STRHFP64_REG(machInst, rt, rnsp, rm, 92912856Sgiacomo.gabrielli@arm.com type, s); 93012856Sgiacomo.gabrielli@arm.com case 0x0d: 93112856Sgiacomo.gabrielli@arm.com return new LDRHFP64_REG(machInst, rt, rnsp, rm, 93212856Sgiacomo.gabrielli@arm.com type, s); 93312856Sgiacomo.gabrielli@arm.com case 0x10: 93412856Sgiacomo.gabrielli@arm.com return new STRW64_REG(machInst, rt, rnsp, rm, 93512856Sgiacomo.gabrielli@arm.com type, s * 2); 93612856Sgiacomo.gabrielli@arm.com case 0x11: 93712856Sgiacomo.gabrielli@arm.com return new LDRW64_REG(machInst, rt, rnsp, rm, 93812856Sgiacomo.gabrielli@arm.com type, s * 2); 93912856Sgiacomo.gabrielli@arm.com case 0x12: 94012856Sgiacomo.gabrielli@arm.com return new LDRSW64_REG(machInst, rt, rnsp, rm, 94112856Sgiacomo.gabrielli@arm.com type, s * 2); 94212856Sgiacomo.gabrielli@arm.com case 0x14: 94312856Sgiacomo.gabrielli@arm.com return new STRSFP64_REG(machInst, rt, rnsp, rm, 94412856Sgiacomo.gabrielli@arm.com type, s * 2); 94512856Sgiacomo.gabrielli@arm.com case 0x15: 94612856Sgiacomo.gabrielli@arm.com return new LDRSFP64_REG(machInst, rt, rnsp, rm, 94712856Sgiacomo.gabrielli@arm.com type, s * 2); 94812856Sgiacomo.gabrielli@arm.com case 0x18: 94912856Sgiacomo.gabrielli@arm.com return new STRX64_REG(machInst, rt, rnsp, rm, 95012856Sgiacomo.gabrielli@arm.com type, s * 3); 95112856Sgiacomo.gabrielli@arm.com case 0x19: 95212856Sgiacomo.gabrielli@arm.com return new LDRX64_REG(machInst, rt, rnsp, rm, 95312856Sgiacomo.gabrielli@arm.com type, s * 3); 95412856Sgiacomo.gabrielli@arm.com case 0x1a: 95512856Sgiacomo.gabrielli@arm.com return new PRFM64_REG(machInst, rt, rnsp, rm, 95612856Sgiacomo.gabrielli@arm.com type, s * 3); 95712856Sgiacomo.gabrielli@arm.com case 0x1c: 95812856Sgiacomo.gabrielli@arm.com return new STRDFP64_REG(machInst, rt, rnsp, rm, 95912856Sgiacomo.gabrielli@arm.com type, s * 3); 96012856Sgiacomo.gabrielli@arm.com case 0x1d: 96112856Sgiacomo.gabrielli@arm.com return new LDRDFP64_REG(machInst, rt, rnsp, rm, 96212856Sgiacomo.gabrielli@arm.com type, s * 3); 96312856Sgiacomo.gabrielli@arm.com default: 96412856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 96512856Sgiacomo.gabrielli@arm.com 96612856Sgiacomo.gabrielli@arm.com } 96712856Sgiacomo.gabrielli@arm.com } 96810037SARM gem5 Developers default: 96910037SARM gem5 Developers return new Unknown64(machInst); 97010037SARM gem5 Developers } 97110037SARM gem5 Developers } else { 97210037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0 97310037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 97410037SARM gem5 Developers case 0x0: 97510037SARM gem5 Developers { 97610037SARM gem5 Developers IntRegIndex rt = 97710037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 97810037SARM gem5 Developers IntRegIndex rn = 97910037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 98010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 98110037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 98210037SARM gem5 Developers switch (switchVal) { 98310037SARM gem5 Developers case 0x00: 98410037SARM gem5 Developers return new STURB64_IMM(machInst, rt, rnsp, imm); 98510037SARM gem5 Developers case 0x01: 98610037SARM gem5 Developers return new LDURB64_IMM(machInst, rt, rnsp, imm); 98710037SARM gem5 Developers case 0x02: 98810037SARM gem5 Developers return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 98910037SARM gem5 Developers case 0x03: 99010037SARM gem5 Developers return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 99110037SARM gem5 Developers case 0x04: 99210037SARM gem5 Developers return new STURBFP64_IMM(machInst, rt, rnsp, imm); 99310037SARM gem5 Developers case 0x05: 99410037SARM gem5 Developers return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 99510037SARM gem5 Developers case 0x06: 99610037SARM gem5 Developers return new BigFpMemImm("stur", machInst, false, 99710037SARM gem5 Developers rt, rnsp, imm); 99810037SARM gem5 Developers case 0x07: 99910037SARM gem5 Developers return new BigFpMemImm("ldur", machInst, true, 100010037SARM gem5 Developers rt, rnsp, imm); 100110037SARM gem5 Developers case 0x08: 100210037SARM gem5 Developers return new STURH64_IMM(machInst, rt, rnsp, imm); 100310037SARM gem5 Developers case 0x09: 100410037SARM gem5 Developers return new LDURH64_IMM(machInst, rt, rnsp, imm); 100510037SARM gem5 Developers case 0x0a: 100610037SARM gem5 Developers return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 100710037SARM gem5 Developers case 0x0b: 100810037SARM gem5 Developers return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 100910037SARM gem5 Developers case 0x0c: 101010037SARM gem5 Developers return new STURHFP64_IMM(machInst, rt, rnsp, imm); 101110037SARM gem5 Developers case 0x0d: 101210037SARM gem5 Developers return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 101310037SARM gem5 Developers case 0x10: 101410037SARM gem5 Developers return new STURW64_IMM(machInst, rt, rnsp, imm); 101510037SARM gem5 Developers case 0x11: 101610037SARM gem5 Developers return new LDURW64_IMM(machInst, rt, rnsp, imm); 101710037SARM gem5 Developers case 0x12: 101810037SARM gem5 Developers return new LDURSW64_IMM(machInst, rt, rnsp, imm); 101910037SARM gem5 Developers case 0x14: 102010037SARM gem5 Developers return new STURSFP64_IMM(machInst, rt, rnsp, imm); 102110037SARM gem5 Developers case 0x15: 102210037SARM gem5 Developers return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 102310037SARM gem5 Developers case 0x18: 102410037SARM gem5 Developers return new STURX64_IMM(machInst, rt, rnsp, imm); 102510037SARM gem5 Developers case 0x19: 102610037SARM gem5 Developers return new LDURX64_IMM(machInst, rt, rnsp, imm); 102710037SARM gem5 Developers case 0x1a: 102810037SARM gem5 Developers return new PRFUM64_IMM(machInst, rt, rnsp, imm); 102910037SARM gem5 Developers case 0x1c: 103010037SARM gem5 Developers return new STURDFP64_IMM(machInst, rt, rnsp, imm); 103110037SARM gem5 Developers case 0x1d: 103210037SARM gem5 Developers return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 103310037SARM gem5 Developers default: 103410037SARM gem5 Developers return new Unknown64(machInst); 103510037SARM gem5 Developers } 103610037SARM gem5 Developers } 103710037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0, 11:10=01 103810037SARM gem5 Developers case 0x1: 103910037SARM gem5 Developers { 104010037SARM gem5 Developers IntRegIndex rt = 104110037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 104210037SARM gem5 Developers IntRegIndex rn = 104310037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 104410037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 104510037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 104610037SARM gem5 Developers switch (switchVal) { 104710037SARM gem5 Developers case 0x00: 104810037SARM gem5 Developers return new STRB64_POST(machInst, rt, rnsp, imm); 104910037SARM gem5 Developers case 0x01: 105010037SARM gem5 Developers return new LDRB64_POST(machInst, rt, rnsp, imm); 105110037SARM gem5 Developers case 0x02: 105210037SARM gem5 Developers return new LDRSBX64_POST(machInst, rt, rnsp, imm); 105310037SARM gem5 Developers case 0x03: 105410037SARM gem5 Developers return new LDRSBW64_POST(machInst, rt, rnsp, imm); 105510037SARM gem5 Developers case 0x04: 105610037SARM gem5 Developers return new STRBFP64_POST(machInst, rt, rnsp, imm); 105710037SARM gem5 Developers case 0x05: 105810037SARM gem5 Developers return new LDRBFP64_POST(machInst, rt, rnsp, imm); 105910037SARM gem5 Developers case 0x06: 106010037SARM gem5 Developers return new BigFpMemPost("str", machInst, false, 106110037SARM gem5 Developers rt, rnsp, imm); 106210037SARM gem5 Developers case 0x07: 106310037SARM gem5 Developers return new BigFpMemPost("ldr", machInst, true, 106410037SARM gem5 Developers rt, rnsp, imm); 106510037SARM gem5 Developers case 0x08: 106610037SARM gem5 Developers return new STRH64_POST(machInst, rt, rnsp, imm); 106710037SARM gem5 Developers case 0x09: 106810037SARM gem5 Developers return new LDRH64_POST(machInst, rt, rnsp, imm); 106910037SARM gem5 Developers case 0x0a: 107010037SARM gem5 Developers return new LDRSHX64_POST(machInst, rt, rnsp, imm); 107110037SARM gem5 Developers case 0x0b: 107210037SARM gem5 Developers return new LDRSHW64_POST(machInst, rt, rnsp, imm); 107310037SARM gem5 Developers case 0x0c: 107410037SARM gem5 Developers return new STRHFP64_POST(machInst, rt, rnsp, imm); 107510037SARM gem5 Developers case 0x0d: 107610037SARM gem5 Developers return new LDRHFP64_POST(machInst, rt, rnsp, imm); 107710037SARM gem5 Developers case 0x10: 107810037SARM gem5 Developers return new STRW64_POST(machInst, rt, rnsp, imm); 107910037SARM gem5 Developers case 0x11: 108010037SARM gem5 Developers return new LDRW64_POST(machInst, rt, rnsp, imm); 108110037SARM gem5 Developers case 0x12: 108210037SARM gem5 Developers return new LDRSW64_POST(machInst, rt, rnsp, imm); 108310037SARM gem5 Developers case 0x14: 108410037SARM gem5 Developers return new STRSFP64_POST(machInst, rt, rnsp, imm); 108510037SARM gem5 Developers case 0x15: 108610037SARM gem5 Developers return new LDRSFP64_POST(machInst, rt, rnsp, imm); 108710037SARM gem5 Developers case 0x18: 108810037SARM gem5 Developers return new STRX64_POST(machInst, rt, rnsp, imm); 108910037SARM gem5 Developers case 0x19: 109010037SARM gem5 Developers return new LDRX64_POST(machInst, rt, rnsp, imm); 109110037SARM gem5 Developers case 0x1c: 109210037SARM gem5 Developers return new STRDFP64_POST(machInst, rt, rnsp, imm); 109310037SARM gem5 Developers case 0x1d: 109410037SARM gem5 Developers return new LDRDFP64_POST(machInst, rt, rnsp, imm); 109510037SARM gem5 Developers default: 109610037SARM gem5 Developers return new Unknown64(machInst); 109710037SARM gem5 Developers } 109810037SARM gem5 Developers } 109910037SARM gem5 Developers case 0x2: 110010037SARM gem5 Developers { 110110037SARM gem5 Developers IntRegIndex rt = 110210037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 110310037SARM gem5 Developers IntRegIndex rn = 110410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 110510037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 110610037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 110710037SARM gem5 Developers switch (switchVal) { 110810037SARM gem5 Developers case 0x00: 110910037SARM gem5 Developers return new STTRB64_IMM(machInst, rt, rnsp, imm); 111010037SARM gem5 Developers case 0x01: 111110037SARM gem5 Developers return new LDTRB64_IMM(machInst, rt, rnsp, imm); 111210037SARM gem5 Developers case 0x02: 111310037SARM gem5 Developers return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 111410037SARM gem5 Developers case 0x03: 111510037SARM gem5 Developers return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 111610037SARM gem5 Developers case 0x08: 111710037SARM gem5 Developers return new STTRH64_IMM(machInst, rt, rnsp, imm); 111810037SARM gem5 Developers case 0x09: 111910037SARM gem5 Developers return new LDTRH64_IMM(machInst, rt, rnsp, imm); 112010037SARM gem5 Developers case 0x0a: 112110037SARM gem5 Developers return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 112210037SARM gem5 Developers case 0x0b: 112310037SARM gem5 Developers return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 112410037SARM gem5 Developers case 0x10: 112510037SARM gem5 Developers return new STTRW64_IMM(machInst, rt, rnsp, imm); 112610037SARM gem5 Developers case 0x11: 112710037SARM gem5 Developers return new LDTRW64_IMM(machInst, rt, rnsp, imm); 112810037SARM gem5 Developers case 0x12: 112910037SARM gem5 Developers return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 113010037SARM gem5 Developers case 0x18: 113110037SARM gem5 Developers return new STTRX64_IMM(machInst, rt, rnsp, imm); 113210037SARM gem5 Developers case 0x19: 113310037SARM gem5 Developers return new LDTRX64_IMM(machInst, rt, rnsp, imm); 113410037SARM gem5 Developers default: 113510037SARM gem5 Developers return new Unknown64(machInst); 113610037SARM gem5 Developers } 113710037SARM gem5 Developers } 113810037SARM gem5 Developers case 0x3: 113910037SARM gem5 Developers { 114010037SARM gem5 Developers IntRegIndex rt = 114110037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 114210037SARM gem5 Developers IntRegIndex rn = 114310037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 114410037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 114510037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 114610037SARM gem5 Developers switch (switchVal) { 114710037SARM gem5 Developers case 0x00: 114810037SARM gem5 Developers return new STRB64_PRE(machInst, rt, rnsp, imm); 114910037SARM gem5 Developers case 0x01: 115010037SARM gem5 Developers return new LDRB64_PRE(machInst, rt, rnsp, imm); 115110037SARM gem5 Developers case 0x02: 115210037SARM gem5 Developers return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 115310037SARM gem5 Developers case 0x03: 115410037SARM gem5 Developers return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 115510037SARM gem5 Developers case 0x04: 115610037SARM gem5 Developers return new STRBFP64_PRE(machInst, rt, rnsp, imm); 115710037SARM gem5 Developers case 0x05: 115810037SARM gem5 Developers return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 115910037SARM gem5 Developers case 0x06: 116010037SARM gem5 Developers return new BigFpMemPre("str", machInst, false, 116110037SARM gem5 Developers rt, rnsp, imm); 116210037SARM gem5 Developers case 0x07: 116310037SARM gem5 Developers return new BigFpMemPre("ldr", machInst, true, 116410037SARM gem5 Developers rt, rnsp, imm); 116510037SARM gem5 Developers case 0x08: 116610037SARM gem5 Developers return new STRH64_PRE(machInst, rt, rnsp, imm); 116710037SARM gem5 Developers case 0x09: 116810037SARM gem5 Developers return new LDRH64_PRE(machInst, rt, rnsp, imm); 116910037SARM gem5 Developers case 0x0a: 117010037SARM gem5 Developers return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 117110037SARM gem5 Developers case 0x0b: 117210037SARM gem5 Developers return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 117310037SARM gem5 Developers case 0x0c: 117410037SARM gem5 Developers return new STRHFP64_PRE(machInst, rt, rnsp, imm); 117510037SARM gem5 Developers case 0x0d: 117610037SARM gem5 Developers return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 117710037SARM gem5 Developers case 0x10: 117810037SARM gem5 Developers return new STRW64_PRE(machInst, rt, rnsp, imm); 117910037SARM gem5 Developers case 0x11: 118010037SARM gem5 Developers return new LDRW64_PRE(machInst, rt, rnsp, imm); 118110037SARM gem5 Developers case 0x12: 118210037SARM gem5 Developers return new LDRSW64_PRE(machInst, rt, rnsp, imm); 118310037SARM gem5 Developers case 0x14: 118410037SARM gem5 Developers return new STRSFP64_PRE(machInst, rt, rnsp, imm); 118510037SARM gem5 Developers case 0x15: 118610037SARM gem5 Developers return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 118710037SARM gem5 Developers case 0x18: 118810037SARM gem5 Developers return new STRX64_PRE(machInst, rt, rnsp, imm); 118910037SARM gem5 Developers case 0x19: 119010037SARM gem5 Developers return new LDRX64_PRE(machInst, rt, rnsp, imm); 119110037SARM gem5 Developers case 0x1c: 119210037SARM gem5 Developers return new STRDFP64_PRE(machInst, rt, rnsp, imm); 119310037SARM gem5 Developers case 0x1d: 119410037SARM gem5 Developers return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 119510037SARM gem5 Developers default: 119610037SARM gem5 Developers return new Unknown64(machInst); 119710037SARM gem5 Developers } 119810037SARM gem5 Developers } 119912595Ssiddhesh.poyarekar@gmail.com default: 120012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 120110037SARM gem5 Developers } 120210037SARM gem5 Developers } 120310037SARM gem5 Developers } 120412595Ssiddhesh.poyarekar@gmail.com default: 120512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 120610037SARM gem5 Developers } 120710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case1", machInst); 120810037SARM gem5 Developers } 120910037SARM gem5 Developers} 121010037SARM gem5 Developers}}; 121110037SARM gem5 Developers 121210037SARM gem5 Developersoutput decoder {{ 121310037SARM gem5 Developersnamespace Aarch64 121410037SARM gem5 Developers{ 121510037SARM gem5 Developers StaticInstPtr 121610037SARM gem5 Developers decodeDataProcReg(ExtMachInst machInst) 121710037SARM gem5 Developers { 121810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 28) << 1) | 121910037SARM gem5 Developers (bits(machInst, 24) << 0); 122010037SARM gem5 Developers switch (switchVal) { 122110037SARM gem5 Developers case 0x0: 122210037SARM gem5 Developers { 122310037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 21) << 0) | 122410037SARM gem5 Developers (bits(machInst, 30, 29) << 1); 122510037SARM gem5 Developers ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 122610037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 122710037SARM gem5 Developers bool sf = bits(machInst, 31); 122810037SARM gem5 Developers if (!sf && (imm6 & 0x20)) 122910037SARM gem5 Developers return new Unknown64(machInst); 123010037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 123110337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 123210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 123310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 123410037SARM gem5 Developers 123510037SARM gem5 Developers switch (switchVal) { 123610037SARM gem5 Developers case 0x0: 123710337SAndrew.Bardsley@arm.com return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 123810037SARM gem5 Developers case 0x1: 123910337SAndrew.Bardsley@arm.com return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 124010037SARM gem5 Developers case 0x2: 124110337SAndrew.Bardsley@arm.com return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 124210037SARM gem5 Developers case 0x3: 124310337SAndrew.Bardsley@arm.com return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 124410037SARM gem5 Developers case 0x4: 124510337SAndrew.Bardsley@arm.com return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 124610037SARM gem5 Developers case 0x5: 124710337SAndrew.Bardsley@arm.com return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 124810037SARM gem5 Developers case 0x6: 124910337SAndrew.Bardsley@arm.com return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 125010037SARM gem5 Developers case 0x7: 125110337SAndrew.Bardsley@arm.com return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 125212595Ssiddhesh.poyarekar@gmail.com default: 125312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 125410037SARM gem5 Developers } 125510037SARM gem5 Developers } 125610037SARM gem5 Developers case 0x1: 125710037SARM gem5 Developers { 125810037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 125910037SARM gem5 Developers if (bits(machInst, 21) == 0) { 126010037SARM gem5 Developers ArmShiftType type = 126110037SARM gem5 Developers (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 126210037SARM gem5 Developers if (type == ROR) 126310037SARM gem5 Developers return new Unknown64(machInst); 126410037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 126510037SARM gem5 Developers if (!bits(machInst, 31) && bits(imm6, 5)) 126610037SARM gem5 Developers return new Unknown64(machInst); 126710037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 126810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 126910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 127010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 127110037SARM gem5 Developers switch (switchVal) { 127210037SARM gem5 Developers case 0x0: 127310337SAndrew.Bardsley@arm.com return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 127410037SARM gem5 Developers case 0x1: 127510337SAndrew.Bardsley@arm.com return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 127610037SARM gem5 Developers case 0x2: 127710337SAndrew.Bardsley@arm.com return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 127810037SARM gem5 Developers case 0x3: 127910337SAndrew.Bardsley@arm.com return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 128012595Ssiddhesh.poyarekar@gmail.com default: 128112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 128210037SARM gem5 Developers } 128310037SARM gem5 Developers } else { 128410037SARM gem5 Developers if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 128510037SARM gem5 Developers return new Unknown64(machInst); 128610037SARM gem5 Developers ArmExtendType type = 128710037SARM gem5 Developers (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 128810037SARM gem5 Developers uint8_t imm3 = bits(machInst, 12, 10); 128910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 129010037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 129110337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 129210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 129310037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 129410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 129510037SARM gem5 Developers 129610037SARM gem5 Developers switch (switchVal) { 129710037SARM gem5 Developers case 0x0: 129810037SARM gem5 Developers return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 129910037SARM gem5 Developers case 0x1: 130010337SAndrew.Bardsley@arm.com return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 130110037SARM gem5 Developers case 0x2: 130210037SARM gem5 Developers return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 130310037SARM gem5 Developers case 0x3: 130410337SAndrew.Bardsley@arm.com return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 130512595Ssiddhesh.poyarekar@gmail.com default: 130612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 130710037SARM gem5 Developers } 130810037SARM gem5 Developers } 130910037SARM gem5 Developers } 131010037SARM gem5 Developers case 0x2: 131110037SARM gem5 Developers { 131210037SARM gem5 Developers if (bits(machInst, 21) == 1) 131310037SARM gem5 Developers return new Unknown64(machInst); 131410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 131510337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 131610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 131710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 131810037SARM gem5 Developers switch (bits(machInst, 23, 22)) { 131910037SARM gem5 Developers case 0x0: 132010037SARM gem5 Developers { 132110037SARM gem5 Developers if (bits(machInst, 15, 10)) 132210037SARM gem5 Developers return new Unknown64(machInst); 132310037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 132410037SARM gem5 Developers switch (switchVal) { 132510037SARM gem5 Developers case 0x0: 132610337SAndrew.Bardsley@arm.com return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 132710037SARM gem5 Developers case 0x1: 132810337SAndrew.Bardsley@arm.com return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 132910037SARM gem5 Developers case 0x2: 133010337SAndrew.Bardsley@arm.com return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 133110037SARM gem5 Developers case 0x3: 133210337SAndrew.Bardsley@arm.com return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 133312595Ssiddhesh.poyarekar@gmail.com default: 133412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 133510037SARM gem5 Developers } 133610037SARM gem5 Developers } 133710037SARM gem5 Developers case 0x1: 133810037SARM gem5 Developers { 133910037SARM gem5 Developers if ((bits(machInst, 4) == 1) || 134010037SARM gem5 Developers (bits(machInst, 10) == 1) || 134110037SARM gem5 Developers (bits(machInst, 29) == 0)) { 134210037SARM gem5 Developers return new Unknown64(machInst); 134310037SARM gem5 Developers } 134410037SARM gem5 Developers ConditionCode cond = 134510037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 134610037SARM gem5 Developers uint8_t flags = bits(machInst, 3, 0); 134710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 134810037SARM gem5 Developers if (bits(machInst, 11) == 0) { 134910037SARM gem5 Developers IntRegIndex rm = 135010037SARM gem5 Developers (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 135110037SARM gem5 Developers if (bits(machInst, 30) == 0) { 135210037SARM gem5 Developers return new CcmnReg64(machInst, rn, rm, cond, flags); 135310037SARM gem5 Developers } else { 135410037SARM gem5 Developers return new CcmpReg64(machInst, rn, rm, cond, flags); 135510037SARM gem5 Developers } 135610037SARM gem5 Developers } else { 135710037SARM gem5 Developers uint8_t imm5 = bits(machInst, 20, 16); 135810037SARM gem5 Developers if (bits(machInst, 30) == 0) { 135910037SARM gem5 Developers return new CcmnImm64(machInst, rn, imm5, cond, flags); 136010037SARM gem5 Developers } else { 136110037SARM gem5 Developers return new CcmpImm64(machInst, rn, imm5, cond, flags); 136210037SARM gem5 Developers } 136310037SARM gem5 Developers } 136410037SARM gem5 Developers } 136510037SARM gem5 Developers case 0x2: 136610037SARM gem5 Developers { 136710037SARM gem5 Developers if (bits(machInst, 29) == 1 || 136810037SARM gem5 Developers bits(machInst, 11) == 1) { 136910037SARM gem5 Developers return new Unknown64(machInst); 137010037SARM gem5 Developers } 137110037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 10) << 0) | 137210037SARM gem5 Developers (bits(machInst, 30) << 1); 137310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 137410337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 137510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 137610037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 137710037SARM gem5 Developers ConditionCode cond = 137810037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 137910037SARM gem5 Developers switch (switchVal) { 138010037SARM gem5 Developers case 0x0: 138110337SAndrew.Bardsley@arm.com return new Csel64(machInst, rdzr, rn, rm, cond); 138210037SARM gem5 Developers case 0x1: 138310337SAndrew.Bardsley@arm.com return new Csinc64(machInst, rdzr, rn, rm, cond); 138410037SARM gem5 Developers case 0x2: 138510337SAndrew.Bardsley@arm.com return new Csinv64(machInst, rdzr, rn, rm, cond); 138610037SARM gem5 Developers case 0x3: 138710337SAndrew.Bardsley@arm.com return new Csneg64(machInst, rdzr, rn, rm, cond); 138812595Ssiddhesh.poyarekar@gmail.com default: 138912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 139010037SARM gem5 Developers } 139110037SARM gem5 Developers } 139210037SARM gem5 Developers case 0x3: 139310037SARM gem5 Developers if (bits(machInst, 30) == 0) { 139410037SARM gem5 Developers if (bits(machInst, 29) != 0) 139510037SARM gem5 Developers return new Unknown64(machInst); 139610037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 139710037SARM gem5 Developers switch (switchVal) { 139810037SARM gem5 Developers case 0x2: 139910337SAndrew.Bardsley@arm.com return new Udiv64(machInst, rdzr, rn, rm); 140010037SARM gem5 Developers case 0x3: 140110337SAndrew.Bardsley@arm.com return new Sdiv64(machInst, rdzr, rn, rm); 140210037SARM gem5 Developers case 0x8: 140310337SAndrew.Bardsley@arm.com return new Lslv64(machInst, rdzr, rn, rm); 140410037SARM gem5 Developers case 0x9: 140510337SAndrew.Bardsley@arm.com return new Lsrv64(machInst, rdzr, rn, rm); 140610037SARM gem5 Developers case 0xa: 140710337SAndrew.Bardsley@arm.com return new Asrv64(machInst, rdzr, rn, rm); 140810037SARM gem5 Developers case 0xb: 140910337SAndrew.Bardsley@arm.com return new Rorv64(machInst, rdzr, rn, rm); 141012258Sgiacomo.travaglini@arm.com case 0x10: 141112258Sgiacomo.travaglini@arm.com return new Crc32b64(machInst, rdzr, rn, rm); 141212258Sgiacomo.travaglini@arm.com case 0x11: 141312258Sgiacomo.travaglini@arm.com return new Crc32h64(machInst, rdzr, rn, rm); 141412258Sgiacomo.travaglini@arm.com case 0x12: 141512258Sgiacomo.travaglini@arm.com return new Crc32w64(machInst, rdzr, rn, rm); 141612258Sgiacomo.travaglini@arm.com case 0x13: 141712258Sgiacomo.travaglini@arm.com return new Crc32x64(machInst, rdzr, rn, rm); 141812258Sgiacomo.travaglini@arm.com case 0x14: 141912258Sgiacomo.travaglini@arm.com return new Crc32cb64(machInst, rdzr, rn, rm); 142012258Sgiacomo.travaglini@arm.com case 0x15: 142112258Sgiacomo.travaglini@arm.com return new Crc32ch64(machInst, rdzr, rn, rm); 142212258Sgiacomo.travaglini@arm.com case 0x16: 142312258Sgiacomo.travaglini@arm.com return new Crc32cw64(machInst, rdzr, rn, rm); 142412258Sgiacomo.travaglini@arm.com case 0x17: 142512258Sgiacomo.travaglini@arm.com return new Crc32cx64(machInst, rdzr, rn, rm); 142610037SARM gem5 Developers default: 142710037SARM gem5 Developers return new Unknown64(machInst); 142810037SARM gem5 Developers } 142910037SARM gem5 Developers } else { 143010037SARM gem5 Developers if (bits(machInst, 20, 16) != 0 || 143110037SARM gem5 Developers bits(machInst, 29) != 0) { 143210037SARM gem5 Developers return new Unknown64(machInst); 143310037SARM gem5 Developers } 143410037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 143510037SARM gem5 Developers switch (switchVal) { 143610037SARM gem5 Developers case 0x0: 143710337SAndrew.Bardsley@arm.com return new Rbit64(machInst, rdzr, rn); 143810037SARM gem5 Developers case 0x1: 143910337SAndrew.Bardsley@arm.com return new Rev1664(machInst, rdzr, rn); 144010037SARM gem5 Developers case 0x2: 144110037SARM gem5 Developers if (bits(machInst, 31) == 0) 144210337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 144310037SARM gem5 Developers else 144410337SAndrew.Bardsley@arm.com return new Rev3264(machInst, rdzr, rn); 144510037SARM gem5 Developers case 0x3: 144610037SARM gem5 Developers if (bits(machInst, 31) != 1) 144710037SARM gem5 Developers return new Unknown64(machInst); 144810337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 144910037SARM gem5 Developers case 0x4: 145010337SAndrew.Bardsley@arm.com return new Clz64(machInst, rdzr, rn); 145110037SARM gem5 Developers case 0x5: 145210337SAndrew.Bardsley@arm.com return new Cls64(machInst, rdzr, rn); 145312595Ssiddhesh.poyarekar@gmail.com default: 145412595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 145510037SARM gem5 Developers } 145610037SARM gem5 Developers } 145712595Ssiddhesh.poyarekar@gmail.com default: 145812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 145910037SARM gem5 Developers } 146010037SARM gem5 Developers } 146110037SARM gem5 Developers case 0x3: 146210037SARM gem5 Developers { 146310037SARM gem5 Developers if (bits(machInst, 30, 29) != 0x0 || 146410037SARM gem5 Developers (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 146510037SARM gem5 Developers return new Unknown64(machInst); 146610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 146710337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 146810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 146910037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 147010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 147110037SARM gem5 Developers switch (bits(machInst, 23, 21)) { 147210037SARM gem5 Developers case 0x0: 147310037SARM gem5 Developers if (bits(machInst, 15) == 0) 147410337SAndrew.Bardsley@arm.com return new Madd64(machInst, rdzr, ra, rn, rm); 147510037SARM gem5 Developers else 147610337SAndrew.Bardsley@arm.com return new Msub64(machInst, rdzr, ra, rn, rm); 147710037SARM gem5 Developers case 0x1: 147810037SARM gem5 Developers if (bits(machInst, 15) == 0) 147910337SAndrew.Bardsley@arm.com return new Smaddl64(machInst, rdzr, ra, rn, rm); 148010037SARM gem5 Developers else 148110337SAndrew.Bardsley@arm.com return new Smsubl64(machInst, rdzr, ra, rn, rm); 148210037SARM gem5 Developers case 0x2: 148310037SARM gem5 Developers if (bits(machInst, 15) != 0) 148410037SARM gem5 Developers return new Unknown64(machInst); 148510337SAndrew.Bardsley@arm.com return new Smulh64(machInst, rdzr, rn, rm); 148610037SARM gem5 Developers case 0x5: 148710037SARM gem5 Developers if (bits(machInst, 15) == 0) 148810337SAndrew.Bardsley@arm.com return new Umaddl64(machInst, rdzr, ra, rn, rm); 148910037SARM gem5 Developers else 149010337SAndrew.Bardsley@arm.com return new Umsubl64(machInst, rdzr, ra, rn, rm); 149110037SARM gem5 Developers case 0x6: 149210037SARM gem5 Developers if (bits(machInst, 15) != 0) 149310037SARM gem5 Developers return new Unknown64(machInst); 149410337SAndrew.Bardsley@arm.com return new Umulh64(machInst, rdzr, rn, rm); 149510037SARM gem5 Developers default: 149610037SARM gem5 Developers return new Unknown64(machInst); 149710037SARM gem5 Developers } 149810037SARM gem5 Developers } 149912595Ssiddhesh.poyarekar@gmail.com default: 150012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 150110037SARM gem5 Developers } 150210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case2", machInst); 150310037SARM gem5 Developers } 150410037SARM gem5 Developers} 150510037SARM gem5 Developers}}; 150610037SARM gem5 Developers 150710037SARM gem5 Developersoutput decoder {{ 150810037SARM gem5 Developersnamespace Aarch64 150910037SARM gem5 Developers{ 151011165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 151110037SARM gem5 Developers StaticInstPtr 151210037SARM gem5 Developers decodeAdvSIMD(ExtMachInst machInst) 151310037SARM gem5 Developers { 151410037SARM gem5 Developers if (bits(machInst, 24) == 1) { 151510037SARM gem5 Developers if (bits(machInst, 10) == 0) { 151611165SRekai.GonzalezAlberquilla@arm.com return decodeNeonIndexedElem<DecoderFeatures>(machInst); 151710037SARM gem5 Developers } else if (bits(machInst, 23) == 1) { 151810037SARM gem5 Developers return new Unknown64(machInst); 151910037SARM gem5 Developers } else { 152010037SARM gem5 Developers if (bits(machInst, 22, 19)) { 152110037SARM gem5 Developers return decodeNeonShiftByImm(machInst); 152210037SARM gem5 Developers } else { 152310037SARM gem5 Developers return decodeNeonModImm(machInst); 152410037SARM gem5 Developers } 152510037SARM gem5 Developers } 152610037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 152710037SARM gem5 Developers if (bits(machInst, 10) == 1) { 152811165SRekai.GonzalezAlberquilla@arm.com return decodeNeon3Same<DecoderFeatures>(machInst); 152910037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 153010037SARM gem5 Developers return decodeNeon3Diff(machInst); 153110037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 153210037SARM gem5 Developers return decodeNeon2RegMisc(machInst); 153313171Sgiacomo.travaglini@arm.com } else if (bits(machInst, 20, 17) == 0x4) { 153413171Sgiacomo.travaglini@arm.com return decodeCryptoAES(machInst); 153510037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 153610037SARM gem5 Developers return decodeNeonAcrossLanes(machInst); 153710037SARM gem5 Developers } else { 153810037SARM gem5 Developers return new Unknown64(machInst); 153910037SARM gem5 Developers } 154010037SARM gem5 Developers } else if (bits(machInst, 24) || 154110037SARM gem5 Developers bits(machInst, 21) || 154210037SARM gem5 Developers bits(machInst, 15)) { 154310037SARM gem5 Developers return new Unknown64(machInst); 154410037SARM gem5 Developers } else if (bits(machInst, 10) == 1) { 154510037SARM gem5 Developers if (bits(machInst, 23, 22)) 154610037SARM gem5 Developers return new Unknown64(machInst); 154710037SARM gem5 Developers return decodeNeonCopy(machInst); 154810037SARM gem5 Developers } else if (bits(machInst, 29) == 1) { 154910037SARM gem5 Developers return decodeNeonExt(machInst); 155010037SARM gem5 Developers } else if (bits(machInst, 11) == 1) { 155110037SARM gem5 Developers return decodeNeonZipUzpTrn(machInst); 155210037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0x0) { 155310037SARM gem5 Developers return decodeNeonTblTbx(machInst); 155410037SARM gem5 Developers } else { 155510037SARM gem5 Developers return new Unknown64(machInst); 155610037SARM gem5 Developers } 155710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case3", machInst); 155810037SARM gem5 Developers } 155910037SARM gem5 Developers} 156010037SARM gem5 Developers}}; 156110037SARM gem5 Developers 156210037SARM gem5 Developers 156310037SARM gem5 Developersoutput decoder {{ 156410037SARM gem5 Developersnamespace Aarch64 156510037SARM gem5 Developers{ 156610037SARM gem5 Developers StaticInstPtr 156710037SARM gem5 Developers // bit 30=0, 28:25=1111 156810037SARM gem5 Developers decodeFp(ExtMachInst machInst) 156910037SARM gem5 Developers { 157010037SARM gem5 Developers if (bits(machInst, 24) == 1) { 157110037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 157210037SARM gem5 Developers return new Unknown64(machInst); 157310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 157410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 157510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 157610037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 157710037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 157810037SARM gem5 Developers (bits(machInst, 15) << 0); 157910037SARM gem5 Developers switch (switchVal) { 158010037SARM gem5 Developers case 0x0: // FMADD Sd = Sa + Sn*Sm 158110037SARM gem5 Developers return new FMAddS(machInst, rd, rn, rm, ra); 158210037SARM gem5 Developers case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 158310037SARM gem5 Developers return new FMSubS(machInst, rd, rn, rm, ra); 158410037SARM gem5 Developers case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 158510037SARM gem5 Developers return new FNMAddS(machInst, rd, rn, rm, ra); 158610037SARM gem5 Developers case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 158710037SARM gem5 Developers return new FNMSubS(machInst, rd, rn, rm, ra); 158810037SARM gem5 Developers case 0x4: // FMADD Dd = Da + Dn*Dm 158910037SARM gem5 Developers return new FMAddD(machInst, rd, rn, rm, ra); 159010037SARM gem5 Developers case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 159110037SARM gem5 Developers return new FMSubD(machInst, rd, rn, rm, ra); 159210037SARM gem5 Developers case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 159310037SARM gem5 Developers return new FNMAddD(machInst, rd, rn, rm, ra); 159410037SARM gem5 Developers case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 159510037SARM gem5 Developers return new FNMSubD(machInst, rd, rn, rm, ra); 159610037SARM gem5 Developers default: 159710037SARM gem5 Developers return new Unknown64(machInst); 159810037SARM gem5 Developers } 159910037SARM gem5 Developers } else if (bits(machInst, 21) == 0) { 160010037SARM gem5 Developers bool s = bits(machInst, 29); 160110037SARM gem5 Developers if (s) 160210037SARM gem5 Developers return new Unknown64(machInst); 160310037SARM gem5 Developers uint8_t switchVal = bits(machInst, 20, 16); 160410037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 160510037SARM gem5 Developers uint8_t scale = bits(machInst, 15, 10); 160610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 160710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 160810037SARM gem5 Developers if (bits(machInst, 18, 17) == 3 && scale != 0) 160910037SARM gem5 Developers return new Unknown64(machInst); 161010037SARM gem5 Developers // 30:24=0011110, 21=0 161110037SARM gem5 Developers switch (switchVal) { 161210037SARM gem5 Developers case 0x00: 161310037SARM gem5 Developers return new FailUnimplemented("fcvtns", machInst); 161410037SARM gem5 Developers case 0x01: 161510037SARM gem5 Developers return new FailUnimplemented("fcvtnu", machInst); 161610037SARM gem5 Developers case 0x02: 161710037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 161810037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 161910037SARM gem5 Developers return new FcvtSFixedFpSW(machInst, rd, rn, scale); 162010037SARM gem5 Developers case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 162110037SARM gem5 Developers return new FcvtSFixedFpDW(machInst, rd, rn, scale); 162210037SARM gem5 Developers case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 162310037SARM gem5 Developers return new FcvtSFixedFpSX(machInst, rd, rn, scale); 162410037SARM gem5 Developers case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 162510037SARM gem5 Developers return new FcvtSFixedFpDX(machInst, rd, rn, scale); 162610037SARM gem5 Developers default: 162710037SARM gem5 Developers return new Unknown64(machInst); 162810037SARM gem5 Developers } 162910037SARM gem5 Developers case 0x03: 163010037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 163110037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 163210037SARM gem5 Developers return new FcvtUFixedFpSW(machInst, rd, rn, scale); 163310037SARM gem5 Developers case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 163410037SARM gem5 Developers return new FcvtUFixedFpDW(machInst, rd, rn, scale); 163510037SARM gem5 Developers case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 163610037SARM gem5 Developers return new FcvtUFixedFpSX(machInst, rd, rn, scale); 163710037SARM gem5 Developers case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 163810037SARM gem5 Developers return new FcvtUFixedFpDX(machInst, rd, rn, scale); 163910037SARM gem5 Developers default: 164010037SARM gem5 Developers return new Unknown64(machInst); 164110037SARM gem5 Developers } 164210037SARM gem5 Developers case 0x04: 164310037SARM gem5 Developers return new FailUnimplemented("fcvtas", machInst); 164410037SARM gem5 Developers case 0x05: 164510037SARM gem5 Developers return new FailUnimplemented("fcvtau", machInst); 164610037SARM gem5 Developers case 0x08: 164710037SARM gem5 Developers return new FailUnimplemented("fcvtps", machInst); 164810037SARM gem5 Developers case 0x09: 164910037SARM gem5 Developers return new FailUnimplemented("fcvtpu", machInst); 165010037SARM gem5 Developers case 0x0e: 165110037SARM gem5 Developers return new FailUnimplemented("fmov elem. to 64", machInst); 165210037SARM gem5 Developers case 0x0f: 165310037SARM gem5 Developers return new FailUnimplemented("fmov 64 bit", machInst); 165410037SARM gem5 Developers case 0x10: 165510037SARM gem5 Developers return new FailUnimplemented("fcvtms", machInst); 165610037SARM gem5 Developers case 0x11: 165710037SARM gem5 Developers return new FailUnimplemented("fcvtmu", machInst); 165810037SARM gem5 Developers case 0x18: 165910037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 166010037SARM gem5 Developers case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 166110037SARM gem5 Developers return new FcvtFpSFixedSW(machInst, rd, rn, scale); 166210037SARM gem5 Developers case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 166310037SARM gem5 Developers return new FcvtFpSFixedDW(machInst, rd, rn, scale); 166410037SARM gem5 Developers case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 166510037SARM gem5 Developers return new FcvtFpSFixedSX(machInst, rd, rn, scale); 166610037SARM gem5 Developers case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 166710037SARM gem5 Developers return new FcvtFpSFixedDX(machInst, rd, rn, scale); 166810037SARM gem5 Developers default: 166910037SARM gem5 Developers return new Unknown64(machInst); 167010037SARM gem5 Developers } 167110037SARM gem5 Developers case 0x19: 167210037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 167310037SARM gem5 Developers case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 167410037SARM gem5 Developers return new FcvtFpUFixedSW(machInst, rd, rn, scale); 167510037SARM gem5 Developers case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 167610037SARM gem5 Developers return new FcvtFpUFixedDW(machInst, rd, rn, scale); 167710037SARM gem5 Developers case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 167810037SARM gem5 Developers return new FcvtFpUFixedSX(machInst, rd, rn, scale); 167910037SARM gem5 Developers case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 168010037SARM gem5 Developers return new FcvtFpUFixedDX(machInst, rd, rn, scale); 168110037SARM gem5 Developers default: 168210037SARM gem5 Developers return new Unknown64(machInst); 168310037SARM gem5 Developers } 168412595Ssiddhesh.poyarekar@gmail.com default: 168512595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 168610037SARM gem5 Developers } 168710037SARM gem5 Developers } else { 168810037SARM gem5 Developers // 30=0, 28:24=11110, 21=1 168910037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 169010037SARM gem5 Developers uint8_t imm8 = bits(machInst, 20, 13); 169110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 169210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 169310037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 169410037SARM gem5 Developers case 0x0: 169510037SARM gem5 Developers if (bits(machInst, 12) == 1) { 169610037SARM gem5 Developers if (bits(machInst, 31) || 169710037SARM gem5 Developers bits(machInst, 29) || 169810037SARM gem5 Developers bits(machInst, 9, 5)) { 169910037SARM gem5 Developers return new Unknown64(machInst); 170010037SARM gem5 Developers } 170110037SARM gem5 Developers // 31:29=000, 28:24=11110, 21=1, 12:10=100 170210037SARM gem5 Developers if (type == 0) { 170310037SARM gem5 Developers // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 170410037SARM gem5 Developers // :imm8<5:0>:Zeros(19) 170513120SEdmund.Grimley-Evans@arm.com uint32_t imm = vfp_modified_imm(imm8, 170613120SEdmund.Grimley-Evans@arm.com FpDataType::Fp32); 170710037SARM gem5 Developers return new FmovImmS(machInst, rd, imm); 170810037SARM gem5 Developers } else if (type == 1) { 170910037SARM gem5 Developers // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 171010037SARM gem5 Developers // :imm8<5:0>:Zeros(48) 171113120SEdmund.Grimley-Evans@arm.com uint64_t imm = vfp_modified_imm(imm8, 171213120SEdmund.Grimley-Evans@arm.com FpDataType::Fp64); 171310037SARM gem5 Developers return new FmovImmD(machInst, rd, imm); 171410037SARM gem5 Developers } else { 171510037SARM gem5 Developers return new Unknown64(machInst); 171610037SARM gem5 Developers } 171710037SARM gem5 Developers } else if (bits(machInst, 13) == 1) { 171810037SARM gem5 Developers if (bits(machInst, 31) || 171910037SARM gem5 Developers bits(machInst, 29) || 172010037SARM gem5 Developers bits(machInst, 15, 14) || 172110037SARM gem5 Developers bits(machInst, 23) || 172210037SARM gem5 Developers bits(machInst, 2, 0)) { 172310037SARM gem5 Developers return new Unknown64(machInst); 172410037SARM gem5 Developers } 172510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 172610037SARM gem5 Developers (bits(machInst, 22) << 2); 172710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) 172810037SARM gem5 Developers bits(machInst, 20, 16); 172910037SARM gem5 Developers // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 173010037SARM gem5 Developers switch (switchVal) { 173110037SARM gem5 Developers case 0x0: 173210037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,Sm) 173310037SARM gem5 Developers return new FCmpRegS(machInst, rn, rm); 173410037SARM gem5 Developers case 0x1: 173510037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,0.0) 173610037SARM gem5 Developers return new FCmpImmS(machInst, rn, 0); 173710037SARM gem5 Developers case 0x2: 173810037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,Sm) 173910037SARM gem5 Developers return new FCmpERegS(machInst, rn, rm); 174010037SARM gem5 Developers case 0x3: 174110037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,0.0) 174210037SARM gem5 Developers return new FCmpEImmS(machInst, rn, 0); 174310037SARM gem5 Developers case 0x4: 174410037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,Dm) 174510037SARM gem5 Developers return new FCmpRegD(machInst, rn, rm); 174610037SARM gem5 Developers case 0x5: 174710037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,0.0) 174810037SARM gem5 Developers return new FCmpImmD(machInst, rn, 0); 174910037SARM gem5 Developers case 0x6: 175010037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,Dm) 175110037SARM gem5 Developers return new FCmpERegD(machInst, rn, rm); 175210037SARM gem5 Developers case 0x7: 175310037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,0.0) 175410037SARM gem5 Developers return new FCmpEImmD(machInst, rn, 0); 175510037SARM gem5 Developers default: 175610037SARM gem5 Developers return new Unknown64(machInst); 175710037SARM gem5 Developers } 175810037SARM gem5 Developers } else if (bits(machInst, 14) == 1) { 175910037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 176010037SARM gem5 Developers return new Unknown64(machInst); 176110037SARM gem5 Developers uint8_t opcode = bits(machInst, 20, 15); 176210037SARM gem5 Developers // Bits 31:24=00011110, 21=1, 14:10=10000 176310037SARM gem5 Developers switch (opcode) { 176410037SARM gem5 Developers case 0x0: 176510037SARM gem5 Developers if (type == 0) 176610037SARM gem5 Developers // FMOV Sd = Sn 176710037SARM gem5 Developers return new FmovRegS(machInst, rd, rn); 176810037SARM gem5 Developers else if (type == 1) 176910037SARM gem5 Developers // FMOV Dd = Dn 177010037SARM gem5 Developers return new FmovRegD(machInst, rd, rn); 177110037SARM gem5 Developers break; 177210037SARM gem5 Developers case 0x1: 177310037SARM gem5 Developers if (type == 0) 177410037SARM gem5 Developers // FABS Sd = abs(Sn) 177510037SARM gem5 Developers return new FAbsS(machInst, rd, rn); 177610037SARM gem5 Developers else if (type == 1) 177710037SARM gem5 Developers // FABS Dd = abs(Dn) 177810037SARM gem5 Developers return new FAbsD(machInst, rd, rn); 177910037SARM gem5 Developers break; 178010037SARM gem5 Developers case 0x2: 178110037SARM gem5 Developers if (type == 0) 178210037SARM gem5 Developers // FNEG Sd = -Sn 178310037SARM gem5 Developers return new FNegS(machInst, rd, rn); 178410037SARM gem5 Developers else if (type == 1) 178510037SARM gem5 Developers // FNEG Dd = -Dn 178610037SARM gem5 Developers return new FNegD(machInst, rd, rn); 178710037SARM gem5 Developers break; 178810037SARM gem5 Developers case 0x3: 178910037SARM gem5 Developers if (type == 0) 179010037SARM gem5 Developers // FSQRT Sd = sqrt(Sn) 179110037SARM gem5 Developers return new FSqrtS(machInst, rd, rn); 179210037SARM gem5 Developers else if (type == 1) 179310037SARM gem5 Developers // FSQRT Dd = sqrt(Dn) 179410037SARM gem5 Developers return new FSqrtD(machInst, rd, rn); 179510037SARM gem5 Developers break; 179610037SARM gem5 Developers case 0x4: 179710037SARM gem5 Developers if (type == 1) 179810037SARM gem5 Developers // FCVT Sd = convertFormat(Dn) 179910037SARM gem5 Developers return new FcvtFpDFpS(machInst, rd, rn); 180010037SARM gem5 Developers else if (type == 3) 180110037SARM gem5 Developers // FCVT Sd = convertFormat(Hn) 180210037SARM gem5 Developers return new FcvtFpHFpS(machInst, rd, rn); 180310037SARM gem5 Developers break; 180410037SARM gem5 Developers case 0x5: 180510037SARM gem5 Developers if (type == 0) 180610037SARM gem5 Developers // FCVT Dd = convertFormat(Sn) 180710037SARM gem5 Developers return new FCvtFpSFpD(machInst, rd, rn); 180810037SARM gem5 Developers else if (type == 3) 180910037SARM gem5 Developers // FCVT Dd = convertFormat(Hn) 181010037SARM gem5 Developers return new FcvtFpHFpD(machInst, rd, rn); 181110037SARM gem5 Developers break; 181210037SARM gem5 Developers case 0x7: 181310037SARM gem5 Developers if (type == 0) 181410037SARM gem5 Developers // FCVT Hd = convertFormat(Sn) 181510037SARM gem5 Developers return new FcvtFpSFpH(machInst, rd, rn); 181610037SARM gem5 Developers else if (type == 1) 181710037SARM gem5 Developers // FCVT Hd = convertFormat(Dn) 181810037SARM gem5 Developers return new FcvtFpDFpH(machInst, rd, rn); 181910037SARM gem5 Developers break; 182010037SARM gem5 Developers case 0x8: 182110037SARM gem5 Developers if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 182210037SARM gem5 Developers return new FRIntNS(machInst, rd, rn); 182310037SARM gem5 Developers else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 182410037SARM gem5 Developers return new FRIntND(machInst, rd, rn); 182510037SARM gem5 Developers break; 182610037SARM gem5 Developers case 0x9: 182710037SARM gem5 Developers if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 182810037SARM gem5 Developers return new FRIntPS(machInst, rd, rn); 182910037SARM gem5 Developers else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 183010037SARM gem5 Developers return new FRIntPD(machInst, rd, rn); 183110037SARM gem5 Developers break; 183210037SARM gem5 Developers case 0xa: 183310037SARM gem5 Developers if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 183410037SARM gem5 Developers return new FRIntMS(machInst, rd, rn); 183510037SARM gem5 Developers else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 183610037SARM gem5 Developers return new FRIntMD(machInst, rd, rn); 183710037SARM gem5 Developers break; 183810037SARM gem5 Developers case 0xb: 183910037SARM gem5 Developers if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 184010037SARM gem5 Developers return new FRIntZS(machInst, rd, rn); 184110037SARM gem5 Developers else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 184210037SARM gem5 Developers return new FRIntZD(machInst, rd, rn); 184310037SARM gem5 Developers break; 184410037SARM gem5 Developers case 0xc: 184510037SARM gem5 Developers if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 184610037SARM gem5 Developers return new FRIntAS(machInst, rd, rn); 184710037SARM gem5 Developers else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 184810037SARM gem5 Developers return new FRIntAD(machInst, rd, rn); 184910037SARM gem5 Developers break; 185010037SARM gem5 Developers case 0xe: 185110037SARM gem5 Developers if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 185210037SARM gem5 Developers return new FRIntXS(machInst, rd, rn); 185310037SARM gem5 Developers else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 185410037SARM gem5 Developers return new FRIntXD(machInst, rd, rn); 185510037SARM gem5 Developers break; 185610037SARM gem5 Developers case 0xf: 185710037SARM gem5 Developers if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 185810037SARM gem5 Developers return new FRIntIS(machInst, rd, rn); 185910037SARM gem5 Developers else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 186010037SARM gem5 Developers return new FRIntID(machInst, rd, rn); 186110037SARM gem5 Developers break; 186210037SARM gem5 Developers default: 186310037SARM gem5 Developers return new Unknown64(machInst); 186410037SARM gem5 Developers } 186510037SARM gem5 Developers return new Unknown64(machInst); 186610037SARM gem5 Developers } else if (bits(machInst, 15) == 1) { 186710037SARM gem5 Developers return new Unknown64(machInst); 186810037SARM gem5 Developers } else { 186910037SARM gem5 Developers if (bits(machInst, 29)) 187010037SARM gem5 Developers return new Unknown64(machInst); 187110037SARM gem5 Developers uint8_t rmode = bits(machInst, 20, 19); 187210037SARM gem5 Developers uint8_t switchVal1 = bits(machInst, 18, 16); 187310037SARM gem5 Developers uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 187410037SARM gem5 Developers // 30:24=0011110, 21=1, 15:10=000000 187510037SARM gem5 Developers switch (switchVal1) { 187610037SARM gem5 Developers case 0x0: 187710037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 187810037SARM gem5 Developers case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 187910037SARM gem5 Developers return new FcvtFpSIntWSN(machInst, rd, rn); 188010037SARM gem5 Developers case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 188110037SARM gem5 Developers return new FcvtFpSIntWSP(machInst, rd, rn); 188210037SARM gem5 Developers case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 188310037SARM gem5 Developers return new FcvtFpSIntWSM(machInst, rd, rn); 188410037SARM gem5 Developers case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 188510037SARM gem5 Developers return new FcvtFpSIntWSZ(machInst, rd, rn); 188610037SARM gem5 Developers case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 188710037SARM gem5 Developers return new FcvtFpSIntXSN(machInst, rd, rn); 188810037SARM gem5 Developers case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 188910037SARM gem5 Developers return new FcvtFpSIntXSP(machInst, rd, rn); 189010037SARM gem5 Developers case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 189110037SARM gem5 Developers return new FcvtFpSIntXSM(machInst, rd, rn); 189210037SARM gem5 Developers case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 189310037SARM gem5 Developers return new FcvtFpSIntXSZ(machInst, rd, rn); 189410037SARM gem5 Developers case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 189510037SARM gem5 Developers return new FcvtFpSIntWDN(machInst, rd, rn); 189610037SARM gem5 Developers case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 189710037SARM gem5 Developers return new FcvtFpSIntWDP(machInst, rd, rn); 189810037SARM gem5 Developers case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 189910037SARM gem5 Developers return new FcvtFpSIntWDM(machInst, rd, rn); 190010037SARM gem5 Developers case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 190110037SARM gem5 Developers return new FcvtFpSIntWDZ(machInst, rd, rn); 190210037SARM gem5 Developers case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 190310037SARM gem5 Developers return new FcvtFpSIntXDN(machInst, rd, rn); 190410037SARM gem5 Developers case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 190510037SARM gem5 Developers return new FcvtFpSIntXDP(machInst, rd, rn); 190610037SARM gem5 Developers case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 190710037SARM gem5 Developers return new FcvtFpSIntXDM(machInst, rd, rn); 190810037SARM gem5 Developers case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 190910037SARM gem5 Developers return new FcvtFpSIntXDZ(machInst, rd, rn); 191010037SARM gem5 Developers default: 191110037SARM gem5 Developers return new Unknown64(machInst); 191210037SARM gem5 Developers } 191310037SARM gem5 Developers case 0x1: 191410037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 191510037SARM gem5 Developers case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 191610037SARM gem5 Developers return new FcvtFpUIntWSN(machInst, rd, rn); 191710037SARM gem5 Developers case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 191810037SARM gem5 Developers return new FcvtFpUIntWSP(machInst, rd, rn); 191910037SARM gem5 Developers case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 192010037SARM gem5 Developers return new FcvtFpUIntWSM(machInst, rd, rn); 192110037SARM gem5 Developers case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 192210037SARM gem5 Developers return new FcvtFpUIntWSZ(machInst, rd, rn); 192310037SARM gem5 Developers case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 192410037SARM gem5 Developers return new FcvtFpUIntXSN(machInst, rd, rn); 192510037SARM gem5 Developers case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 192610037SARM gem5 Developers return new FcvtFpUIntXSP(machInst, rd, rn); 192710037SARM gem5 Developers case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 192810037SARM gem5 Developers return new FcvtFpUIntXSM(machInst, rd, rn); 192910037SARM gem5 Developers case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 193010037SARM gem5 Developers return new FcvtFpUIntXSZ(machInst, rd, rn); 193110037SARM gem5 Developers case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 193210037SARM gem5 Developers return new FcvtFpUIntWDN(machInst, rd, rn); 193310037SARM gem5 Developers case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 193410037SARM gem5 Developers return new FcvtFpUIntWDP(machInst, rd, rn); 193510037SARM gem5 Developers case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 193610037SARM gem5 Developers return new FcvtFpUIntWDM(machInst, rd, rn); 193710037SARM gem5 Developers case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 193810037SARM gem5 Developers return new FcvtFpUIntWDZ(machInst, rd, rn); 193910037SARM gem5 Developers case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 194010037SARM gem5 Developers return new FcvtFpUIntXDN(machInst, rd, rn); 194110037SARM gem5 Developers case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 194210037SARM gem5 Developers return new FcvtFpUIntXDP(machInst, rd, rn); 194310037SARM gem5 Developers case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 194410037SARM gem5 Developers return new FcvtFpUIntXDM(machInst, rd, rn); 194510037SARM gem5 Developers case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 194610037SARM gem5 Developers return new FcvtFpUIntXDZ(machInst, rd, rn); 194710037SARM gem5 Developers default: 194810037SARM gem5 Developers return new Unknown64(machInst); 194910037SARM gem5 Developers } 195010037SARM gem5 Developers case 0x2: 195110037SARM gem5 Developers if (rmode != 0) 195210037SARM gem5 Developers return new Unknown64(machInst); 195310037SARM gem5 Developers switch (switchVal2) { 195410037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn) 195510037SARM gem5 Developers return new FcvtWSIntFpS(machInst, rd, rn); 195610037SARM gem5 Developers case 1: // SCVTF Sd = convertFromInt(Xn) 195710037SARM gem5 Developers return new FcvtXSIntFpS(machInst, rd, rn); 195810037SARM gem5 Developers case 2: // SCVTF Dd = convertFromInt(Wn) 195910037SARM gem5 Developers return new FcvtWSIntFpD(machInst, rd, rn); 196010037SARM gem5 Developers case 3: // SCVTF Dd = convertFromInt(Xn) 196110037SARM gem5 Developers return new FcvtXSIntFpD(machInst, rd, rn); 196210037SARM gem5 Developers default: 196310037SARM gem5 Developers return new Unknown64(machInst); 196410037SARM gem5 Developers } 196510037SARM gem5 Developers case 0x3: 196610037SARM gem5 Developers switch (switchVal2) { 196710037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn) 196810037SARM gem5 Developers return new FcvtWUIntFpS(machInst, rd, rn); 196910037SARM gem5 Developers case 1: // UCVTF Sd = convertFromInt(Xn) 197010037SARM gem5 Developers return new FcvtXUIntFpS(machInst, rd, rn); 197110037SARM gem5 Developers case 2: // UCVTF Dd = convertFromInt(Wn) 197210037SARM gem5 Developers return new FcvtWUIntFpD(machInst, rd, rn); 197310037SARM gem5 Developers case 3: // UCVTF Dd = convertFromInt(Xn) 197410037SARM gem5 Developers return new FcvtXUIntFpD(machInst, rd, rn); 197510037SARM gem5 Developers default: 197610037SARM gem5 Developers return new Unknown64(machInst); 197710037SARM gem5 Developers } 197810037SARM gem5 Developers case 0x4: 197910037SARM gem5 Developers if (rmode != 0) 198010037SARM gem5 Developers return new Unknown64(machInst); 198110037SARM gem5 Developers switch (switchVal2) { 198210037SARM gem5 Developers case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 198310037SARM gem5 Developers return new FcvtFpSIntWSA(machInst, rd, rn); 198410037SARM gem5 Developers case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 198510037SARM gem5 Developers return new FcvtFpSIntXSA(machInst, rd, rn); 198610037SARM gem5 Developers case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 198710037SARM gem5 Developers return new FcvtFpSIntWDA(machInst, rd, rn); 198810037SARM gem5 Developers case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 198910037SARM gem5 Developers return new FcvtFpSIntXDA(machInst, rd, rn); 199010037SARM gem5 Developers default: 199110037SARM gem5 Developers return new Unknown64(machInst); 199210037SARM gem5 Developers } 199310037SARM gem5 Developers case 0x5: 199410037SARM gem5 Developers switch (switchVal2) { 199510037SARM gem5 Developers case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 199610037SARM gem5 Developers return new FcvtFpUIntWSA(machInst, rd, rn); 199710037SARM gem5 Developers case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 199810037SARM gem5 Developers return new FcvtFpUIntXSA(machInst, rd, rn); 199910037SARM gem5 Developers case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 200010037SARM gem5 Developers return new FcvtFpUIntWDA(machInst, rd, rn); 200110037SARM gem5 Developers case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 200210037SARM gem5 Developers return new FcvtFpUIntXDA(machInst, rd, rn); 200310037SARM gem5 Developers default: 200410037SARM gem5 Developers return new Unknown64(machInst); 200510037SARM gem5 Developers } 200610037SARM gem5 Developers case 0x06: 200710037SARM gem5 Developers switch (switchVal2) { 200810037SARM gem5 Developers case 0: // FMOV Wd = Sn 200910037SARM gem5 Developers if (rmode != 0) 201010037SARM gem5 Developers return new Unknown64(machInst); 201110037SARM gem5 Developers return new FmovRegCoreW(machInst, rd, rn); 201210037SARM gem5 Developers case 3: // FMOV Xd = Dn 201310037SARM gem5 Developers if (rmode != 0) 201410037SARM gem5 Developers return new Unknown64(machInst); 201510037SARM gem5 Developers return new FmovRegCoreX(machInst, rd, rn); 201610037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 201710037SARM gem5 Developers if (rmode != 1) 201810037SARM gem5 Developers return new Unknown64(machInst); 201910037SARM gem5 Developers return new FmovURegCoreX(machInst, rd, rn); 202010037SARM gem5 Developers default: 202110037SARM gem5 Developers return new Unknown64(machInst); 202210037SARM gem5 Developers } 202310037SARM gem5 Developers break; 202410037SARM gem5 Developers case 0x07: 202510037SARM gem5 Developers switch (switchVal2) { 202610037SARM gem5 Developers case 0: // FMOV Sd = Wn 202710037SARM gem5 Developers if (rmode != 0) 202810037SARM gem5 Developers return new Unknown64(machInst); 202910037SARM gem5 Developers return new FmovCoreRegW(machInst, rd, rn); 203010037SARM gem5 Developers case 3: // FMOV Xd = Dn 203110037SARM gem5 Developers if (rmode != 0) 203210037SARM gem5 Developers return new Unknown64(machInst); 203310037SARM gem5 Developers return new FmovCoreRegX(machInst, rd, rn); 203410037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 203510037SARM gem5 Developers if (rmode != 1) 203610037SARM gem5 Developers return new Unknown64(machInst); 203710037SARM gem5 Developers return new FmovUCoreRegX(machInst, rd, rn); 203810037SARM gem5 Developers default: 203910037SARM gem5 Developers return new Unknown64(machInst); 204010037SARM gem5 Developers } 204110037SARM gem5 Developers break; 204210037SARM gem5 Developers default: // Warning! missing cases in switch statement above, that still need to be added 204310037SARM gem5 Developers return new Unknown64(machInst); 204410037SARM gem5 Developers } 204510037SARM gem5 Developers } 204612597Schunchenhsu@google.com M5_UNREACHABLE; 204710037SARM gem5 Developers case 0x1: 204810037SARM gem5 Developers { 204910037SARM gem5 Developers if (bits(machInst, 31) || 205010037SARM gem5 Developers bits(machInst, 29) || 205110037SARM gem5 Developers bits(machInst, 23)) { 205210037SARM gem5 Developers return new Unknown64(machInst); 205310037SARM gem5 Developers } 205410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 205510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 205610037SARM gem5 Developers uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 205710037SARM gem5 Developers ConditionCode cond = 205810037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 205910037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4) << 0) | 206010037SARM gem5 Developers (bits(machInst, 22) << 1); 206110037SARM gem5 Developers // 31:23=000111100, 21=1, 11:10=01 206210037SARM gem5 Developers switch (switchVal) { 206310037SARM gem5 Developers case 0x0: 206410037SARM gem5 Developers // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 206510037SARM gem5 Developers return new FCCmpRegS(machInst, rn, rm, cond, imm); 206610037SARM gem5 Developers case 0x1: 206710037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Sn,Sm) 206810037SARM gem5 Developers // else #nzcv 206910037SARM gem5 Developers return new FCCmpERegS(machInst, rn, rm, cond, imm); 207010037SARM gem5 Developers case 0x2: 207110037SARM gem5 Developers // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 207210037SARM gem5 Developers return new FCCmpRegD(machInst, rn, rm, cond, imm); 207310037SARM gem5 Developers case 0x3: 207410037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Dn,Dm) 207510037SARM gem5 Developers // else #nzcv 207610037SARM gem5 Developers return new FCCmpERegD(machInst, rn, rm, cond, imm); 207710037SARM gem5 Developers default: 207810037SARM gem5 Developers return new Unknown64(machInst); 207910037SARM gem5 Developers } 208010037SARM gem5 Developers } 208110037SARM gem5 Developers case 0x2: 208210037SARM gem5 Developers { 208310037SARM gem5 Developers if (bits(machInst, 31) || 208410037SARM gem5 Developers bits(machInst, 29) || 208510037SARM gem5 Developers bits(machInst, 23)) { 208610037SARM gem5 Developers return new Unknown64(machInst); 208710037SARM gem5 Developers } 208810037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 208910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 209010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 209110037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 209210037SARM gem5 Developers (bits(machInst, 22) << 4); 209310037SARM gem5 Developers switch (switchVal) { 209410037SARM gem5 Developers case 0x00: // FMUL Sd = Sn * Sm 209510037SARM gem5 Developers return new FMulS(machInst, rd, rn, rm); 209610037SARM gem5 Developers case 0x10: // FMUL Dd = Dn * Dm 209710037SARM gem5 Developers return new FMulD(machInst, rd, rn, rm); 209810037SARM gem5 Developers case 0x01: // FDIV Sd = Sn / Sm 209910037SARM gem5 Developers return new FDivS(machInst, rd, rn, rm); 210010037SARM gem5 Developers case 0x11: // FDIV Dd = Dn / Dm 210110037SARM gem5 Developers return new FDivD(machInst, rd, rn, rm); 210210037SARM gem5 Developers case 0x02: // FADD Sd = Sn + Sm 210310037SARM gem5 Developers return new FAddS(machInst, rd, rn, rm); 210410037SARM gem5 Developers case 0x12: // FADD Dd = Dn + Dm 210510037SARM gem5 Developers return new FAddD(machInst, rd, rn, rm); 210610037SARM gem5 Developers case 0x03: // FSUB Sd = Sn - Sm 210710037SARM gem5 Developers return new FSubS(machInst, rd, rn, rm); 210810037SARM gem5 Developers case 0x13: // FSUB Dd = Dn - Dm 210910037SARM gem5 Developers return new FSubD(machInst, rd, rn, rm); 211010037SARM gem5 Developers case 0x04: // FMAX Sd = max(Sn, Sm) 211110037SARM gem5 Developers return new FMaxS(machInst, rd, rn, rm); 211210037SARM gem5 Developers case 0x14: // FMAX Dd = max(Dn, Dm) 211310037SARM gem5 Developers return new FMaxD(machInst, rd, rn, rm); 211410037SARM gem5 Developers case 0x05: // FMIN Sd = min(Sn, Sm) 211510037SARM gem5 Developers return new FMinS(machInst, rd, rn, rm); 211610037SARM gem5 Developers case 0x15: // FMIN Dd = min(Dn, Dm) 211710037SARM gem5 Developers return new FMinD(machInst, rd, rn, rm); 211810037SARM gem5 Developers case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 211910037SARM gem5 Developers return new FMaxNMS(machInst, rd, rn, rm); 212010037SARM gem5 Developers case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 212110037SARM gem5 Developers return new FMaxNMD(machInst, rd, rn, rm); 212210037SARM gem5 Developers case 0x07: // FMINNM Sd = minNum(Sn, Sm) 212310037SARM gem5 Developers return new FMinNMS(machInst, rd, rn, rm); 212410037SARM gem5 Developers case 0x17: // FMINNM Dd = minNum(Dn, Dm) 212510037SARM gem5 Developers return new FMinNMD(machInst, rd, rn, rm); 212610037SARM gem5 Developers case 0x08: // FNMUL Sd = -(Sn * Sm) 212710037SARM gem5 Developers return new FNMulS(machInst, rd, rn, rm); 212810037SARM gem5 Developers case 0x18: // FNMUL Dd = -(Dn * Dm) 212910037SARM gem5 Developers return new FNMulD(machInst, rd, rn, rm); 213010037SARM gem5 Developers default: 213110037SARM gem5 Developers return new Unknown64(machInst); 213210037SARM gem5 Developers } 213310037SARM gem5 Developers } 213410037SARM gem5 Developers case 0x3: 213510037SARM gem5 Developers { 213610037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 213710037SARM gem5 Developers return new Unknown64(machInst); 213810037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 213910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 214010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 214110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 214210037SARM gem5 Developers ConditionCode cond = 214310037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 214410037SARM gem5 Developers if (type == 0) // FCSEL Sd = if cond then Sn else Sm 214510037SARM gem5 Developers return new FCSelS(machInst, rd, rn, rm, cond); 214610037SARM gem5 Developers else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 214710037SARM gem5 Developers return new FCSelD(machInst, rd, rn, rm, cond); 214810037SARM gem5 Developers else 214910037SARM gem5 Developers return new Unknown64(machInst); 215010037SARM gem5 Developers } 215112595Ssiddhesh.poyarekar@gmail.com default: 215212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 215310037SARM gem5 Developers } 215410037SARM gem5 Developers } 215512597Schunchenhsu@google.com M5_UNREACHABLE; 215610037SARM gem5 Developers } 215710037SARM gem5 Developers} 215810037SARM gem5 Developers}}; 215910037SARM gem5 Developers 216010037SARM gem5 Developersoutput decoder {{ 216110037SARM gem5 Developersnamespace Aarch64 216210037SARM gem5 Developers{ 216310037SARM gem5 Developers StaticInstPtr 216410037SARM gem5 Developers decodeAdvSIMDScalar(ExtMachInst machInst) 216510037SARM gem5 Developers { 216610037SARM gem5 Developers if (bits(machInst, 24) == 1) { 216710037SARM gem5 Developers if (bits(machInst, 10) == 0) { 216810037SARM gem5 Developers return decodeNeonScIndexedElem(machInst); 216910037SARM gem5 Developers } else if (bits(machInst, 23) == 0) { 217010037SARM gem5 Developers return decodeNeonScShiftByImm(machInst); 217110037SARM gem5 Developers } 217210037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 217310037SARM gem5 Developers if (bits(machInst, 10) == 1) { 217410037SARM gem5 Developers return decodeNeonSc3Same(machInst); 217510037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 217610037SARM gem5 Developers return decodeNeonSc3Diff(machInst); 217710037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 217810037SARM gem5 Developers return decodeNeonSc2RegMisc(machInst); 217913170Sgiacomo.travaglini@arm.com } else if (bits(machInst, 20, 17) == 0x4) { 218013170Sgiacomo.travaglini@arm.com return decodeCryptoTwoRegSHA(machInst); 218110037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 218210037SARM gem5 Developers return decodeNeonScPwise(machInst); 218310037SARM gem5 Developers } else { 218410037SARM gem5 Developers return new Unknown64(machInst); 218510037SARM gem5 Developers } 218610037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0 && 218713170Sgiacomo.travaglini@arm.com bits(machInst, 15) == 0) { 218813170Sgiacomo.travaglini@arm.com if (bits(machInst, 10) == 1) { 218913170Sgiacomo.travaglini@arm.com return decodeNeonScCopy(machInst); 219013170Sgiacomo.travaglini@arm.com } else { 219113170Sgiacomo.travaglini@arm.com return decodeCryptoThreeRegSHA(machInst); 219213170Sgiacomo.travaglini@arm.com } 219310037SARM gem5 Developers } else { 219410037SARM gem5 Developers return new Unknown64(machInst); 219510037SARM gem5 Developers } 219610037SARM gem5 Developers return new FailUnimplemented("Unhandled Case6", machInst); 219710037SARM gem5 Developers } 219810037SARM gem5 Developers} 219910037SARM gem5 Developers}}; 220010037SARM gem5 Developers 220110037SARM gem5 Developersoutput decoder {{ 220210037SARM gem5 Developersnamespace Aarch64 220310037SARM gem5 Developers{ 220411165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 220510037SARM gem5 Developers StaticInstPtr 220610037SARM gem5 Developers decodeFpAdvSIMD(ExtMachInst machInst) 220710037SARM gem5 Developers { 220810037SARM gem5 Developers 220910037SARM gem5 Developers if (bits(machInst, 28) == 0) { 221010037SARM gem5 Developers if (bits(machInst, 31) == 0) { 221111165SRekai.GonzalezAlberquilla@arm.com return decodeAdvSIMD<DecoderFeatures>(machInst); 221210037SARM gem5 Developers } else { 221310037SARM gem5 Developers return new Unknown64(machInst); 221410037SARM gem5 Developers } 221510037SARM gem5 Developers } else if (bits(machInst, 30) == 0) { 221610037SARM gem5 Developers return decodeFp(machInst); 221710037SARM gem5 Developers } else if (bits(machInst, 31) == 0) { 221810037SARM gem5 Developers return decodeAdvSIMDScalar(machInst); 221910037SARM gem5 Developers } else { 222010037SARM gem5 Developers return new Unknown64(machInst); 222110037SARM gem5 Developers } 222210037SARM gem5 Developers } 222310037SARM gem5 Developers} 222410037SARM gem5 Developers}}; 222510037SARM gem5 Developers 222611165SRekai.GonzalezAlberquilla@arm.comlet {{ 222711165SRekai.GonzalezAlberquilla@arm.com decoder_output =''' 222811165SRekai.GonzalezAlberquilla@arm.comnamespace Aarch64 222911165SRekai.GonzalezAlberquilla@arm.com{''' 223011165SRekai.GonzalezAlberquilla@arm.com for decoderFlavour, type_dict in decoders.iteritems(): 223111165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 223211165SRekai.GonzalezAlberquilla@arm.comtemplate StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); 223311165SRekai.GonzalezAlberquilla@arm.com''' % { "df" : decoderFlavour } 223411165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 223511165SRekai.GonzalezAlberquilla@arm.com}''' 223611165SRekai.GonzalezAlberquilla@arm.com}}; 223711165SRekai.GonzalezAlberquilla@arm.com 223810037SARM gem5 Developersoutput decoder {{ 223910037SARM gem5 Developersnamespace Aarch64 224010037SARM gem5 Developers{ 224110037SARM gem5 Developers StaticInstPtr 224210037SARM gem5 Developers decodeGem5Ops(ExtMachInst machInst) 224310037SARM gem5 Developers { 224410037SARM gem5 Developers const uint32_t m5func = bits(machInst, 23, 16); 224510037SARM gem5 Developers switch (m5func) { 224612159Sandreas.sandberg@arm.com case M5OP_ARM: return new Arm(machInst); 224712159Sandreas.sandberg@arm.com case M5OP_QUIESCE: return new Quiesce(machInst); 224812159Sandreas.sandberg@arm.com case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst); 224912159Sandreas.sandberg@arm.com case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst); 225012159Sandreas.sandberg@arm.com case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst); 225112159Sandreas.sandberg@arm.com case M5OP_RPNS: return new Rpns64(machInst); 225212159Sandreas.sandberg@arm.com case M5OP_WAKE_CPU: return new WakeCPU64(machInst); 225312159Sandreas.sandberg@arm.com case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); 225412159Sandreas.sandberg@arm.com case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); 225512159Sandreas.sandberg@arm.com case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); 225612159Sandreas.sandberg@arm.com case M5OP_EXIT: return new M5exit64(machInst); 225712159Sandreas.sandberg@arm.com case M5OP_FAIL: return new M5fail64(machInst); 225812159Sandreas.sandberg@arm.com case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); 225912159Sandreas.sandberg@arm.com case M5OP_INIT_PARAM: return new Initparam64(machInst); 226012159Sandreas.sandberg@arm.com case M5OP_RESET_STATS: return new Resetstats64(machInst); 226112159Sandreas.sandberg@arm.com case M5OP_DUMP_STATS: return new Dumpstats64(machInst); 226212159Sandreas.sandberg@arm.com case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst); 226312159Sandreas.sandberg@arm.com case M5OP_CHECKPOINT: return new M5checkpoint64(machInst); 226412159Sandreas.sandberg@arm.com case M5OP_WRITE_FILE: return new M5writefile64(machInst); 226512159Sandreas.sandberg@arm.com case M5OP_READ_FILE: return new M5readfile64(machInst); 226612159Sandreas.sandberg@arm.com case M5OP_DEBUG_BREAK: return new M5break(machInst); 226712159Sandreas.sandberg@arm.com case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); 226812159Sandreas.sandberg@arm.com case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst); 226912159Sandreas.sandberg@arm.com case M5OP_PANIC: return new M5panic(machInst); 227012159Sandreas.sandberg@arm.com case M5OP_WORK_BEGIN: return new M5workbegin64(machInst); 227112159Sandreas.sandberg@arm.com case M5OP_WORK_END: return new M5workend64(machInst); 227210037SARM gem5 Developers default: return new Unknown64(machInst); 227310037SARM gem5 Developers } 227410037SARM gem5 Developers } 227510037SARM gem5 Developers} 227610037SARM gem5 Developers}}; 227710037SARM gem5 Developers 227810037SARM gem5 Developersdef format Aarch64() {{ 227910037SARM gem5 Developers decode_block = ''' 228010037SARM gem5 Developers { 228110037SARM gem5 Developers using namespace Aarch64; 228210037SARM gem5 Developers if (bits(machInst, 27) == 0x0) { 228310037SARM gem5 Developers if (bits(machInst, 28) == 0x0) 228410037SARM gem5 Developers return new Unknown64(machInst); 228510037SARM gem5 Developers else if (bits(machInst, 26) == 0) 228610037SARM gem5 Developers // bit 28:26=100 228710037SARM gem5 Developers return decodeDataProcImm(machInst); 228810037SARM gem5 Developers else 228910037SARM gem5 Developers // bit 28:26=101 229010037SARM gem5 Developers return decodeBranchExcSys(machInst); 229110037SARM gem5 Developers } else if (bits(machInst, 25) == 0) { 229210037SARM gem5 Developers // bit 27=1, 25=0 229310037SARM gem5 Developers return decodeLoadsStores(machInst); 229410037SARM gem5 Developers } else if (bits(machInst, 26) == 0) { 229510037SARM gem5 Developers // bit 27:25=101 229610037SARM gem5 Developers return decodeDataProcReg(machInst); 229710037SARM gem5 Developers } else if (bits(machInst, 24) == 1 && 229810037SARM gem5 Developers bits(machInst, 31, 28) == 0xF) { 229910037SARM gem5 Developers return decodeGem5Ops(machInst); 230010037SARM gem5 Developers } else { 230110037SARM gem5 Developers // bit 27:25=111 230211165SRekai.GonzalezAlberquilla@arm.com switch(decoderFlavour){ 230311165SRekai.GonzalezAlberquilla@arm.com default: 230411165SRekai.GonzalezAlberquilla@arm.com return decodeFpAdvSIMD<GenericDecoder>(machInst); 230511165SRekai.GonzalezAlberquilla@arm.com } 230610037SARM gem5 Developers } 230710037SARM gem5 Developers } 230810037SARM gem5 Developers ''' 230910037SARM gem5 Developers}}; 2310