aarch64.isa revision 13171
112531Sandreas.sandberg@arm.com// Copyright (c) 2011-2018 ARM Limited 210037SARM gem5 Developers// All rights reserved 310037SARM gem5 Developers// 410037SARM gem5 Developers// The license below extends only to copyright in the software and shall 510037SARM gem5 Developers// not be construed as granting a license to any other intellectual 610037SARM gem5 Developers// property including but not limited to intellectual property relating 710037SARM gem5 Developers// to a hardware implementation of the functionality of the software 810037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers// 1310037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1410037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1510037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1610037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1710037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1910037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2010037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2110037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2210037SARM gem5 Developers// this software without specific prior written permission. 2310037SARM gem5 Developers// 2410037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510037SARM gem5 Developers// 3610037SARM gem5 Developers// Authors: Gabe Black 3710037SARM gem5 Developers// Thomas Grocutt 3810037SARM gem5 Developers// Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developersoutput header {{ 4210037SARM gem5 Developersnamespace Aarch64 4310037SARM gem5 Developers{ 4410037SARM gem5 Developers StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 4510037SARM gem5 Developers StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 4610037SARM gem5 Developers StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 4710037SARM gem5 Developers StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 4810037SARM gem5 Developers 4911165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5010037SARM gem5 Developers StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 5110037SARM gem5 Developers StaticInstPtr decodeFp(ExtMachInst machInst); 5211165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5310037SARM gem5 Developers StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 5410037SARM gem5 Developers StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 5510037SARM gem5 Developers 5610037SARM gem5 Developers StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 5710037SARM gem5 Developers} 5810037SARM gem5 Developers}}; 5910037SARM gem5 Developers 6010037SARM gem5 Developersoutput decoder {{ 6110037SARM gem5 Developersnamespace Aarch64 6210037SARM gem5 Developers{ 6310037SARM gem5 Developers StaticInstPtr 6410037SARM gem5 Developers decodeDataProcImm(ExtMachInst machInst) 6510037SARM gem5 Developers { 6610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 6710037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 6810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 6910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 7010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 7110037SARM gem5 Developers 7210037SARM gem5 Developers uint8_t opc = bits(machInst, 30, 29); 7310037SARM gem5 Developers bool sf = bits(machInst, 31); 7410037SARM gem5 Developers bool n = bits(machInst, 22); 7510037SARM gem5 Developers uint8_t immr = bits(machInst, 21, 16); 7610037SARM gem5 Developers uint8_t imms = bits(machInst, 15, 10); 7710037SARM gem5 Developers switch (bits(machInst, 25, 23)) { 7810037SARM gem5 Developers case 0x0: 7910037SARM gem5 Developers case 0x1: 8010037SARM gem5 Developers { 8110037SARM gem5 Developers uint64_t immlo = bits(machInst, 30, 29); 8210037SARM gem5 Developers uint64_t immhi = bits(machInst, 23, 5); 8310037SARM gem5 Developers uint64_t imm = (immlo << 0) | (immhi << 2); 8410037SARM gem5 Developers if (bits(machInst, 31) == 0) 8510337SAndrew.Bardsley@arm.com return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 8610037SARM gem5 Developers else 8710337SAndrew.Bardsley@arm.com return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 8810037SARM gem5 Developers sext<33>(imm << 12)); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers case 0x2: 9110037SARM gem5 Developers case 0x3: 9210037SARM gem5 Developers { 9310037SARM gem5 Developers uint32_t imm12 = bits(machInst, 21, 10); 9410037SARM gem5 Developers uint8_t shift = bits(machInst, 23, 22); 9510037SARM gem5 Developers uint32_t imm; 9610037SARM gem5 Developers if (shift == 0x0) 9710037SARM gem5 Developers imm = imm12 << 0; 9810037SARM gem5 Developers else if (shift == 0x1) 9910037SARM gem5 Developers imm = imm12 << 12; 10010037SARM gem5 Developers else 10110037SARM gem5 Developers return new Unknown64(machInst); 10210037SARM gem5 Developers switch (opc) { 10310037SARM gem5 Developers case 0x0: 10410037SARM gem5 Developers return new AddXImm(machInst, rdsp, rnsp, imm); 10510037SARM gem5 Developers case 0x1: 10610337SAndrew.Bardsley@arm.com return new AddXImmCc(machInst, rdzr, rnsp, imm); 10710037SARM gem5 Developers case 0x2: 10810037SARM gem5 Developers return new SubXImm(machInst, rdsp, rnsp, imm); 10910037SARM gem5 Developers case 0x3: 11010337SAndrew.Bardsley@arm.com return new SubXImmCc(machInst, rdzr, rnsp, imm); 11112595Ssiddhesh.poyarekar@gmail.com default: 11212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 11310037SARM gem5 Developers } 11410037SARM gem5 Developers } 11510037SARM gem5 Developers case 0x4: 11610037SARM gem5 Developers { 11710037SARM gem5 Developers if (!sf && n) 11810037SARM gem5 Developers return new Unknown64(machInst); 11910037SARM gem5 Developers // len = MSB(n:NOT(imms)), len < 1 is undefined. 12010037SARM gem5 Developers uint8_t len = 0; 12110037SARM gem5 Developers if (n) { 12210037SARM gem5 Developers len = 6; 12310037SARM gem5 Developers } else if (imms == 0x3f || imms == 0x3e) { 12410037SARM gem5 Developers return new Unknown64(machInst); 12510037SARM gem5 Developers } else { 12610037SARM gem5 Developers len = findMsbSet(imms ^ 0x3f); 12710037SARM gem5 Developers } 12810037SARM gem5 Developers // Generate r, s, and size. 12910037SARM gem5 Developers uint64_t r = bits(immr, len - 1, 0); 13010037SARM gem5 Developers uint64_t s = bits(imms, len - 1, 0); 13110037SARM gem5 Developers uint8_t size = 1 << len; 13210037SARM gem5 Developers if (s == size - 1) 13310037SARM gem5 Developers return new Unknown64(machInst); 13410037SARM gem5 Developers // Generate the pattern with s 1s, rotated by r, with size bits. 13510037SARM gem5 Developers uint64_t pattern = mask(s + 1); 13610037SARM gem5 Developers if (r) { 13710037SARM gem5 Developers pattern = (pattern >> r) | (pattern << (size - r)); 13810037SARM gem5 Developers pattern &= mask(size); 13910037SARM gem5 Developers } 14010037SARM gem5 Developers uint8_t width = sf ? 64 : 32; 14110037SARM gem5 Developers // Replicate that to fill up the immediate. 14210037SARM gem5 Developers for (unsigned i = 1; i < (width / size); i *= 2) 14310037SARM gem5 Developers pattern |= (pattern << (i * size)); 14410037SARM gem5 Developers uint64_t imm = pattern; 14510037SARM gem5 Developers 14610037SARM gem5 Developers switch (opc) { 14710037SARM gem5 Developers case 0x0: 14810037SARM gem5 Developers return new AndXImm(machInst, rdsp, rn, imm); 14910037SARM gem5 Developers case 0x1: 15010037SARM gem5 Developers return new OrrXImm(machInst, rdsp, rn, imm); 15110037SARM gem5 Developers case 0x2: 15210037SARM gem5 Developers return new EorXImm(machInst, rdsp, rn, imm); 15310037SARM gem5 Developers case 0x3: 15410337SAndrew.Bardsley@arm.com return new AndXImmCc(machInst, rdzr, rn, imm); 15512595Ssiddhesh.poyarekar@gmail.com default: 15612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 15710037SARM gem5 Developers } 15810037SARM gem5 Developers } 15910037SARM gem5 Developers case 0x5: 16010037SARM gem5 Developers { 16110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 16210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 16310037SARM gem5 Developers uint32_t imm16 = bits(machInst, 20, 5); 16410037SARM gem5 Developers uint32_t hw = bits(machInst, 22, 21); 16510037SARM gem5 Developers switch (opc) { 16610037SARM gem5 Developers case 0x0: 16710337SAndrew.Bardsley@arm.com return new Movn(machInst, rdzr, imm16, hw * 16); 16810037SARM gem5 Developers case 0x1: 16910037SARM gem5 Developers return new Unknown64(machInst); 17010037SARM gem5 Developers case 0x2: 17110337SAndrew.Bardsley@arm.com return new Movz(machInst, rdzr, imm16, hw * 16); 17210037SARM gem5 Developers case 0x3: 17310337SAndrew.Bardsley@arm.com return new Movk(machInst, rdzr, imm16, hw * 16); 17412595Ssiddhesh.poyarekar@gmail.com default: 17512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 17610037SARM gem5 Developers } 17710037SARM gem5 Developers } 17810037SARM gem5 Developers case 0x6: 17910037SARM gem5 Developers if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 18010037SARM gem5 Developers return new Unknown64(machInst); 18110037SARM gem5 Developers switch (opc) { 18210037SARM gem5 Developers case 0x0: 18310337SAndrew.Bardsley@arm.com return new Sbfm64(machInst, rdzr, rn, immr, imms); 18410037SARM gem5 Developers case 0x1: 18510337SAndrew.Bardsley@arm.com return new Bfm64(machInst, rdzr, rn, immr, imms); 18610037SARM gem5 Developers case 0x2: 18710337SAndrew.Bardsley@arm.com return new Ubfm64(machInst, rdzr, rn, immr, imms); 18810037SARM gem5 Developers case 0x3: 18910037SARM gem5 Developers return new Unknown64(machInst); 19012595Ssiddhesh.poyarekar@gmail.com default: 19112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 19210037SARM gem5 Developers } 19310037SARM gem5 Developers case 0x7: 19410037SARM gem5 Developers { 19510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 19610037SARM gem5 Developers if (opc || bits(machInst, 21)) 19710037SARM gem5 Developers return new Unknown64(machInst); 19810037SARM gem5 Developers else 19910337SAndrew.Bardsley@arm.com return new Extr64(machInst, rdzr, rn, rm, imms); 20010037SARM gem5 Developers } 20110037SARM gem5 Developers } 20210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case8", machInst); 20310037SARM gem5 Developers } 20410037SARM gem5 Developers} 20510037SARM gem5 Developers}}; 20610037SARM gem5 Developers 20710037SARM gem5 Developersoutput decoder {{ 20810037SARM gem5 Developersnamespace Aarch64 20910037SARM gem5 Developers{ 21010037SARM gem5 Developers StaticInstPtr 21110037SARM gem5 Developers decodeBranchExcSys(ExtMachInst machInst) 21210037SARM gem5 Developers { 21310037SARM gem5 Developers switch (bits(machInst, 30, 29)) { 21410037SARM gem5 Developers case 0x0: 21510037SARM gem5 Developers { 21610037SARM gem5 Developers int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 21710037SARM gem5 Developers if (bits(machInst, 31) == 0) 21810037SARM gem5 Developers return new B64(machInst, imm); 21910037SARM gem5 Developers else 22010037SARM gem5 Developers return new Bl64(machInst, imm); 22110037SARM gem5 Developers } 22210037SARM gem5 Developers case 0x1: 22310037SARM gem5 Developers { 22410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 22510037SARM gem5 Developers if (bits(machInst, 25) == 0) { 22610037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 22710037SARM gem5 Developers if (bits(machInst, 24) == 0) 22810037SARM gem5 Developers return new Cbz64(machInst, imm, rt); 22910037SARM gem5 Developers else 23010037SARM gem5 Developers return new Cbnz64(machInst, imm, rt); 23110037SARM gem5 Developers } else { 23210037SARM gem5 Developers uint64_t bitmask = 0x1; 23310037SARM gem5 Developers bitmask <<= bits(machInst, 23, 19); 23410037SARM gem5 Developers int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 23510037SARM gem5 Developers if (bits(machInst, 31)) 23610037SARM gem5 Developers bitmask <<= 32; 23710037SARM gem5 Developers if (bits(machInst, 24) == 0) 23810037SARM gem5 Developers return new Tbz64(machInst, bitmask, imm, rt); 23910037SARM gem5 Developers else 24010037SARM gem5 Developers return new Tbnz64(machInst, bitmask, imm, rt); 24110037SARM gem5 Developers } 24210037SARM gem5 Developers } 24310037SARM gem5 Developers case 0x2: 24410037SARM gem5 Developers // bit 30:26=10101 24510037SARM gem5 Developers if (bits(machInst, 31) == 0) { 24610037SARM gem5 Developers if (bits(machInst, 25, 24) || bits(machInst, 4)) 24710037SARM gem5 Developers return new Unknown64(machInst); 24810037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 24910037SARM gem5 Developers ConditionCode condCode = 25010037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 25110037SARM gem5 Developers return new BCond64(machInst, imm, condCode); 25210037SARM gem5 Developers } else if (bits(machInst, 25, 24) == 0x0) { 25312538Sgiacomo.travaglini@arm.com 25410037SARM gem5 Developers if (bits(machInst, 4, 2)) 25510037SARM gem5 Developers return new Unknown64(machInst); 25612538Sgiacomo.travaglini@arm.com 25712538Sgiacomo.travaglini@arm.com auto imm16 = bits(machInst, 20, 5); 25810037SARM gem5 Developers uint8_t decVal = (bits(machInst, 1, 0) << 0) | 25910037SARM gem5 Developers (bits(machInst, 23, 21) << 2); 26012538Sgiacomo.travaglini@arm.com 26110037SARM gem5 Developers switch (decVal) { 26210037SARM gem5 Developers case 0x01: 26312538Sgiacomo.travaglini@arm.com return new Svc64(machInst, imm16); 26410037SARM gem5 Developers case 0x02: 26512538Sgiacomo.travaglini@arm.com return new Hvc64(machInst, imm16); 26610037SARM gem5 Developers case 0x03: 26712538Sgiacomo.travaglini@arm.com return new Smc64(machInst, imm16); 26810037SARM gem5 Developers case 0x04: 26912538Sgiacomo.travaglini@arm.com return new Brk64(machInst, imm16); 27010037SARM gem5 Developers case 0x08: 27112538Sgiacomo.travaglini@arm.com return new Hlt64(machInst, imm16); 27210037SARM gem5 Developers case 0x15: 27310037SARM gem5 Developers return new FailUnimplemented("dcps1", machInst); 27410037SARM gem5 Developers case 0x16: 27510037SARM gem5 Developers return new FailUnimplemented("dcps2", machInst); 27610037SARM gem5 Developers case 0x17: 27710037SARM gem5 Developers return new FailUnimplemented("dcps3", machInst); 27810037SARM gem5 Developers default: 27910037SARM gem5 Developers return new Unknown64(machInst); 28010037SARM gem5 Developers } 28110037SARM gem5 Developers } else if (bits(machInst, 25, 22) == 0x4) { 28210037SARM gem5 Developers // bit 31:22=1101010100 28310037SARM gem5 Developers bool l = bits(machInst, 21); 28410037SARM gem5 Developers uint8_t op0 = bits(machInst, 20, 19); 28510037SARM gem5 Developers uint8_t op1 = bits(machInst, 18, 16); 28610037SARM gem5 Developers uint8_t crn = bits(machInst, 15, 12); 28710037SARM gem5 Developers uint8_t crm = bits(machInst, 11, 8); 28810037SARM gem5 Developers uint8_t op2 = bits(machInst, 7, 5); 28910037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 29010037SARM gem5 Developers switch (op0) { 29110037SARM gem5 Developers case 0x0: 29210037SARM gem5 Developers if (rt != 0x1f || l) 29310037SARM gem5 Developers return new Unknown64(machInst); 29410037SARM gem5 Developers if (crn == 0x2 && op1 == 0x3) { 29510037SARM gem5 Developers switch (op2) { 29610037SARM gem5 Developers case 0x0: 29710037SARM gem5 Developers return new NopInst(machInst); 29810037SARM gem5 Developers case 0x1: 29910037SARM gem5 Developers return new YieldInst(machInst); 30010037SARM gem5 Developers case 0x2: 30110037SARM gem5 Developers return new WfeInst(machInst); 30210037SARM gem5 Developers case 0x3: 30310037SARM gem5 Developers return new WfiInst(machInst); 30410037SARM gem5 Developers case 0x4: 30510037SARM gem5 Developers return new SevInst(machInst); 30610037SARM gem5 Developers case 0x5: 30710037SARM gem5 Developers return new SevlInst(machInst); 30810037SARM gem5 Developers default: 30910037SARM gem5 Developers return new Unknown64(machInst); 31010037SARM gem5 Developers } 31110037SARM gem5 Developers } else if (crn == 0x3 && op1 == 0x3) { 31210037SARM gem5 Developers switch (op2) { 31310037SARM gem5 Developers case 0x2: 31410037SARM gem5 Developers return new Clrex64(machInst); 31510037SARM gem5 Developers case 0x4: 31610037SARM gem5 Developers return new Dsb64(machInst); 31710037SARM gem5 Developers case 0x5: 31810037SARM gem5 Developers return new Dmb64(machInst); 31910037SARM gem5 Developers case 0x6: 32010037SARM gem5 Developers return new Isb64(machInst); 32110037SARM gem5 Developers default: 32210037SARM gem5 Developers return new Unknown64(machInst); 32310037SARM gem5 Developers } 32410037SARM gem5 Developers } else if (crn == 0x4) { 32510037SARM gem5 Developers // MSR immediate 32610037SARM gem5 Developers switch (op1 << 3 | op2) { 32710037SARM gem5 Developers case 0x5: 32810037SARM gem5 Developers // SP 32910037SARM gem5 Developers return new MsrSP64(machInst, 33010037SARM gem5 Developers (IntRegIndex) MISCREG_SPSEL, 33110037SARM gem5 Developers INTREG_ZERO, 33210037SARM gem5 Developers crm & 0x1); 33310037SARM gem5 Developers case 0x1e: 33410037SARM gem5 Developers // DAIFSet 33510037SARM gem5 Developers return new MsrDAIFSet64( 33610037SARM gem5 Developers machInst, 33710037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 33810037SARM gem5 Developers INTREG_ZERO, 33910037SARM gem5 Developers crm); 34010037SARM gem5 Developers case 0x1f: 34110037SARM gem5 Developers // DAIFClr 34210037SARM gem5 Developers return new MsrDAIFClr64( 34310037SARM gem5 Developers machInst, 34410037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 34510037SARM gem5 Developers INTREG_ZERO, 34610037SARM gem5 Developers crm); 34710037SARM gem5 Developers default: 34810037SARM gem5 Developers return new Unknown64(machInst); 34910037SARM gem5 Developers } 35010037SARM gem5 Developers } else { 35110037SARM gem5 Developers return new Unknown64(machInst); 35210037SARM gem5 Developers } 35310037SARM gem5 Developers break; 35410037SARM gem5 Developers case 0x1: 35510037SARM gem5 Developers case 0x2: 35610037SARM gem5 Developers case 0x3: 35710037SARM gem5 Developers { 35810037SARM gem5 Developers // bit 31:22=1101010100, 20:19=11 35910037SARM gem5 Developers bool read = l; 36010037SARM gem5 Developers MiscRegIndex miscReg = 36110037SARM gem5 Developers decodeAArch64SysReg(op0, op1, crn, crm, op2); 36210037SARM gem5 Developers if (read) { 36310037SARM gem5 Developers if ((miscReg == MISCREG_DC_CIVAC_Xt) || 36410037SARM gem5 Developers (miscReg == MISCREG_DC_CVAC_Xt) || 36512359Snikos.nikoleris@arm.com (miscReg == MISCREG_DC_IVAC_Xt) || 36610037SARM gem5 Developers (miscReg == MISCREG_DC_ZVA_Xt)) { 36710037SARM gem5 Developers return new Unknown64(machInst); 36810037SARM gem5 Developers } 36910037SARM gem5 Developers } 37010037SARM gem5 Developers // Check for invalid registers 37110037SARM gem5 Developers if (miscReg == MISCREG_UNKNOWN) { 37212673Sgiacomo.travaglini@arm.com auto full_mnemonic = 37312673Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 37412673Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 37512673Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 37612673Sgiacomo.travaglini@arm.com 37712673Sgiacomo.travaglini@arm.com return new FailUnimplemented(read ? "mrs" : "msr", 37812673Sgiacomo.travaglini@arm.com machInst, full_mnemonic); 37912673Sgiacomo.travaglini@arm.com 38012714Sgiacomo.travaglini@arm.com } else if (miscReg == MISCREG_IMPDEF_UNIMPL) { 38112714Sgiacomo.travaglini@arm.com auto full_mnemonic = 38212714Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 38312714Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 38412714Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 38512714Sgiacomo.travaglini@arm.com 38612714Sgiacomo.travaglini@arm.com if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 38712714Sgiacomo.travaglini@arm.com return new WarnUnimplemented(read ? "mrs" : "msr", 38812714Sgiacomo.travaglini@arm.com machInst, full_mnemonic + " treated as NOP"); 38912714Sgiacomo.travaglini@arm.com } else { 39012714Sgiacomo.travaglini@arm.com return new FailUnimplemented(read ? "mrs" : "msr", 39112714Sgiacomo.travaglini@arm.com machInst, full_mnemonic); 39212714Sgiacomo.travaglini@arm.com } 39312714Sgiacomo.travaglini@arm.com 39410037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 39510037SARM gem5 Developers if (miscReg == MISCREG_NZCV) { 39610037SARM gem5 Developers if (read) 39710037SARM gem5 Developers return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 39810037SARM gem5 Developers else 39910037SARM gem5 Developers return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 40010037SARM gem5 Developers } 40110037SARM gem5 Developers uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 40210506SAli.Saidi@ARM.com if (read) { 40312280Sgiacomo.travaglini@arm.com StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); 40410506SAli.Saidi@ARM.com if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 40510506SAli.Saidi@ARM.com si->setFlag(StaticInst::IsUnverifiable); 40610506SAli.Saidi@ARM.com return si; 40712280Sgiacomo.travaglini@arm.com } else { 40812359Snikos.nikoleris@arm.com switch (miscReg) { 40912359Snikos.nikoleris@arm.com case MISCREG_DC_ZVA_Xt: 41012359Snikos.nikoleris@arm.com return new Dczva(machInst, rt, miscReg, iss); 41112359Snikos.nikoleris@arm.com case MISCREG_DC_CVAU_Xt: 41212359Snikos.nikoleris@arm.com return new Dccvau(machInst, rt, miscReg, iss); 41312359Snikos.nikoleris@arm.com case MISCREG_DC_CVAC_Xt: 41412359Snikos.nikoleris@arm.com return new Dccvac(machInst, rt, miscReg, iss); 41512359Snikos.nikoleris@arm.com case MISCREG_DC_CIVAC_Xt: 41612359Snikos.nikoleris@arm.com return new Dccivac(machInst, rt, miscReg, iss); 41712359Snikos.nikoleris@arm.com case MISCREG_DC_IVAC_Xt: 41812359Snikos.nikoleris@arm.com return new Dcivac(machInst, rt, miscReg, iss); 41912359Snikos.nikoleris@arm.com default: 42012359Snikos.nikoleris@arm.com return new Msr64(machInst, miscReg, rt, iss); 42112359Snikos.nikoleris@arm.com } 42212280Sgiacomo.travaglini@arm.com } 42310037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 42410037SARM gem5 Developers std::string full_mnem = csprintf("%s %s", 42510037SARM gem5 Developers read ? "mrs" : "msr", miscRegName[miscReg]); 42610037SARM gem5 Developers return new WarnUnimplemented(read ? "mrs" : "msr", 42710037SARM gem5 Developers machInst, full_mnem); 42810037SARM gem5 Developers } else { 42910173SMitchell.Hayenga@ARM.com return new FailUnimplemented(read ? "mrs" : "msr", 43010173SMitchell.Hayenga@ARM.com machInst, 43110173SMitchell.Hayenga@ARM.com csprintf("%s %s", 43210173SMitchell.Hayenga@ARM.com read ? "mrs" : "msr", 43310173SMitchell.Hayenga@ARM.com miscRegName[miscReg])); 43410037SARM gem5 Developers } 43510037SARM gem5 Developers } 43610037SARM gem5 Developers break; 43712595Ssiddhesh.poyarekar@gmail.com default: 43812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 43910037SARM gem5 Developers } 44010037SARM gem5 Developers } else if (bits(machInst, 25) == 0x1) { 44110037SARM gem5 Developers uint8_t opc = bits(machInst, 24, 21); 44210037SARM gem5 Developers uint8_t op2 = bits(machInst, 20, 16); 44310037SARM gem5 Developers uint8_t op3 = bits(machInst, 15, 10); 44410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 44510037SARM gem5 Developers uint8_t op4 = bits(machInst, 4, 0); 44610037SARM gem5 Developers if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 44710037SARM gem5 Developers return new Unknown64(machInst); 44810037SARM gem5 Developers switch (opc) { 44910037SARM gem5 Developers case 0x0: 45010037SARM gem5 Developers return new Br64(machInst, rn); 45110037SARM gem5 Developers case 0x1: 45210037SARM gem5 Developers return new Blr64(machInst, rn); 45310037SARM gem5 Developers case 0x2: 45410037SARM gem5 Developers return new Ret64(machInst, rn); 45510037SARM gem5 Developers case 0x4: 45610037SARM gem5 Developers if (rn != 0x1f) 45710037SARM gem5 Developers return new Unknown64(machInst); 45810037SARM gem5 Developers return new Eret64(machInst); 45910037SARM gem5 Developers case 0x5: 46010037SARM gem5 Developers if (rn != 0x1f) 46110037SARM gem5 Developers return new Unknown64(machInst); 46210037SARM gem5 Developers return new FailUnimplemented("dret", machInst); 46312595Ssiddhesh.poyarekar@gmail.com default: 46412595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 46510037SARM gem5 Developers } 46610037SARM gem5 Developers } 46712595Ssiddhesh.poyarekar@gmail.com M5_FALLTHROUGH; 46810037SARM gem5 Developers default: 46910037SARM gem5 Developers return new Unknown64(machInst); 47010037SARM gem5 Developers } 47110037SARM gem5 Developers return new FailUnimplemented("Unhandled Case7", machInst); 47210037SARM gem5 Developers } 47310037SARM gem5 Developers} 47410037SARM gem5 Developers}}; 47510037SARM gem5 Developers 47610037SARM gem5 Developersoutput decoder {{ 47710037SARM gem5 Developersnamespace Aarch64 47810037SARM gem5 Developers{ 47910037SARM gem5 Developers StaticInstPtr 48010037SARM gem5 Developers decodeLoadsStores(ExtMachInst machInst) 48110037SARM gem5 Developers { 48210037SARM gem5 Developers // bit 27,25=10 48310037SARM gem5 Developers switch (bits(machInst, 29, 28)) { 48410037SARM gem5 Developers case 0x0: 48510037SARM gem5 Developers if (bits(machInst, 26) == 0) { 48610037SARM gem5 Developers if (bits(machInst, 24) != 0) 48710037SARM gem5 Developers return new Unknown64(machInst); 48810037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 48910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 49010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 49110037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 49210037SARM gem5 Developers IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 49310037SARM gem5 Developers uint8_t opc = (bits(machInst, 15) << 0) | 49410037SARM gem5 Developers (bits(machInst, 23, 21) << 1); 49510037SARM gem5 Developers uint8_t size = bits(machInst, 31, 30); 49610037SARM gem5 Developers switch (opc) { 49710037SARM gem5 Developers case 0x0: 49810037SARM gem5 Developers switch (size) { 49910037SARM gem5 Developers case 0x0: 50010037SARM gem5 Developers return new STXRB64(machInst, rt, rnsp, rs); 50110037SARM gem5 Developers case 0x1: 50210037SARM gem5 Developers return new STXRH64(machInst, rt, rnsp, rs); 50310037SARM gem5 Developers case 0x2: 50410037SARM gem5 Developers return new STXRW64(machInst, rt, rnsp, rs); 50510037SARM gem5 Developers case 0x3: 50610037SARM gem5 Developers return new STXRX64(machInst, rt, rnsp, rs); 50712595Ssiddhesh.poyarekar@gmail.com default: 50812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 50910037SARM gem5 Developers } 51010037SARM gem5 Developers case 0x1: 51110037SARM gem5 Developers switch (size) { 51210037SARM gem5 Developers case 0x0: 51310037SARM gem5 Developers return new STLXRB64(machInst, rt, rnsp, rs); 51410037SARM gem5 Developers case 0x1: 51510037SARM gem5 Developers return new STLXRH64(machInst, rt, rnsp, rs); 51610037SARM gem5 Developers case 0x2: 51710037SARM gem5 Developers return new STLXRW64(machInst, rt, rnsp, rs); 51810037SARM gem5 Developers case 0x3: 51910037SARM gem5 Developers return new STLXRX64(machInst, rt, rnsp, rs); 52012595Ssiddhesh.poyarekar@gmail.com default: 52112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 52210037SARM gem5 Developers } 52310037SARM gem5 Developers case 0x2: 52410037SARM gem5 Developers switch (size) { 52510037SARM gem5 Developers case 0x0: 52610037SARM gem5 Developers case 0x1: 52710037SARM gem5 Developers return new Unknown64(machInst); 52810037SARM gem5 Developers case 0x2: 52910037SARM gem5 Developers return new STXPW64(machInst, rs, rt, rt2, rnsp); 53010037SARM gem5 Developers case 0x3: 53110037SARM gem5 Developers return new STXPX64(machInst, rs, rt, rt2, rnsp); 53212595Ssiddhesh.poyarekar@gmail.com default: 53312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 53410037SARM gem5 Developers } 53510037SARM gem5 Developers 53610037SARM gem5 Developers case 0x3: 53710037SARM gem5 Developers switch (size) { 53810037SARM gem5 Developers case 0x0: 53910037SARM gem5 Developers case 0x1: 54010037SARM gem5 Developers return new Unknown64(machInst); 54110037SARM gem5 Developers case 0x2: 54210037SARM gem5 Developers return new STLXPW64(machInst, rs, rt, rt2, rnsp); 54310037SARM gem5 Developers case 0x3: 54410037SARM gem5 Developers return new STLXPX64(machInst, rs, rt, rt2, rnsp); 54512595Ssiddhesh.poyarekar@gmail.com default: 54612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 54710037SARM gem5 Developers } 54810037SARM gem5 Developers 54910037SARM gem5 Developers case 0x4: 55010037SARM gem5 Developers switch (size) { 55110037SARM gem5 Developers case 0x0: 55210037SARM gem5 Developers return new LDXRB64(machInst, rt, rnsp, rs); 55310037SARM gem5 Developers case 0x1: 55410037SARM gem5 Developers return new LDXRH64(machInst, rt, rnsp, rs); 55510037SARM gem5 Developers case 0x2: 55610037SARM gem5 Developers return new LDXRW64(machInst, rt, rnsp, rs); 55710037SARM gem5 Developers case 0x3: 55810037SARM gem5 Developers return new LDXRX64(machInst, rt, rnsp, rs); 55912595Ssiddhesh.poyarekar@gmail.com default: 56012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 56110037SARM gem5 Developers } 56210037SARM gem5 Developers case 0x5: 56310037SARM gem5 Developers switch (size) { 56410037SARM gem5 Developers case 0x0: 56510037SARM gem5 Developers return new LDAXRB64(machInst, rt, rnsp, rs); 56610037SARM gem5 Developers case 0x1: 56710037SARM gem5 Developers return new LDAXRH64(machInst, rt, rnsp, rs); 56810037SARM gem5 Developers case 0x2: 56910037SARM gem5 Developers return new LDAXRW64(machInst, rt, rnsp, rs); 57010037SARM gem5 Developers case 0x3: 57110037SARM gem5 Developers return new LDAXRX64(machInst, rt, rnsp, rs); 57212595Ssiddhesh.poyarekar@gmail.com default: 57312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 57410037SARM gem5 Developers } 57510037SARM gem5 Developers case 0x6: 57610037SARM gem5 Developers switch (size) { 57710037SARM gem5 Developers case 0x0: 57810037SARM gem5 Developers case 0x1: 57910037SARM gem5 Developers return new Unknown64(machInst); 58010037SARM gem5 Developers case 0x2: 58110037SARM gem5 Developers return new LDXPW64(machInst, rt, rt2, rnsp); 58210037SARM gem5 Developers case 0x3: 58310037SARM gem5 Developers return new LDXPX64(machInst, rt, rt2, rnsp); 58412595Ssiddhesh.poyarekar@gmail.com default: 58512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 58610037SARM gem5 Developers } 58710037SARM gem5 Developers 58810037SARM gem5 Developers case 0x7: 58910037SARM gem5 Developers switch (size) { 59010037SARM gem5 Developers case 0x0: 59110037SARM gem5 Developers case 0x1: 59210037SARM gem5 Developers return new Unknown64(machInst); 59310037SARM gem5 Developers case 0x2: 59410037SARM gem5 Developers return new LDAXPW64(machInst, rt, rt2, rnsp); 59510037SARM gem5 Developers case 0x3: 59610037SARM gem5 Developers return new LDAXPX64(machInst, rt, rt2, rnsp); 59712595Ssiddhesh.poyarekar@gmail.com default: 59812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 59910037SARM gem5 Developers } 60010037SARM gem5 Developers 60110037SARM gem5 Developers case 0x9: 60210037SARM gem5 Developers switch (size) { 60310037SARM gem5 Developers case 0x0: 60410037SARM gem5 Developers return new STLRB64(machInst, rt, rnsp); 60510037SARM gem5 Developers case 0x1: 60610037SARM gem5 Developers return new STLRH64(machInst, rt, rnsp); 60710037SARM gem5 Developers case 0x2: 60810037SARM gem5 Developers return new STLRW64(machInst, rt, rnsp); 60910037SARM gem5 Developers case 0x3: 61010037SARM gem5 Developers return new STLRX64(machInst, rt, rnsp); 61112595Ssiddhesh.poyarekar@gmail.com default: 61212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 61310037SARM gem5 Developers } 61410037SARM gem5 Developers case 0xd: 61510037SARM gem5 Developers switch (size) { 61610037SARM gem5 Developers case 0x0: 61710037SARM gem5 Developers return new LDARB64(machInst, rt, rnsp); 61810037SARM gem5 Developers case 0x1: 61910037SARM gem5 Developers return new LDARH64(machInst, rt, rnsp); 62010037SARM gem5 Developers case 0x2: 62110037SARM gem5 Developers return new LDARW64(machInst, rt, rnsp); 62210037SARM gem5 Developers case 0x3: 62310037SARM gem5 Developers return new LDARX64(machInst, rt, rnsp); 62412595Ssiddhesh.poyarekar@gmail.com default: 62512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 62610037SARM gem5 Developers } 62710037SARM gem5 Developers default: 62810037SARM gem5 Developers return new Unknown64(machInst); 62910037SARM gem5 Developers } 63010037SARM gem5 Developers } else if (bits(machInst, 31)) { 63110037SARM gem5 Developers return new Unknown64(machInst); 63210037SARM gem5 Developers } else { 63310037SARM gem5 Developers return decodeNeonMem(machInst); 63410037SARM gem5 Developers } 63510037SARM gem5 Developers case 0x1: 63610037SARM gem5 Developers { 63710037SARM gem5 Developers if (bits(machInst, 24) != 0) 63810037SARM gem5 Developers return new Unknown64(machInst); 63910037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 26) << 0) | 64010037SARM gem5 Developers (bits(machInst, 31, 30) << 1); 64110037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 64210037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 64310037SARM gem5 Developers switch (switchVal) { 64410037SARM gem5 Developers case 0x0: 64510037SARM gem5 Developers return new LDRWL64_LIT(machInst, rt, imm); 64610037SARM gem5 Developers case 0x1: 64710037SARM gem5 Developers return new LDRSFP64_LIT(machInst, rt, imm); 64810037SARM gem5 Developers case 0x2: 64910037SARM gem5 Developers return new LDRXL64_LIT(machInst, rt, imm); 65010037SARM gem5 Developers case 0x3: 65110037SARM gem5 Developers return new LDRDFP64_LIT(machInst, rt, imm); 65210037SARM gem5 Developers case 0x4: 65310037SARM gem5 Developers return new LDRSWL64_LIT(machInst, rt, imm); 65410037SARM gem5 Developers case 0x5: 65510037SARM gem5 Developers return new BigFpMemLit("ldr", machInst, rt, imm); 65610037SARM gem5 Developers case 0x6: 65710037SARM gem5 Developers return new PRFM64_LIT(machInst, rt, imm); 65810037SARM gem5 Developers default: 65910037SARM gem5 Developers return new Unknown64(machInst); 66010037SARM gem5 Developers } 66110037SARM gem5 Developers } 66210037SARM gem5 Developers case 0x2: 66310037SARM gem5 Developers { 66410037SARM gem5 Developers uint8_t opc = bits(machInst, 31, 30); 66510037SARM gem5 Developers if (opc >= 3) 66610037SARM gem5 Developers return new Unknown64(machInst); 66710037SARM gem5 Developers uint32_t size = 0; 66810037SARM gem5 Developers bool fp = bits(machInst, 26); 66910037SARM gem5 Developers bool load = bits(machInst, 22); 67010037SARM gem5 Developers if (fp) { 67110037SARM gem5 Developers size = 4 << opc; 67210037SARM gem5 Developers } else { 67310037SARM gem5 Developers if ((opc == 1) && !load) 67410037SARM gem5 Developers return new Unknown64(machInst); 67510037SARM gem5 Developers size = (opc == 0 || opc == 1) ? 4 : 8; 67610037SARM gem5 Developers } 67710037SARM gem5 Developers uint8_t type = bits(machInst, 24, 23); 67810037SARM gem5 Developers int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 67910037SARM gem5 Developers 68010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 68110037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 68210037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 68310037SARM gem5 Developers 68410037SARM gem5 Developers bool noAlloc = (type == 0); 68510037SARM gem5 Developers bool signExt = !noAlloc && !fp && opc == 1; 68610037SARM gem5 Developers PairMemOp::AddrMode mode; 68710037SARM gem5 Developers const char *mnemonic = NULL; 68810037SARM gem5 Developers switch (type) { 68910037SARM gem5 Developers case 0x0: 69010037SARM gem5 Developers case 0x2: 69110037SARM gem5 Developers mode = PairMemOp::AddrMd_Offset; 69210037SARM gem5 Developers break; 69310037SARM gem5 Developers case 0x1: 69410037SARM gem5 Developers mode = PairMemOp::AddrMd_PostIndex; 69510037SARM gem5 Developers break; 69610037SARM gem5 Developers case 0x3: 69710037SARM gem5 Developers mode = PairMemOp::AddrMd_PreIndex; 69810037SARM gem5 Developers break; 69910037SARM gem5 Developers default: 70010037SARM gem5 Developers return new Unknown64(machInst); 70110037SARM gem5 Developers } 70210037SARM gem5 Developers if (load) { 70310037SARM gem5 Developers if (noAlloc) 70410037SARM gem5 Developers mnemonic = "ldnp"; 70510037SARM gem5 Developers else if (signExt) 70610037SARM gem5 Developers mnemonic = "ldpsw"; 70710037SARM gem5 Developers else 70810037SARM gem5 Developers mnemonic = "ldp"; 70910037SARM gem5 Developers } else { 71010037SARM gem5 Developers if (noAlloc) 71110037SARM gem5 Developers mnemonic = "stnp"; 71210037SARM gem5 Developers else 71310037SARM gem5 Developers mnemonic = "stp"; 71410037SARM gem5 Developers } 71510037SARM gem5 Developers 71610037SARM gem5 Developers return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 71710037SARM gem5 Developers signExt, false, false, imm, mode, rn, rt, rt2); 71810037SARM gem5 Developers } 71910037SARM gem5 Developers // bit 29:27=111, 25=0 72010037SARM gem5 Developers case 0x3: 72110037SARM gem5 Developers { 72210037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 72310037SARM gem5 Developers (bits(machInst, 26) << 2) | 72410037SARM gem5 Developers (bits(machInst, 31, 30) << 3); 72510037SARM gem5 Developers if (bits(machInst, 24) == 1) { 72610037SARM gem5 Developers uint64_t imm12 = bits(machInst, 21, 10); 72710037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 72810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 72910037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 73010037SARM gem5 Developers switch (switchVal) { 73110037SARM gem5 Developers case 0x00: 73210037SARM gem5 Developers return new STRB64_IMM(machInst, rt, rnsp, imm12); 73310037SARM gem5 Developers case 0x01: 73410037SARM gem5 Developers return new LDRB64_IMM(machInst, rt, rnsp, imm12); 73510037SARM gem5 Developers case 0x02: 73610037SARM gem5 Developers return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 73710037SARM gem5 Developers case 0x03: 73810037SARM gem5 Developers return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 73910037SARM gem5 Developers case 0x04: 74010037SARM gem5 Developers return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 74110037SARM gem5 Developers case 0x05: 74210037SARM gem5 Developers return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 74310037SARM gem5 Developers case 0x06: 74410037SARM gem5 Developers return new BigFpMemImm("str", machInst, false, 74510037SARM gem5 Developers rt, rnsp, imm12 << 4); 74610037SARM gem5 Developers case 0x07: 74710037SARM gem5 Developers return new BigFpMemImm("ldr", machInst, true, 74810037SARM gem5 Developers rt, rnsp, imm12 << 4); 74910037SARM gem5 Developers case 0x08: 75010037SARM gem5 Developers return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 75110037SARM gem5 Developers case 0x09: 75210037SARM gem5 Developers return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 75310037SARM gem5 Developers case 0x0a: 75410037SARM gem5 Developers return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 75510037SARM gem5 Developers case 0x0b: 75610037SARM gem5 Developers return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 75710037SARM gem5 Developers case 0x0c: 75810037SARM gem5 Developers return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 75910037SARM gem5 Developers case 0x0d: 76010037SARM gem5 Developers return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 76110037SARM gem5 Developers case 0x10: 76210037SARM gem5 Developers return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 76310037SARM gem5 Developers case 0x11: 76410037SARM gem5 Developers return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 76510037SARM gem5 Developers case 0x12: 76610037SARM gem5 Developers return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 76710037SARM gem5 Developers case 0x14: 76810037SARM gem5 Developers return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 76910037SARM gem5 Developers case 0x15: 77010037SARM gem5 Developers return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 77110037SARM gem5 Developers case 0x18: 77210037SARM gem5 Developers return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 77310037SARM gem5 Developers case 0x19: 77410037SARM gem5 Developers return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 77510037SARM gem5 Developers case 0x1a: 77610037SARM gem5 Developers return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 77710037SARM gem5 Developers case 0x1c: 77810037SARM gem5 Developers return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 77910037SARM gem5 Developers case 0x1d: 78010037SARM gem5 Developers return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 78110037SARM gem5 Developers default: 78210037SARM gem5 Developers return new Unknown64(machInst); 78310037SARM gem5 Developers } 78410037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 78512856Sgiacomo.gabrielli@arm.com uint8_t group = bits(machInst, 11, 10); 78612856Sgiacomo.gabrielli@arm.com switch (group) { 78712856Sgiacomo.gabrielli@arm.com case 0x0: 78812856Sgiacomo.gabrielli@arm.com { 78912856Sgiacomo.gabrielli@arm.com if ((switchVal & 0x7) == 0x2 && 79012856Sgiacomo.gabrielli@arm.com bits(machInst, 20, 12) == 0x1fc) { 79112856Sgiacomo.gabrielli@arm.com IntRegIndex rt = (IntRegIndex)(uint32_t) 79212856Sgiacomo.gabrielli@arm.com bits(machInst, 4, 0); 79312856Sgiacomo.gabrielli@arm.com IntRegIndex rn = (IntRegIndex)(uint32_t) 79412856Sgiacomo.gabrielli@arm.com bits(machInst, 9, 5); 79512856Sgiacomo.gabrielli@arm.com IntRegIndex rnsp = makeSP(rn); 79612856Sgiacomo.gabrielli@arm.com uint8_t size = bits(machInst, 31, 30); 79712856Sgiacomo.gabrielli@arm.com switch (size) { 79812856Sgiacomo.gabrielli@arm.com case 0x0: 79912856Sgiacomo.gabrielli@arm.com return new LDAPRB64(machInst, rt, rnsp); 80012856Sgiacomo.gabrielli@arm.com case 0x1: 80112856Sgiacomo.gabrielli@arm.com return new LDAPRH64(machInst, rt, rnsp); 80212856Sgiacomo.gabrielli@arm.com case 0x2: 80312856Sgiacomo.gabrielli@arm.com return new LDAPRW64(machInst, rt, rnsp); 80412856Sgiacomo.gabrielli@arm.com case 0x3: 80512856Sgiacomo.gabrielli@arm.com return new LDAPRX64(machInst, rt, rnsp); 80612856Sgiacomo.gabrielli@arm.com default: 80712856Sgiacomo.gabrielli@arm.com M5_UNREACHABLE; 80812856Sgiacomo.gabrielli@arm.com } 80912856Sgiacomo.gabrielli@arm.com } else { 81012856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 81112856Sgiacomo.gabrielli@arm.com } 81212856Sgiacomo.gabrielli@arm.com } 81312856Sgiacomo.gabrielli@arm.com case 0x2: 81412856Sgiacomo.gabrielli@arm.com { 81512856Sgiacomo.gabrielli@arm.com if (!bits(machInst, 14)) 81612856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 81712856Sgiacomo.gabrielli@arm.com IntRegIndex rt = (IntRegIndex)(uint32_t) 81812856Sgiacomo.gabrielli@arm.com bits(machInst, 4, 0); 81912856Sgiacomo.gabrielli@arm.com IntRegIndex rn = (IntRegIndex)(uint32_t) 82012856Sgiacomo.gabrielli@arm.com bits(machInst, 9, 5); 82112856Sgiacomo.gabrielli@arm.com IntRegIndex rnsp = makeSP(rn); 82212856Sgiacomo.gabrielli@arm.com IntRegIndex rm = (IntRegIndex)(uint32_t) 82312856Sgiacomo.gabrielli@arm.com bits(machInst, 20, 16); 82412856Sgiacomo.gabrielli@arm.com ArmExtendType type = 82512856Sgiacomo.gabrielli@arm.com (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 82612856Sgiacomo.gabrielli@arm.com uint8_t s = bits(machInst, 12); 82712856Sgiacomo.gabrielli@arm.com switch (switchVal) { 82812856Sgiacomo.gabrielli@arm.com case 0x00: 82912856Sgiacomo.gabrielli@arm.com return new STRB64_REG(machInst, rt, rnsp, rm, 83012856Sgiacomo.gabrielli@arm.com type, 0); 83112856Sgiacomo.gabrielli@arm.com case 0x01: 83212856Sgiacomo.gabrielli@arm.com return new LDRB64_REG(machInst, rt, rnsp, rm, 83312856Sgiacomo.gabrielli@arm.com type, 0); 83412856Sgiacomo.gabrielli@arm.com case 0x02: 83512856Sgiacomo.gabrielli@arm.com return new LDRSBX64_REG(machInst, rt, rnsp, rm, 83612856Sgiacomo.gabrielli@arm.com type, 0); 83712856Sgiacomo.gabrielli@arm.com case 0x03: 83812856Sgiacomo.gabrielli@arm.com return new LDRSBW64_REG(machInst, rt, rnsp, rm, 83912856Sgiacomo.gabrielli@arm.com type, 0); 84012856Sgiacomo.gabrielli@arm.com case 0x04: 84112856Sgiacomo.gabrielli@arm.com return new STRBFP64_REG(machInst, rt, rnsp, rm, 84212856Sgiacomo.gabrielli@arm.com type, 0); 84312856Sgiacomo.gabrielli@arm.com case 0x05: 84412856Sgiacomo.gabrielli@arm.com return new LDRBFP64_REG(machInst, rt, rnsp, rm, 84512856Sgiacomo.gabrielli@arm.com type, 0); 84612856Sgiacomo.gabrielli@arm.com case 0x6: 84712856Sgiacomo.gabrielli@arm.com return new BigFpMemReg("str", machInst, false, 84812856Sgiacomo.gabrielli@arm.com rt, rnsp, rm, type, s * 4); 84912856Sgiacomo.gabrielli@arm.com case 0x7: 85012856Sgiacomo.gabrielli@arm.com return new BigFpMemReg("ldr", machInst, true, 85112856Sgiacomo.gabrielli@arm.com rt, rnsp, rm, type, s * 4); 85212856Sgiacomo.gabrielli@arm.com case 0x08: 85312856Sgiacomo.gabrielli@arm.com return new STRH64_REG(machInst, rt, rnsp, rm, 85412856Sgiacomo.gabrielli@arm.com type, s); 85512856Sgiacomo.gabrielli@arm.com case 0x09: 85612856Sgiacomo.gabrielli@arm.com return new LDRH64_REG(machInst, rt, rnsp, rm, 85712856Sgiacomo.gabrielli@arm.com type, s); 85812856Sgiacomo.gabrielli@arm.com case 0x0a: 85912856Sgiacomo.gabrielli@arm.com return new LDRSHX64_REG(machInst, rt, rnsp, rm, 86012856Sgiacomo.gabrielli@arm.com type, s); 86112856Sgiacomo.gabrielli@arm.com case 0x0b: 86212856Sgiacomo.gabrielli@arm.com return new LDRSHW64_REG(machInst, rt, rnsp, rm, 86312856Sgiacomo.gabrielli@arm.com type, s); 86412856Sgiacomo.gabrielli@arm.com case 0x0c: 86512856Sgiacomo.gabrielli@arm.com return new STRHFP64_REG(machInst, rt, rnsp, rm, 86612856Sgiacomo.gabrielli@arm.com type, s); 86712856Sgiacomo.gabrielli@arm.com case 0x0d: 86812856Sgiacomo.gabrielli@arm.com return new LDRHFP64_REG(machInst, rt, rnsp, rm, 86912856Sgiacomo.gabrielli@arm.com type, s); 87012856Sgiacomo.gabrielli@arm.com case 0x10: 87112856Sgiacomo.gabrielli@arm.com return new STRW64_REG(machInst, rt, rnsp, rm, 87212856Sgiacomo.gabrielli@arm.com type, s * 2); 87312856Sgiacomo.gabrielli@arm.com case 0x11: 87412856Sgiacomo.gabrielli@arm.com return new LDRW64_REG(machInst, rt, rnsp, rm, 87512856Sgiacomo.gabrielli@arm.com type, s * 2); 87612856Sgiacomo.gabrielli@arm.com case 0x12: 87712856Sgiacomo.gabrielli@arm.com return new LDRSW64_REG(machInst, rt, rnsp, rm, 87812856Sgiacomo.gabrielli@arm.com type, s * 2); 87912856Sgiacomo.gabrielli@arm.com case 0x14: 88012856Sgiacomo.gabrielli@arm.com return new STRSFP64_REG(machInst, rt, rnsp, rm, 88112856Sgiacomo.gabrielli@arm.com type, s * 2); 88212856Sgiacomo.gabrielli@arm.com case 0x15: 88312856Sgiacomo.gabrielli@arm.com return new LDRSFP64_REG(machInst, rt, rnsp, rm, 88412856Sgiacomo.gabrielli@arm.com type, s * 2); 88512856Sgiacomo.gabrielli@arm.com case 0x18: 88612856Sgiacomo.gabrielli@arm.com return new STRX64_REG(machInst, rt, rnsp, rm, 88712856Sgiacomo.gabrielli@arm.com type, s * 3); 88812856Sgiacomo.gabrielli@arm.com case 0x19: 88912856Sgiacomo.gabrielli@arm.com return new LDRX64_REG(machInst, rt, rnsp, rm, 89012856Sgiacomo.gabrielli@arm.com type, s * 3); 89112856Sgiacomo.gabrielli@arm.com case 0x1a: 89212856Sgiacomo.gabrielli@arm.com return new PRFM64_REG(machInst, rt, rnsp, rm, 89312856Sgiacomo.gabrielli@arm.com type, s * 3); 89412856Sgiacomo.gabrielli@arm.com case 0x1c: 89512856Sgiacomo.gabrielli@arm.com return new STRDFP64_REG(machInst, rt, rnsp, rm, 89612856Sgiacomo.gabrielli@arm.com type, s * 3); 89712856Sgiacomo.gabrielli@arm.com case 0x1d: 89812856Sgiacomo.gabrielli@arm.com return new LDRDFP64_REG(machInst, rt, rnsp, rm, 89912856Sgiacomo.gabrielli@arm.com type, s * 3); 90012856Sgiacomo.gabrielli@arm.com default: 90112856Sgiacomo.gabrielli@arm.com return new Unknown64(machInst); 90212856Sgiacomo.gabrielli@arm.com 90312856Sgiacomo.gabrielli@arm.com } 90412856Sgiacomo.gabrielli@arm.com } 90510037SARM gem5 Developers default: 90610037SARM gem5 Developers return new Unknown64(machInst); 90710037SARM gem5 Developers } 90810037SARM gem5 Developers } else { 90910037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0 91010037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 91110037SARM gem5 Developers case 0x0: 91210037SARM gem5 Developers { 91310037SARM gem5 Developers IntRegIndex rt = 91410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 91510037SARM gem5 Developers IntRegIndex rn = 91610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 91710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 91810037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 91910037SARM gem5 Developers switch (switchVal) { 92010037SARM gem5 Developers case 0x00: 92110037SARM gem5 Developers return new STURB64_IMM(machInst, rt, rnsp, imm); 92210037SARM gem5 Developers case 0x01: 92310037SARM gem5 Developers return new LDURB64_IMM(machInst, rt, rnsp, imm); 92410037SARM gem5 Developers case 0x02: 92510037SARM gem5 Developers return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 92610037SARM gem5 Developers case 0x03: 92710037SARM gem5 Developers return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 92810037SARM gem5 Developers case 0x04: 92910037SARM gem5 Developers return new STURBFP64_IMM(machInst, rt, rnsp, imm); 93010037SARM gem5 Developers case 0x05: 93110037SARM gem5 Developers return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 93210037SARM gem5 Developers case 0x06: 93310037SARM gem5 Developers return new BigFpMemImm("stur", machInst, false, 93410037SARM gem5 Developers rt, rnsp, imm); 93510037SARM gem5 Developers case 0x07: 93610037SARM gem5 Developers return new BigFpMemImm("ldur", machInst, true, 93710037SARM gem5 Developers rt, rnsp, imm); 93810037SARM gem5 Developers case 0x08: 93910037SARM gem5 Developers return new STURH64_IMM(machInst, rt, rnsp, imm); 94010037SARM gem5 Developers case 0x09: 94110037SARM gem5 Developers return new LDURH64_IMM(machInst, rt, rnsp, imm); 94210037SARM gem5 Developers case 0x0a: 94310037SARM gem5 Developers return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 94410037SARM gem5 Developers case 0x0b: 94510037SARM gem5 Developers return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 94610037SARM gem5 Developers case 0x0c: 94710037SARM gem5 Developers return new STURHFP64_IMM(machInst, rt, rnsp, imm); 94810037SARM gem5 Developers case 0x0d: 94910037SARM gem5 Developers return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 95010037SARM gem5 Developers case 0x10: 95110037SARM gem5 Developers return new STURW64_IMM(machInst, rt, rnsp, imm); 95210037SARM gem5 Developers case 0x11: 95310037SARM gem5 Developers return new LDURW64_IMM(machInst, rt, rnsp, imm); 95410037SARM gem5 Developers case 0x12: 95510037SARM gem5 Developers return new LDURSW64_IMM(machInst, rt, rnsp, imm); 95610037SARM gem5 Developers case 0x14: 95710037SARM gem5 Developers return new STURSFP64_IMM(machInst, rt, rnsp, imm); 95810037SARM gem5 Developers case 0x15: 95910037SARM gem5 Developers return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 96010037SARM gem5 Developers case 0x18: 96110037SARM gem5 Developers return new STURX64_IMM(machInst, rt, rnsp, imm); 96210037SARM gem5 Developers case 0x19: 96310037SARM gem5 Developers return new LDURX64_IMM(machInst, rt, rnsp, imm); 96410037SARM gem5 Developers case 0x1a: 96510037SARM gem5 Developers return new PRFUM64_IMM(machInst, rt, rnsp, imm); 96610037SARM gem5 Developers case 0x1c: 96710037SARM gem5 Developers return new STURDFP64_IMM(machInst, rt, rnsp, imm); 96810037SARM gem5 Developers case 0x1d: 96910037SARM gem5 Developers return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 97010037SARM gem5 Developers default: 97110037SARM gem5 Developers return new Unknown64(machInst); 97210037SARM gem5 Developers } 97310037SARM gem5 Developers } 97410037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0, 11:10=01 97510037SARM gem5 Developers case 0x1: 97610037SARM gem5 Developers { 97710037SARM gem5 Developers IntRegIndex rt = 97810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 97910037SARM gem5 Developers IntRegIndex rn = 98010037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 98110037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 98210037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 98310037SARM gem5 Developers switch (switchVal) { 98410037SARM gem5 Developers case 0x00: 98510037SARM gem5 Developers return new STRB64_POST(machInst, rt, rnsp, imm); 98610037SARM gem5 Developers case 0x01: 98710037SARM gem5 Developers return new LDRB64_POST(machInst, rt, rnsp, imm); 98810037SARM gem5 Developers case 0x02: 98910037SARM gem5 Developers return new LDRSBX64_POST(machInst, rt, rnsp, imm); 99010037SARM gem5 Developers case 0x03: 99110037SARM gem5 Developers return new LDRSBW64_POST(machInst, rt, rnsp, imm); 99210037SARM gem5 Developers case 0x04: 99310037SARM gem5 Developers return new STRBFP64_POST(machInst, rt, rnsp, imm); 99410037SARM gem5 Developers case 0x05: 99510037SARM gem5 Developers return new LDRBFP64_POST(machInst, rt, rnsp, imm); 99610037SARM gem5 Developers case 0x06: 99710037SARM gem5 Developers return new BigFpMemPost("str", machInst, false, 99810037SARM gem5 Developers rt, rnsp, imm); 99910037SARM gem5 Developers case 0x07: 100010037SARM gem5 Developers return new BigFpMemPost("ldr", machInst, true, 100110037SARM gem5 Developers rt, rnsp, imm); 100210037SARM gem5 Developers case 0x08: 100310037SARM gem5 Developers return new STRH64_POST(machInst, rt, rnsp, imm); 100410037SARM gem5 Developers case 0x09: 100510037SARM gem5 Developers return new LDRH64_POST(machInst, rt, rnsp, imm); 100610037SARM gem5 Developers case 0x0a: 100710037SARM gem5 Developers return new LDRSHX64_POST(machInst, rt, rnsp, imm); 100810037SARM gem5 Developers case 0x0b: 100910037SARM gem5 Developers return new LDRSHW64_POST(machInst, rt, rnsp, imm); 101010037SARM gem5 Developers case 0x0c: 101110037SARM gem5 Developers return new STRHFP64_POST(machInst, rt, rnsp, imm); 101210037SARM gem5 Developers case 0x0d: 101310037SARM gem5 Developers return new LDRHFP64_POST(machInst, rt, rnsp, imm); 101410037SARM gem5 Developers case 0x10: 101510037SARM gem5 Developers return new STRW64_POST(machInst, rt, rnsp, imm); 101610037SARM gem5 Developers case 0x11: 101710037SARM gem5 Developers return new LDRW64_POST(machInst, rt, rnsp, imm); 101810037SARM gem5 Developers case 0x12: 101910037SARM gem5 Developers return new LDRSW64_POST(machInst, rt, rnsp, imm); 102010037SARM gem5 Developers case 0x14: 102110037SARM gem5 Developers return new STRSFP64_POST(machInst, rt, rnsp, imm); 102210037SARM gem5 Developers case 0x15: 102310037SARM gem5 Developers return new LDRSFP64_POST(machInst, rt, rnsp, imm); 102410037SARM gem5 Developers case 0x18: 102510037SARM gem5 Developers return new STRX64_POST(machInst, rt, rnsp, imm); 102610037SARM gem5 Developers case 0x19: 102710037SARM gem5 Developers return new LDRX64_POST(machInst, rt, rnsp, imm); 102810037SARM gem5 Developers case 0x1c: 102910037SARM gem5 Developers return new STRDFP64_POST(machInst, rt, rnsp, imm); 103010037SARM gem5 Developers case 0x1d: 103110037SARM gem5 Developers return new LDRDFP64_POST(machInst, rt, rnsp, imm); 103210037SARM gem5 Developers default: 103310037SARM gem5 Developers return new Unknown64(machInst); 103410037SARM gem5 Developers } 103510037SARM gem5 Developers } 103610037SARM gem5 Developers case 0x2: 103710037SARM gem5 Developers { 103810037SARM gem5 Developers IntRegIndex rt = 103910037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 104010037SARM gem5 Developers IntRegIndex rn = 104110037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 104210037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 104310037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 104410037SARM gem5 Developers switch (switchVal) { 104510037SARM gem5 Developers case 0x00: 104610037SARM gem5 Developers return new STTRB64_IMM(machInst, rt, rnsp, imm); 104710037SARM gem5 Developers case 0x01: 104810037SARM gem5 Developers return new LDTRB64_IMM(machInst, rt, rnsp, imm); 104910037SARM gem5 Developers case 0x02: 105010037SARM gem5 Developers return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 105110037SARM gem5 Developers case 0x03: 105210037SARM gem5 Developers return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 105310037SARM gem5 Developers case 0x08: 105410037SARM gem5 Developers return new STTRH64_IMM(machInst, rt, rnsp, imm); 105510037SARM gem5 Developers case 0x09: 105610037SARM gem5 Developers return new LDTRH64_IMM(machInst, rt, rnsp, imm); 105710037SARM gem5 Developers case 0x0a: 105810037SARM gem5 Developers return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 105910037SARM gem5 Developers case 0x0b: 106010037SARM gem5 Developers return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 106110037SARM gem5 Developers case 0x10: 106210037SARM gem5 Developers return new STTRW64_IMM(machInst, rt, rnsp, imm); 106310037SARM gem5 Developers case 0x11: 106410037SARM gem5 Developers return new LDTRW64_IMM(machInst, rt, rnsp, imm); 106510037SARM gem5 Developers case 0x12: 106610037SARM gem5 Developers return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 106710037SARM gem5 Developers case 0x18: 106810037SARM gem5 Developers return new STTRX64_IMM(machInst, rt, rnsp, imm); 106910037SARM gem5 Developers case 0x19: 107010037SARM gem5 Developers return new LDTRX64_IMM(machInst, rt, rnsp, imm); 107110037SARM gem5 Developers default: 107210037SARM gem5 Developers return new Unknown64(machInst); 107310037SARM gem5 Developers } 107410037SARM gem5 Developers } 107510037SARM gem5 Developers case 0x3: 107610037SARM gem5 Developers { 107710037SARM gem5 Developers IntRegIndex rt = 107810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 107910037SARM gem5 Developers IntRegIndex rn = 108010037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 108110037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 108210037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 108310037SARM gem5 Developers switch (switchVal) { 108410037SARM gem5 Developers case 0x00: 108510037SARM gem5 Developers return new STRB64_PRE(machInst, rt, rnsp, imm); 108610037SARM gem5 Developers case 0x01: 108710037SARM gem5 Developers return new LDRB64_PRE(machInst, rt, rnsp, imm); 108810037SARM gem5 Developers case 0x02: 108910037SARM gem5 Developers return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 109010037SARM gem5 Developers case 0x03: 109110037SARM gem5 Developers return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 109210037SARM gem5 Developers case 0x04: 109310037SARM gem5 Developers return new STRBFP64_PRE(machInst, rt, rnsp, imm); 109410037SARM gem5 Developers case 0x05: 109510037SARM gem5 Developers return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 109610037SARM gem5 Developers case 0x06: 109710037SARM gem5 Developers return new BigFpMemPre("str", machInst, false, 109810037SARM gem5 Developers rt, rnsp, imm); 109910037SARM gem5 Developers case 0x07: 110010037SARM gem5 Developers return new BigFpMemPre("ldr", machInst, true, 110110037SARM gem5 Developers rt, rnsp, imm); 110210037SARM gem5 Developers case 0x08: 110310037SARM gem5 Developers return new STRH64_PRE(machInst, rt, rnsp, imm); 110410037SARM gem5 Developers case 0x09: 110510037SARM gem5 Developers return new LDRH64_PRE(machInst, rt, rnsp, imm); 110610037SARM gem5 Developers case 0x0a: 110710037SARM gem5 Developers return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 110810037SARM gem5 Developers case 0x0b: 110910037SARM gem5 Developers return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 111010037SARM gem5 Developers case 0x0c: 111110037SARM gem5 Developers return new STRHFP64_PRE(machInst, rt, rnsp, imm); 111210037SARM gem5 Developers case 0x0d: 111310037SARM gem5 Developers return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 111410037SARM gem5 Developers case 0x10: 111510037SARM gem5 Developers return new STRW64_PRE(machInst, rt, rnsp, imm); 111610037SARM gem5 Developers case 0x11: 111710037SARM gem5 Developers return new LDRW64_PRE(machInst, rt, rnsp, imm); 111810037SARM gem5 Developers case 0x12: 111910037SARM gem5 Developers return new LDRSW64_PRE(machInst, rt, rnsp, imm); 112010037SARM gem5 Developers case 0x14: 112110037SARM gem5 Developers return new STRSFP64_PRE(machInst, rt, rnsp, imm); 112210037SARM gem5 Developers case 0x15: 112310037SARM gem5 Developers return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 112410037SARM gem5 Developers case 0x18: 112510037SARM gem5 Developers return new STRX64_PRE(machInst, rt, rnsp, imm); 112610037SARM gem5 Developers case 0x19: 112710037SARM gem5 Developers return new LDRX64_PRE(machInst, rt, rnsp, imm); 112810037SARM gem5 Developers case 0x1c: 112910037SARM gem5 Developers return new STRDFP64_PRE(machInst, rt, rnsp, imm); 113010037SARM gem5 Developers case 0x1d: 113110037SARM gem5 Developers return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 113210037SARM gem5 Developers default: 113310037SARM gem5 Developers return new Unknown64(machInst); 113410037SARM gem5 Developers } 113510037SARM gem5 Developers } 113612595Ssiddhesh.poyarekar@gmail.com default: 113712595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 113810037SARM gem5 Developers } 113910037SARM gem5 Developers } 114010037SARM gem5 Developers } 114112595Ssiddhesh.poyarekar@gmail.com default: 114212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 114310037SARM gem5 Developers } 114410037SARM gem5 Developers return new FailUnimplemented("Unhandled Case1", machInst); 114510037SARM gem5 Developers } 114610037SARM gem5 Developers} 114710037SARM gem5 Developers}}; 114810037SARM gem5 Developers 114910037SARM gem5 Developersoutput decoder {{ 115010037SARM gem5 Developersnamespace Aarch64 115110037SARM gem5 Developers{ 115210037SARM gem5 Developers StaticInstPtr 115310037SARM gem5 Developers decodeDataProcReg(ExtMachInst machInst) 115410037SARM gem5 Developers { 115510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 28) << 1) | 115610037SARM gem5 Developers (bits(machInst, 24) << 0); 115710037SARM gem5 Developers switch (switchVal) { 115810037SARM gem5 Developers case 0x0: 115910037SARM gem5 Developers { 116010037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 21) << 0) | 116110037SARM gem5 Developers (bits(machInst, 30, 29) << 1); 116210037SARM gem5 Developers ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 116310037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 116410037SARM gem5 Developers bool sf = bits(machInst, 31); 116510037SARM gem5 Developers if (!sf && (imm6 & 0x20)) 116610037SARM gem5 Developers return new Unknown64(machInst); 116710037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 116810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 116910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 117010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 117110037SARM gem5 Developers 117210037SARM gem5 Developers switch (switchVal) { 117310037SARM gem5 Developers case 0x0: 117410337SAndrew.Bardsley@arm.com return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 117510037SARM gem5 Developers case 0x1: 117610337SAndrew.Bardsley@arm.com return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 117710037SARM gem5 Developers case 0x2: 117810337SAndrew.Bardsley@arm.com return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 117910037SARM gem5 Developers case 0x3: 118010337SAndrew.Bardsley@arm.com return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 118110037SARM gem5 Developers case 0x4: 118210337SAndrew.Bardsley@arm.com return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 118310037SARM gem5 Developers case 0x5: 118410337SAndrew.Bardsley@arm.com return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 118510037SARM gem5 Developers case 0x6: 118610337SAndrew.Bardsley@arm.com return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 118710037SARM gem5 Developers case 0x7: 118810337SAndrew.Bardsley@arm.com return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 118912595Ssiddhesh.poyarekar@gmail.com default: 119012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 119110037SARM gem5 Developers } 119210037SARM gem5 Developers } 119310037SARM gem5 Developers case 0x1: 119410037SARM gem5 Developers { 119510037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 119610037SARM gem5 Developers if (bits(machInst, 21) == 0) { 119710037SARM gem5 Developers ArmShiftType type = 119810037SARM gem5 Developers (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 119910037SARM gem5 Developers if (type == ROR) 120010037SARM gem5 Developers return new Unknown64(machInst); 120110037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 120210037SARM gem5 Developers if (!bits(machInst, 31) && bits(imm6, 5)) 120310037SARM gem5 Developers return new Unknown64(machInst); 120410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 120510337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 120610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 120710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 120810037SARM gem5 Developers switch (switchVal) { 120910037SARM gem5 Developers case 0x0: 121010337SAndrew.Bardsley@arm.com return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 121110037SARM gem5 Developers case 0x1: 121210337SAndrew.Bardsley@arm.com return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 121310037SARM gem5 Developers case 0x2: 121410337SAndrew.Bardsley@arm.com return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 121510037SARM gem5 Developers case 0x3: 121610337SAndrew.Bardsley@arm.com return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 121712595Ssiddhesh.poyarekar@gmail.com default: 121812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 121910037SARM gem5 Developers } 122010037SARM gem5 Developers } else { 122110037SARM gem5 Developers if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 122210037SARM gem5 Developers return new Unknown64(machInst); 122310037SARM gem5 Developers ArmExtendType type = 122410037SARM gem5 Developers (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 122510037SARM gem5 Developers uint8_t imm3 = bits(machInst, 12, 10); 122610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 122710037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 122810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 122910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 123010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 123110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 123210037SARM gem5 Developers 123310037SARM gem5 Developers switch (switchVal) { 123410037SARM gem5 Developers case 0x0: 123510037SARM gem5 Developers return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 123610037SARM gem5 Developers case 0x1: 123710337SAndrew.Bardsley@arm.com return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 123810037SARM gem5 Developers case 0x2: 123910037SARM gem5 Developers return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 124010037SARM gem5 Developers case 0x3: 124110337SAndrew.Bardsley@arm.com return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 124212595Ssiddhesh.poyarekar@gmail.com default: 124312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 124410037SARM gem5 Developers } 124510037SARM gem5 Developers } 124610037SARM gem5 Developers } 124710037SARM gem5 Developers case 0x2: 124810037SARM gem5 Developers { 124910037SARM gem5 Developers if (bits(machInst, 21) == 1) 125010037SARM gem5 Developers return new Unknown64(machInst); 125110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 125210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 125310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 125410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 125510037SARM gem5 Developers switch (bits(machInst, 23, 22)) { 125610037SARM gem5 Developers case 0x0: 125710037SARM gem5 Developers { 125810037SARM gem5 Developers if (bits(machInst, 15, 10)) 125910037SARM gem5 Developers return new Unknown64(machInst); 126010037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 126110037SARM gem5 Developers switch (switchVal) { 126210037SARM gem5 Developers case 0x0: 126310337SAndrew.Bardsley@arm.com return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 126410037SARM gem5 Developers case 0x1: 126510337SAndrew.Bardsley@arm.com return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 126610037SARM gem5 Developers case 0x2: 126710337SAndrew.Bardsley@arm.com return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 126810037SARM gem5 Developers case 0x3: 126910337SAndrew.Bardsley@arm.com return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 127012595Ssiddhesh.poyarekar@gmail.com default: 127112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 127210037SARM gem5 Developers } 127310037SARM gem5 Developers } 127410037SARM gem5 Developers case 0x1: 127510037SARM gem5 Developers { 127610037SARM gem5 Developers if ((bits(machInst, 4) == 1) || 127710037SARM gem5 Developers (bits(machInst, 10) == 1) || 127810037SARM gem5 Developers (bits(machInst, 29) == 0)) { 127910037SARM gem5 Developers return new Unknown64(machInst); 128010037SARM gem5 Developers } 128110037SARM gem5 Developers ConditionCode cond = 128210037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 128310037SARM gem5 Developers uint8_t flags = bits(machInst, 3, 0); 128410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 128510037SARM gem5 Developers if (bits(machInst, 11) == 0) { 128610037SARM gem5 Developers IntRegIndex rm = 128710037SARM gem5 Developers (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 128810037SARM gem5 Developers if (bits(machInst, 30) == 0) { 128910037SARM gem5 Developers return new CcmnReg64(machInst, rn, rm, cond, flags); 129010037SARM gem5 Developers } else { 129110037SARM gem5 Developers return new CcmpReg64(machInst, rn, rm, cond, flags); 129210037SARM gem5 Developers } 129310037SARM gem5 Developers } else { 129410037SARM gem5 Developers uint8_t imm5 = bits(machInst, 20, 16); 129510037SARM gem5 Developers if (bits(machInst, 30) == 0) { 129610037SARM gem5 Developers return new CcmnImm64(machInst, rn, imm5, cond, flags); 129710037SARM gem5 Developers } else { 129810037SARM gem5 Developers return new CcmpImm64(machInst, rn, imm5, cond, flags); 129910037SARM gem5 Developers } 130010037SARM gem5 Developers } 130110037SARM gem5 Developers } 130210037SARM gem5 Developers case 0x2: 130310037SARM gem5 Developers { 130410037SARM gem5 Developers if (bits(machInst, 29) == 1 || 130510037SARM gem5 Developers bits(machInst, 11) == 1) { 130610037SARM gem5 Developers return new Unknown64(machInst); 130710037SARM gem5 Developers } 130810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 10) << 0) | 130910037SARM gem5 Developers (bits(machInst, 30) << 1); 131010037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 131110337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 131210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 131310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 131410037SARM gem5 Developers ConditionCode cond = 131510037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 131610037SARM gem5 Developers switch (switchVal) { 131710037SARM gem5 Developers case 0x0: 131810337SAndrew.Bardsley@arm.com return new Csel64(machInst, rdzr, rn, rm, cond); 131910037SARM gem5 Developers case 0x1: 132010337SAndrew.Bardsley@arm.com return new Csinc64(machInst, rdzr, rn, rm, cond); 132110037SARM gem5 Developers case 0x2: 132210337SAndrew.Bardsley@arm.com return new Csinv64(machInst, rdzr, rn, rm, cond); 132310037SARM gem5 Developers case 0x3: 132410337SAndrew.Bardsley@arm.com return new Csneg64(machInst, rdzr, rn, rm, cond); 132512595Ssiddhesh.poyarekar@gmail.com default: 132612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 132710037SARM gem5 Developers } 132810037SARM gem5 Developers } 132910037SARM gem5 Developers case 0x3: 133010037SARM gem5 Developers if (bits(machInst, 30) == 0) { 133110037SARM gem5 Developers if (bits(machInst, 29) != 0) 133210037SARM gem5 Developers return new Unknown64(machInst); 133310037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 133410037SARM gem5 Developers switch (switchVal) { 133510037SARM gem5 Developers case 0x2: 133610337SAndrew.Bardsley@arm.com return new Udiv64(machInst, rdzr, rn, rm); 133710037SARM gem5 Developers case 0x3: 133810337SAndrew.Bardsley@arm.com return new Sdiv64(machInst, rdzr, rn, rm); 133910037SARM gem5 Developers case 0x8: 134010337SAndrew.Bardsley@arm.com return new Lslv64(machInst, rdzr, rn, rm); 134110037SARM gem5 Developers case 0x9: 134210337SAndrew.Bardsley@arm.com return new Lsrv64(machInst, rdzr, rn, rm); 134310037SARM gem5 Developers case 0xa: 134410337SAndrew.Bardsley@arm.com return new Asrv64(machInst, rdzr, rn, rm); 134510037SARM gem5 Developers case 0xb: 134610337SAndrew.Bardsley@arm.com return new Rorv64(machInst, rdzr, rn, rm); 134712258Sgiacomo.travaglini@arm.com case 0x10: 134812258Sgiacomo.travaglini@arm.com return new Crc32b64(machInst, rdzr, rn, rm); 134912258Sgiacomo.travaglini@arm.com case 0x11: 135012258Sgiacomo.travaglini@arm.com return new Crc32h64(machInst, rdzr, rn, rm); 135112258Sgiacomo.travaglini@arm.com case 0x12: 135212258Sgiacomo.travaglini@arm.com return new Crc32w64(machInst, rdzr, rn, rm); 135312258Sgiacomo.travaglini@arm.com case 0x13: 135412258Sgiacomo.travaglini@arm.com return new Crc32x64(machInst, rdzr, rn, rm); 135512258Sgiacomo.travaglini@arm.com case 0x14: 135612258Sgiacomo.travaglini@arm.com return new Crc32cb64(machInst, rdzr, rn, rm); 135712258Sgiacomo.travaglini@arm.com case 0x15: 135812258Sgiacomo.travaglini@arm.com return new Crc32ch64(machInst, rdzr, rn, rm); 135912258Sgiacomo.travaglini@arm.com case 0x16: 136012258Sgiacomo.travaglini@arm.com return new Crc32cw64(machInst, rdzr, rn, rm); 136112258Sgiacomo.travaglini@arm.com case 0x17: 136212258Sgiacomo.travaglini@arm.com return new Crc32cx64(machInst, rdzr, rn, rm); 136310037SARM gem5 Developers default: 136410037SARM gem5 Developers return new Unknown64(machInst); 136510037SARM gem5 Developers } 136610037SARM gem5 Developers } else { 136710037SARM gem5 Developers if (bits(machInst, 20, 16) != 0 || 136810037SARM gem5 Developers bits(machInst, 29) != 0) { 136910037SARM gem5 Developers return new Unknown64(machInst); 137010037SARM gem5 Developers } 137110037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 137210037SARM gem5 Developers switch (switchVal) { 137310037SARM gem5 Developers case 0x0: 137410337SAndrew.Bardsley@arm.com return new Rbit64(machInst, rdzr, rn); 137510037SARM gem5 Developers case 0x1: 137610337SAndrew.Bardsley@arm.com return new Rev1664(machInst, rdzr, rn); 137710037SARM gem5 Developers case 0x2: 137810037SARM gem5 Developers if (bits(machInst, 31) == 0) 137910337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 138010037SARM gem5 Developers else 138110337SAndrew.Bardsley@arm.com return new Rev3264(machInst, rdzr, rn); 138210037SARM gem5 Developers case 0x3: 138310037SARM gem5 Developers if (bits(machInst, 31) != 1) 138410037SARM gem5 Developers return new Unknown64(machInst); 138510337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 138610037SARM gem5 Developers case 0x4: 138710337SAndrew.Bardsley@arm.com return new Clz64(machInst, rdzr, rn); 138810037SARM gem5 Developers case 0x5: 138910337SAndrew.Bardsley@arm.com return new Cls64(machInst, rdzr, rn); 139012595Ssiddhesh.poyarekar@gmail.com default: 139112595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 139210037SARM gem5 Developers } 139310037SARM gem5 Developers } 139412595Ssiddhesh.poyarekar@gmail.com default: 139512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 139610037SARM gem5 Developers } 139710037SARM gem5 Developers } 139810037SARM gem5 Developers case 0x3: 139910037SARM gem5 Developers { 140010037SARM gem5 Developers if (bits(machInst, 30, 29) != 0x0 || 140110037SARM gem5 Developers (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 140210037SARM gem5 Developers return new Unknown64(machInst); 140310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 140410337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 140510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 140610037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 140710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 140810037SARM gem5 Developers switch (bits(machInst, 23, 21)) { 140910037SARM gem5 Developers case 0x0: 141010037SARM gem5 Developers if (bits(machInst, 15) == 0) 141110337SAndrew.Bardsley@arm.com return new Madd64(machInst, rdzr, ra, rn, rm); 141210037SARM gem5 Developers else 141310337SAndrew.Bardsley@arm.com return new Msub64(machInst, rdzr, ra, rn, rm); 141410037SARM gem5 Developers case 0x1: 141510037SARM gem5 Developers if (bits(machInst, 15) == 0) 141610337SAndrew.Bardsley@arm.com return new Smaddl64(machInst, rdzr, ra, rn, rm); 141710037SARM gem5 Developers else 141810337SAndrew.Bardsley@arm.com return new Smsubl64(machInst, rdzr, ra, rn, rm); 141910037SARM gem5 Developers case 0x2: 142010037SARM gem5 Developers if (bits(machInst, 15) != 0) 142110037SARM gem5 Developers return new Unknown64(machInst); 142210337SAndrew.Bardsley@arm.com return new Smulh64(machInst, rdzr, rn, rm); 142310037SARM gem5 Developers case 0x5: 142410037SARM gem5 Developers if (bits(machInst, 15) == 0) 142510337SAndrew.Bardsley@arm.com return new Umaddl64(machInst, rdzr, ra, rn, rm); 142610037SARM gem5 Developers else 142710337SAndrew.Bardsley@arm.com return new Umsubl64(machInst, rdzr, ra, rn, rm); 142810037SARM gem5 Developers case 0x6: 142910037SARM gem5 Developers if (bits(machInst, 15) != 0) 143010037SARM gem5 Developers return new Unknown64(machInst); 143110337SAndrew.Bardsley@arm.com return new Umulh64(machInst, rdzr, rn, rm); 143210037SARM gem5 Developers default: 143310037SARM gem5 Developers return new Unknown64(machInst); 143410037SARM gem5 Developers } 143510037SARM gem5 Developers } 143612595Ssiddhesh.poyarekar@gmail.com default: 143712595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 143810037SARM gem5 Developers } 143910037SARM gem5 Developers return new FailUnimplemented("Unhandled Case2", machInst); 144010037SARM gem5 Developers } 144110037SARM gem5 Developers} 144210037SARM gem5 Developers}}; 144310037SARM gem5 Developers 144410037SARM gem5 Developersoutput decoder {{ 144510037SARM gem5 Developersnamespace Aarch64 144610037SARM gem5 Developers{ 144711165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 144810037SARM gem5 Developers StaticInstPtr 144910037SARM gem5 Developers decodeAdvSIMD(ExtMachInst machInst) 145010037SARM gem5 Developers { 145110037SARM gem5 Developers if (bits(machInst, 24) == 1) { 145210037SARM gem5 Developers if (bits(machInst, 10) == 0) { 145311165SRekai.GonzalezAlberquilla@arm.com return decodeNeonIndexedElem<DecoderFeatures>(machInst); 145410037SARM gem5 Developers } else if (bits(machInst, 23) == 1) { 145510037SARM gem5 Developers return new Unknown64(machInst); 145610037SARM gem5 Developers } else { 145710037SARM gem5 Developers if (bits(machInst, 22, 19)) { 145810037SARM gem5 Developers return decodeNeonShiftByImm(machInst); 145910037SARM gem5 Developers } else { 146010037SARM gem5 Developers return decodeNeonModImm(machInst); 146110037SARM gem5 Developers } 146210037SARM gem5 Developers } 146310037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 146410037SARM gem5 Developers if (bits(machInst, 10) == 1) { 146511165SRekai.GonzalezAlberquilla@arm.com return decodeNeon3Same<DecoderFeatures>(machInst); 146610037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 146710037SARM gem5 Developers return decodeNeon3Diff(machInst); 146810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 146910037SARM gem5 Developers return decodeNeon2RegMisc(machInst); 147013171Sgiacomo.travaglini@arm.com } else if (bits(machInst, 20, 17) == 0x4) { 147113171Sgiacomo.travaglini@arm.com return decodeCryptoAES(machInst); 147210037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 147310037SARM gem5 Developers return decodeNeonAcrossLanes(machInst); 147410037SARM gem5 Developers } else { 147510037SARM gem5 Developers return new Unknown64(machInst); 147610037SARM gem5 Developers } 147710037SARM gem5 Developers } else if (bits(machInst, 24) || 147810037SARM gem5 Developers bits(machInst, 21) || 147910037SARM gem5 Developers bits(machInst, 15)) { 148010037SARM gem5 Developers return new Unknown64(machInst); 148110037SARM gem5 Developers } else if (bits(machInst, 10) == 1) { 148210037SARM gem5 Developers if (bits(machInst, 23, 22)) 148310037SARM gem5 Developers return new Unknown64(machInst); 148410037SARM gem5 Developers return decodeNeonCopy(machInst); 148510037SARM gem5 Developers } else if (bits(machInst, 29) == 1) { 148610037SARM gem5 Developers return decodeNeonExt(machInst); 148710037SARM gem5 Developers } else if (bits(machInst, 11) == 1) { 148810037SARM gem5 Developers return decodeNeonZipUzpTrn(machInst); 148910037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0x0) { 149010037SARM gem5 Developers return decodeNeonTblTbx(machInst); 149110037SARM gem5 Developers } else { 149210037SARM gem5 Developers return new Unknown64(machInst); 149310037SARM gem5 Developers } 149410037SARM gem5 Developers return new FailUnimplemented("Unhandled Case3", machInst); 149510037SARM gem5 Developers } 149610037SARM gem5 Developers} 149710037SARM gem5 Developers}}; 149810037SARM gem5 Developers 149910037SARM gem5 Developers 150010037SARM gem5 Developersoutput decoder {{ 150110037SARM gem5 Developersnamespace Aarch64 150210037SARM gem5 Developers{ 150310037SARM gem5 Developers StaticInstPtr 150410037SARM gem5 Developers // bit 30=0, 28:25=1111 150510037SARM gem5 Developers decodeFp(ExtMachInst machInst) 150610037SARM gem5 Developers { 150710037SARM gem5 Developers if (bits(machInst, 24) == 1) { 150810037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 150910037SARM gem5 Developers return new Unknown64(machInst); 151010037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 151110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 151210037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 151310037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 151410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 151510037SARM gem5 Developers (bits(machInst, 15) << 0); 151610037SARM gem5 Developers switch (switchVal) { 151710037SARM gem5 Developers case 0x0: // FMADD Sd = Sa + Sn*Sm 151810037SARM gem5 Developers return new FMAddS(machInst, rd, rn, rm, ra); 151910037SARM gem5 Developers case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 152010037SARM gem5 Developers return new FMSubS(machInst, rd, rn, rm, ra); 152110037SARM gem5 Developers case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 152210037SARM gem5 Developers return new FNMAddS(machInst, rd, rn, rm, ra); 152310037SARM gem5 Developers case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 152410037SARM gem5 Developers return new FNMSubS(machInst, rd, rn, rm, ra); 152510037SARM gem5 Developers case 0x4: // FMADD Dd = Da + Dn*Dm 152610037SARM gem5 Developers return new FMAddD(machInst, rd, rn, rm, ra); 152710037SARM gem5 Developers case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 152810037SARM gem5 Developers return new FMSubD(machInst, rd, rn, rm, ra); 152910037SARM gem5 Developers case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 153010037SARM gem5 Developers return new FNMAddD(machInst, rd, rn, rm, ra); 153110037SARM gem5 Developers case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 153210037SARM gem5 Developers return new FNMSubD(machInst, rd, rn, rm, ra); 153310037SARM gem5 Developers default: 153410037SARM gem5 Developers return new Unknown64(machInst); 153510037SARM gem5 Developers } 153610037SARM gem5 Developers } else if (bits(machInst, 21) == 0) { 153710037SARM gem5 Developers bool s = bits(machInst, 29); 153810037SARM gem5 Developers if (s) 153910037SARM gem5 Developers return new Unknown64(machInst); 154010037SARM gem5 Developers uint8_t switchVal = bits(machInst, 20, 16); 154110037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 154210037SARM gem5 Developers uint8_t scale = bits(machInst, 15, 10); 154310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 154410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 154510037SARM gem5 Developers if (bits(machInst, 18, 17) == 3 && scale != 0) 154610037SARM gem5 Developers return new Unknown64(machInst); 154710037SARM gem5 Developers // 30:24=0011110, 21=0 154810037SARM gem5 Developers switch (switchVal) { 154910037SARM gem5 Developers case 0x00: 155010037SARM gem5 Developers return new FailUnimplemented("fcvtns", machInst); 155110037SARM gem5 Developers case 0x01: 155210037SARM gem5 Developers return new FailUnimplemented("fcvtnu", machInst); 155310037SARM gem5 Developers case 0x02: 155410037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 155510037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 155610037SARM gem5 Developers return new FcvtSFixedFpSW(machInst, rd, rn, scale); 155710037SARM gem5 Developers case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 155810037SARM gem5 Developers return new FcvtSFixedFpDW(machInst, rd, rn, scale); 155910037SARM gem5 Developers case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 156010037SARM gem5 Developers return new FcvtSFixedFpSX(machInst, rd, rn, scale); 156110037SARM gem5 Developers case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 156210037SARM gem5 Developers return new FcvtSFixedFpDX(machInst, rd, rn, scale); 156310037SARM gem5 Developers default: 156410037SARM gem5 Developers return new Unknown64(machInst); 156510037SARM gem5 Developers } 156610037SARM gem5 Developers case 0x03: 156710037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 156810037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 156910037SARM gem5 Developers return new FcvtUFixedFpSW(machInst, rd, rn, scale); 157010037SARM gem5 Developers case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 157110037SARM gem5 Developers return new FcvtUFixedFpDW(machInst, rd, rn, scale); 157210037SARM gem5 Developers case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 157310037SARM gem5 Developers return new FcvtUFixedFpSX(machInst, rd, rn, scale); 157410037SARM gem5 Developers case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 157510037SARM gem5 Developers return new FcvtUFixedFpDX(machInst, rd, rn, scale); 157610037SARM gem5 Developers default: 157710037SARM gem5 Developers return new Unknown64(machInst); 157810037SARM gem5 Developers } 157910037SARM gem5 Developers case 0x04: 158010037SARM gem5 Developers return new FailUnimplemented("fcvtas", machInst); 158110037SARM gem5 Developers case 0x05: 158210037SARM gem5 Developers return new FailUnimplemented("fcvtau", machInst); 158310037SARM gem5 Developers case 0x08: 158410037SARM gem5 Developers return new FailUnimplemented("fcvtps", machInst); 158510037SARM gem5 Developers case 0x09: 158610037SARM gem5 Developers return new FailUnimplemented("fcvtpu", machInst); 158710037SARM gem5 Developers case 0x0e: 158810037SARM gem5 Developers return new FailUnimplemented("fmov elem. to 64", machInst); 158910037SARM gem5 Developers case 0x0f: 159010037SARM gem5 Developers return new FailUnimplemented("fmov 64 bit", machInst); 159110037SARM gem5 Developers case 0x10: 159210037SARM gem5 Developers return new FailUnimplemented("fcvtms", machInst); 159310037SARM gem5 Developers case 0x11: 159410037SARM gem5 Developers return new FailUnimplemented("fcvtmu", machInst); 159510037SARM gem5 Developers case 0x18: 159610037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 159710037SARM gem5 Developers case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 159810037SARM gem5 Developers return new FcvtFpSFixedSW(machInst, rd, rn, scale); 159910037SARM gem5 Developers case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 160010037SARM gem5 Developers return new FcvtFpSFixedDW(machInst, rd, rn, scale); 160110037SARM gem5 Developers case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 160210037SARM gem5 Developers return new FcvtFpSFixedSX(machInst, rd, rn, scale); 160310037SARM gem5 Developers case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 160410037SARM gem5 Developers return new FcvtFpSFixedDX(machInst, rd, rn, scale); 160510037SARM gem5 Developers default: 160610037SARM gem5 Developers return new Unknown64(machInst); 160710037SARM gem5 Developers } 160810037SARM gem5 Developers case 0x19: 160910037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 161010037SARM gem5 Developers case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 161110037SARM gem5 Developers return new FcvtFpUFixedSW(machInst, rd, rn, scale); 161210037SARM gem5 Developers case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 161310037SARM gem5 Developers return new FcvtFpUFixedDW(machInst, rd, rn, scale); 161410037SARM gem5 Developers case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 161510037SARM gem5 Developers return new FcvtFpUFixedSX(machInst, rd, rn, scale); 161610037SARM gem5 Developers case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 161710037SARM gem5 Developers return new FcvtFpUFixedDX(machInst, rd, rn, scale); 161810037SARM gem5 Developers default: 161910037SARM gem5 Developers return new Unknown64(machInst); 162010037SARM gem5 Developers } 162112595Ssiddhesh.poyarekar@gmail.com default: 162212595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 162310037SARM gem5 Developers } 162410037SARM gem5 Developers } else { 162510037SARM gem5 Developers // 30=0, 28:24=11110, 21=1 162610037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 162710037SARM gem5 Developers uint8_t imm8 = bits(machInst, 20, 13); 162810037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 162910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 163010037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 163110037SARM gem5 Developers case 0x0: 163210037SARM gem5 Developers if (bits(machInst, 12) == 1) { 163310037SARM gem5 Developers if (bits(machInst, 31) || 163410037SARM gem5 Developers bits(machInst, 29) || 163510037SARM gem5 Developers bits(machInst, 9, 5)) { 163610037SARM gem5 Developers return new Unknown64(machInst); 163710037SARM gem5 Developers } 163810037SARM gem5 Developers // 31:29=000, 28:24=11110, 21=1, 12:10=100 163910037SARM gem5 Developers if (type == 0) { 164010037SARM gem5 Developers // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 164110037SARM gem5 Developers // :imm8<5:0>:Zeros(19) 164213120SEdmund.Grimley-Evans@arm.com uint32_t imm = vfp_modified_imm(imm8, 164313120SEdmund.Grimley-Evans@arm.com FpDataType::Fp32); 164410037SARM gem5 Developers return new FmovImmS(machInst, rd, imm); 164510037SARM gem5 Developers } else if (type == 1) { 164610037SARM gem5 Developers // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 164710037SARM gem5 Developers // :imm8<5:0>:Zeros(48) 164813120SEdmund.Grimley-Evans@arm.com uint64_t imm = vfp_modified_imm(imm8, 164913120SEdmund.Grimley-Evans@arm.com FpDataType::Fp64); 165010037SARM gem5 Developers return new FmovImmD(machInst, rd, imm); 165110037SARM gem5 Developers } else { 165210037SARM gem5 Developers return new Unknown64(machInst); 165310037SARM gem5 Developers } 165410037SARM gem5 Developers } else if (bits(machInst, 13) == 1) { 165510037SARM gem5 Developers if (bits(machInst, 31) || 165610037SARM gem5 Developers bits(machInst, 29) || 165710037SARM gem5 Developers bits(machInst, 15, 14) || 165810037SARM gem5 Developers bits(machInst, 23) || 165910037SARM gem5 Developers bits(machInst, 2, 0)) { 166010037SARM gem5 Developers return new Unknown64(machInst); 166110037SARM gem5 Developers } 166210037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 166310037SARM gem5 Developers (bits(machInst, 22) << 2); 166410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) 166510037SARM gem5 Developers bits(machInst, 20, 16); 166610037SARM gem5 Developers // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 166710037SARM gem5 Developers switch (switchVal) { 166810037SARM gem5 Developers case 0x0: 166910037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,Sm) 167010037SARM gem5 Developers return new FCmpRegS(machInst, rn, rm); 167110037SARM gem5 Developers case 0x1: 167210037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,0.0) 167310037SARM gem5 Developers return new FCmpImmS(machInst, rn, 0); 167410037SARM gem5 Developers case 0x2: 167510037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,Sm) 167610037SARM gem5 Developers return new FCmpERegS(machInst, rn, rm); 167710037SARM gem5 Developers case 0x3: 167810037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,0.0) 167910037SARM gem5 Developers return new FCmpEImmS(machInst, rn, 0); 168010037SARM gem5 Developers case 0x4: 168110037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,Dm) 168210037SARM gem5 Developers return new FCmpRegD(machInst, rn, rm); 168310037SARM gem5 Developers case 0x5: 168410037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,0.0) 168510037SARM gem5 Developers return new FCmpImmD(machInst, rn, 0); 168610037SARM gem5 Developers case 0x6: 168710037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,Dm) 168810037SARM gem5 Developers return new FCmpERegD(machInst, rn, rm); 168910037SARM gem5 Developers case 0x7: 169010037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,0.0) 169110037SARM gem5 Developers return new FCmpEImmD(machInst, rn, 0); 169210037SARM gem5 Developers default: 169310037SARM gem5 Developers return new Unknown64(machInst); 169410037SARM gem5 Developers } 169510037SARM gem5 Developers } else if (bits(machInst, 14) == 1) { 169610037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 169710037SARM gem5 Developers return new Unknown64(machInst); 169810037SARM gem5 Developers uint8_t opcode = bits(machInst, 20, 15); 169910037SARM gem5 Developers // Bits 31:24=00011110, 21=1, 14:10=10000 170010037SARM gem5 Developers switch (opcode) { 170110037SARM gem5 Developers case 0x0: 170210037SARM gem5 Developers if (type == 0) 170310037SARM gem5 Developers // FMOV Sd = Sn 170410037SARM gem5 Developers return new FmovRegS(machInst, rd, rn); 170510037SARM gem5 Developers else if (type == 1) 170610037SARM gem5 Developers // FMOV Dd = Dn 170710037SARM gem5 Developers return new FmovRegD(machInst, rd, rn); 170810037SARM gem5 Developers break; 170910037SARM gem5 Developers case 0x1: 171010037SARM gem5 Developers if (type == 0) 171110037SARM gem5 Developers // FABS Sd = abs(Sn) 171210037SARM gem5 Developers return new FAbsS(machInst, rd, rn); 171310037SARM gem5 Developers else if (type == 1) 171410037SARM gem5 Developers // FABS Dd = abs(Dn) 171510037SARM gem5 Developers return new FAbsD(machInst, rd, rn); 171610037SARM gem5 Developers break; 171710037SARM gem5 Developers case 0x2: 171810037SARM gem5 Developers if (type == 0) 171910037SARM gem5 Developers // FNEG Sd = -Sn 172010037SARM gem5 Developers return new FNegS(machInst, rd, rn); 172110037SARM gem5 Developers else if (type == 1) 172210037SARM gem5 Developers // FNEG Dd = -Dn 172310037SARM gem5 Developers return new FNegD(machInst, rd, rn); 172410037SARM gem5 Developers break; 172510037SARM gem5 Developers case 0x3: 172610037SARM gem5 Developers if (type == 0) 172710037SARM gem5 Developers // FSQRT Sd = sqrt(Sn) 172810037SARM gem5 Developers return new FSqrtS(machInst, rd, rn); 172910037SARM gem5 Developers else if (type == 1) 173010037SARM gem5 Developers // FSQRT Dd = sqrt(Dn) 173110037SARM gem5 Developers return new FSqrtD(machInst, rd, rn); 173210037SARM gem5 Developers break; 173310037SARM gem5 Developers case 0x4: 173410037SARM gem5 Developers if (type == 1) 173510037SARM gem5 Developers // FCVT Sd = convertFormat(Dn) 173610037SARM gem5 Developers return new FcvtFpDFpS(machInst, rd, rn); 173710037SARM gem5 Developers else if (type == 3) 173810037SARM gem5 Developers // FCVT Sd = convertFormat(Hn) 173910037SARM gem5 Developers return new FcvtFpHFpS(machInst, rd, rn); 174010037SARM gem5 Developers break; 174110037SARM gem5 Developers case 0x5: 174210037SARM gem5 Developers if (type == 0) 174310037SARM gem5 Developers // FCVT Dd = convertFormat(Sn) 174410037SARM gem5 Developers return new FCvtFpSFpD(machInst, rd, rn); 174510037SARM gem5 Developers else if (type == 3) 174610037SARM gem5 Developers // FCVT Dd = convertFormat(Hn) 174710037SARM gem5 Developers return new FcvtFpHFpD(machInst, rd, rn); 174810037SARM gem5 Developers break; 174910037SARM gem5 Developers case 0x7: 175010037SARM gem5 Developers if (type == 0) 175110037SARM gem5 Developers // FCVT Hd = convertFormat(Sn) 175210037SARM gem5 Developers return new FcvtFpSFpH(machInst, rd, rn); 175310037SARM gem5 Developers else if (type == 1) 175410037SARM gem5 Developers // FCVT Hd = convertFormat(Dn) 175510037SARM gem5 Developers return new FcvtFpDFpH(machInst, rd, rn); 175610037SARM gem5 Developers break; 175710037SARM gem5 Developers case 0x8: 175810037SARM gem5 Developers if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 175910037SARM gem5 Developers return new FRIntNS(machInst, rd, rn); 176010037SARM gem5 Developers else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 176110037SARM gem5 Developers return new FRIntND(machInst, rd, rn); 176210037SARM gem5 Developers break; 176310037SARM gem5 Developers case 0x9: 176410037SARM gem5 Developers if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 176510037SARM gem5 Developers return new FRIntPS(machInst, rd, rn); 176610037SARM gem5 Developers else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 176710037SARM gem5 Developers return new FRIntPD(machInst, rd, rn); 176810037SARM gem5 Developers break; 176910037SARM gem5 Developers case 0xa: 177010037SARM gem5 Developers if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 177110037SARM gem5 Developers return new FRIntMS(machInst, rd, rn); 177210037SARM gem5 Developers else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 177310037SARM gem5 Developers return new FRIntMD(machInst, rd, rn); 177410037SARM gem5 Developers break; 177510037SARM gem5 Developers case 0xb: 177610037SARM gem5 Developers if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 177710037SARM gem5 Developers return new FRIntZS(machInst, rd, rn); 177810037SARM gem5 Developers else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 177910037SARM gem5 Developers return new FRIntZD(machInst, rd, rn); 178010037SARM gem5 Developers break; 178110037SARM gem5 Developers case 0xc: 178210037SARM gem5 Developers if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 178310037SARM gem5 Developers return new FRIntAS(machInst, rd, rn); 178410037SARM gem5 Developers else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 178510037SARM gem5 Developers return new FRIntAD(machInst, rd, rn); 178610037SARM gem5 Developers break; 178710037SARM gem5 Developers case 0xe: 178810037SARM gem5 Developers if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 178910037SARM gem5 Developers return new FRIntXS(machInst, rd, rn); 179010037SARM gem5 Developers else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 179110037SARM gem5 Developers return new FRIntXD(machInst, rd, rn); 179210037SARM gem5 Developers break; 179310037SARM gem5 Developers case 0xf: 179410037SARM gem5 Developers if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 179510037SARM gem5 Developers return new FRIntIS(machInst, rd, rn); 179610037SARM gem5 Developers else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 179710037SARM gem5 Developers return new FRIntID(machInst, rd, rn); 179810037SARM gem5 Developers break; 179910037SARM gem5 Developers default: 180010037SARM gem5 Developers return new Unknown64(machInst); 180110037SARM gem5 Developers } 180210037SARM gem5 Developers return new Unknown64(machInst); 180310037SARM gem5 Developers } else if (bits(machInst, 15) == 1) { 180410037SARM gem5 Developers return new Unknown64(machInst); 180510037SARM gem5 Developers } else { 180610037SARM gem5 Developers if (bits(machInst, 29)) 180710037SARM gem5 Developers return new Unknown64(machInst); 180810037SARM gem5 Developers uint8_t rmode = bits(machInst, 20, 19); 180910037SARM gem5 Developers uint8_t switchVal1 = bits(machInst, 18, 16); 181010037SARM gem5 Developers uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 181110037SARM gem5 Developers // 30:24=0011110, 21=1, 15:10=000000 181210037SARM gem5 Developers switch (switchVal1) { 181310037SARM gem5 Developers case 0x0: 181410037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 181510037SARM gem5 Developers case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 181610037SARM gem5 Developers return new FcvtFpSIntWSN(machInst, rd, rn); 181710037SARM gem5 Developers case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 181810037SARM gem5 Developers return new FcvtFpSIntWSP(machInst, rd, rn); 181910037SARM gem5 Developers case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 182010037SARM gem5 Developers return new FcvtFpSIntWSM(machInst, rd, rn); 182110037SARM gem5 Developers case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 182210037SARM gem5 Developers return new FcvtFpSIntWSZ(machInst, rd, rn); 182310037SARM gem5 Developers case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 182410037SARM gem5 Developers return new FcvtFpSIntXSN(machInst, rd, rn); 182510037SARM gem5 Developers case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 182610037SARM gem5 Developers return new FcvtFpSIntXSP(machInst, rd, rn); 182710037SARM gem5 Developers case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 182810037SARM gem5 Developers return new FcvtFpSIntXSM(machInst, rd, rn); 182910037SARM gem5 Developers case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 183010037SARM gem5 Developers return new FcvtFpSIntXSZ(machInst, rd, rn); 183110037SARM gem5 Developers case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 183210037SARM gem5 Developers return new FcvtFpSIntWDN(machInst, rd, rn); 183310037SARM gem5 Developers case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 183410037SARM gem5 Developers return new FcvtFpSIntWDP(machInst, rd, rn); 183510037SARM gem5 Developers case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 183610037SARM gem5 Developers return new FcvtFpSIntWDM(machInst, rd, rn); 183710037SARM gem5 Developers case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 183810037SARM gem5 Developers return new FcvtFpSIntWDZ(machInst, rd, rn); 183910037SARM gem5 Developers case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 184010037SARM gem5 Developers return new FcvtFpSIntXDN(machInst, rd, rn); 184110037SARM gem5 Developers case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 184210037SARM gem5 Developers return new FcvtFpSIntXDP(machInst, rd, rn); 184310037SARM gem5 Developers case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 184410037SARM gem5 Developers return new FcvtFpSIntXDM(machInst, rd, rn); 184510037SARM gem5 Developers case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 184610037SARM gem5 Developers return new FcvtFpSIntXDZ(machInst, rd, rn); 184710037SARM gem5 Developers default: 184810037SARM gem5 Developers return new Unknown64(machInst); 184910037SARM gem5 Developers } 185010037SARM gem5 Developers case 0x1: 185110037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 185210037SARM gem5 Developers case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 185310037SARM gem5 Developers return new FcvtFpUIntWSN(machInst, rd, rn); 185410037SARM gem5 Developers case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 185510037SARM gem5 Developers return new FcvtFpUIntWSP(machInst, rd, rn); 185610037SARM gem5 Developers case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 185710037SARM gem5 Developers return new FcvtFpUIntWSM(machInst, rd, rn); 185810037SARM gem5 Developers case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 185910037SARM gem5 Developers return new FcvtFpUIntWSZ(machInst, rd, rn); 186010037SARM gem5 Developers case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 186110037SARM gem5 Developers return new FcvtFpUIntXSN(machInst, rd, rn); 186210037SARM gem5 Developers case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 186310037SARM gem5 Developers return new FcvtFpUIntXSP(machInst, rd, rn); 186410037SARM gem5 Developers case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 186510037SARM gem5 Developers return new FcvtFpUIntXSM(machInst, rd, rn); 186610037SARM gem5 Developers case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 186710037SARM gem5 Developers return new FcvtFpUIntXSZ(machInst, rd, rn); 186810037SARM gem5 Developers case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 186910037SARM gem5 Developers return new FcvtFpUIntWDN(machInst, rd, rn); 187010037SARM gem5 Developers case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 187110037SARM gem5 Developers return new FcvtFpUIntWDP(machInst, rd, rn); 187210037SARM gem5 Developers case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 187310037SARM gem5 Developers return new FcvtFpUIntWDM(machInst, rd, rn); 187410037SARM gem5 Developers case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 187510037SARM gem5 Developers return new FcvtFpUIntWDZ(machInst, rd, rn); 187610037SARM gem5 Developers case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 187710037SARM gem5 Developers return new FcvtFpUIntXDN(machInst, rd, rn); 187810037SARM gem5 Developers case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 187910037SARM gem5 Developers return new FcvtFpUIntXDP(machInst, rd, rn); 188010037SARM gem5 Developers case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 188110037SARM gem5 Developers return new FcvtFpUIntXDM(machInst, rd, rn); 188210037SARM gem5 Developers case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 188310037SARM gem5 Developers return new FcvtFpUIntXDZ(machInst, rd, rn); 188410037SARM gem5 Developers default: 188510037SARM gem5 Developers return new Unknown64(machInst); 188610037SARM gem5 Developers } 188710037SARM gem5 Developers case 0x2: 188810037SARM gem5 Developers if (rmode != 0) 188910037SARM gem5 Developers return new Unknown64(machInst); 189010037SARM gem5 Developers switch (switchVal2) { 189110037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn) 189210037SARM gem5 Developers return new FcvtWSIntFpS(machInst, rd, rn); 189310037SARM gem5 Developers case 1: // SCVTF Sd = convertFromInt(Xn) 189410037SARM gem5 Developers return new FcvtXSIntFpS(machInst, rd, rn); 189510037SARM gem5 Developers case 2: // SCVTF Dd = convertFromInt(Wn) 189610037SARM gem5 Developers return new FcvtWSIntFpD(machInst, rd, rn); 189710037SARM gem5 Developers case 3: // SCVTF Dd = convertFromInt(Xn) 189810037SARM gem5 Developers return new FcvtXSIntFpD(machInst, rd, rn); 189910037SARM gem5 Developers default: 190010037SARM gem5 Developers return new Unknown64(machInst); 190110037SARM gem5 Developers } 190210037SARM gem5 Developers case 0x3: 190310037SARM gem5 Developers switch (switchVal2) { 190410037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn) 190510037SARM gem5 Developers return new FcvtWUIntFpS(machInst, rd, rn); 190610037SARM gem5 Developers case 1: // UCVTF Sd = convertFromInt(Xn) 190710037SARM gem5 Developers return new FcvtXUIntFpS(machInst, rd, rn); 190810037SARM gem5 Developers case 2: // UCVTF Dd = convertFromInt(Wn) 190910037SARM gem5 Developers return new FcvtWUIntFpD(machInst, rd, rn); 191010037SARM gem5 Developers case 3: // UCVTF Dd = convertFromInt(Xn) 191110037SARM gem5 Developers return new FcvtXUIntFpD(machInst, rd, rn); 191210037SARM gem5 Developers default: 191310037SARM gem5 Developers return new Unknown64(machInst); 191410037SARM gem5 Developers } 191510037SARM gem5 Developers case 0x4: 191610037SARM gem5 Developers if (rmode != 0) 191710037SARM gem5 Developers return new Unknown64(machInst); 191810037SARM gem5 Developers switch (switchVal2) { 191910037SARM gem5 Developers case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 192010037SARM gem5 Developers return new FcvtFpSIntWSA(machInst, rd, rn); 192110037SARM gem5 Developers case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 192210037SARM gem5 Developers return new FcvtFpSIntXSA(machInst, rd, rn); 192310037SARM gem5 Developers case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 192410037SARM gem5 Developers return new FcvtFpSIntWDA(machInst, rd, rn); 192510037SARM gem5 Developers case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 192610037SARM gem5 Developers return new FcvtFpSIntXDA(machInst, rd, rn); 192710037SARM gem5 Developers default: 192810037SARM gem5 Developers return new Unknown64(machInst); 192910037SARM gem5 Developers } 193010037SARM gem5 Developers case 0x5: 193110037SARM gem5 Developers switch (switchVal2) { 193210037SARM gem5 Developers case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 193310037SARM gem5 Developers return new FcvtFpUIntWSA(machInst, rd, rn); 193410037SARM gem5 Developers case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 193510037SARM gem5 Developers return new FcvtFpUIntXSA(machInst, rd, rn); 193610037SARM gem5 Developers case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 193710037SARM gem5 Developers return new FcvtFpUIntWDA(machInst, rd, rn); 193810037SARM gem5 Developers case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 193910037SARM gem5 Developers return new FcvtFpUIntXDA(machInst, rd, rn); 194010037SARM gem5 Developers default: 194110037SARM gem5 Developers return new Unknown64(machInst); 194210037SARM gem5 Developers } 194310037SARM gem5 Developers case 0x06: 194410037SARM gem5 Developers switch (switchVal2) { 194510037SARM gem5 Developers case 0: // FMOV Wd = Sn 194610037SARM gem5 Developers if (rmode != 0) 194710037SARM gem5 Developers return new Unknown64(machInst); 194810037SARM gem5 Developers return new FmovRegCoreW(machInst, rd, rn); 194910037SARM gem5 Developers case 3: // FMOV Xd = Dn 195010037SARM gem5 Developers if (rmode != 0) 195110037SARM gem5 Developers return new Unknown64(machInst); 195210037SARM gem5 Developers return new FmovRegCoreX(machInst, rd, rn); 195310037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 195410037SARM gem5 Developers if (rmode != 1) 195510037SARM gem5 Developers return new Unknown64(machInst); 195610037SARM gem5 Developers return new FmovURegCoreX(machInst, rd, rn); 195710037SARM gem5 Developers default: 195810037SARM gem5 Developers return new Unknown64(machInst); 195910037SARM gem5 Developers } 196010037SARM gem5 Developers break; 196110037SARM gem5 Developers case 0x07: 196210037SARM gem5 Developers switch (switchVal2) { 196310037SARM gem5 Developers case 0: // FMOV Sd = Wn 196410037SARM gem5 Developers if (rmode != 0) 196510037SARM gem5 Developers return new Unknown64(machInst); 196610037SARM gem5 Developers return new FmovCoreRegW(machInst, rd, rn); 196710037SARM gem5 Developers case 3: // FMOV Xd = Dn 196810037SARM gem5 Developers if (rmode != 0) 196910037SARM gem5 Developers return new Unknown64(machInst); 197010037SARM gem5 Developers return new FmovCoreRegX(machInst, rd, rn); 197110037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 197210037SARM gem5 Developers if (rmode != 1) 197310037SARM gem5 Developers return new Unknown64(machInst); 197410037SARM gem5 Developers return new FmovUCoreRegX(machInst, rd, rn); 197510037SARM gem5 Developers default: 197610037SARM gem5 Developers return new Unknown64(machInst); 197710037SARM gem5 Developers } 197810037SARM gem5 Developers break; 197910037SARM gem5 Developers default: // Warning! missing cases in switch statement above, that still need to be added 198010037SARM gem5 Developers return new Unknown64(machInst); 198110037SARM gem5 Developers } 198210037SARM gem5 Developers } 198312597Schunchenhsu@google.com M5_UNREACHABLE; 198410037SARM gem5 Developers case 0x1: 198510037SARM gem5 Developers { 198610037SARM gem5 Developers if (bits(machInst, 31) || 198710037SARM gem5 Developers bits(machInst, 29) || 198810037SARM gem5 Developers bits(machInst, 23)) { 198910037SARM gem5 Developers return new Unknown64(machInst); 199010037SARM gem5 Developers } 199110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 199210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 199310037SARM gem5 Developers uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 199410037SARM gem5 Developers ConditionCode cond = 199510037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 199610037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4) << 0) | 199710037SARM gem5 Developers (bits(machInst, 22) << 1); 199810037SARM gem5 Developers // 31:23=000111100, 21=1, 11:10=01 199910037SARM gem5 Developers switch (switchVal) { 200010037SARM gem5 Developers case 0x0: 200110037SARM gem5 Developers // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 200210037SARM gem5 Developers return new FCCmpRegS(machInst, rn, rm, cond, imm); 200310037SARM gem5 Developers case 0x1: 200410037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Sn,Sm) 200510037SARM gem5 Developers // else #nzcv 200610037SARM gem5 Developers return new FCCmpERegS(machInst, rn, rm, cond, imm); 200710037SARM gem5 Developers case 0x2: 200810037SARM gem5 Developers // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 200910037SARM gem5 Developers return new FCCmpRegD(machInst, rn, rm, cond, imm); 201010037SARM gem5 Developers case 0x3: 201110037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Dn,Dm) 201210037SARM gem5 Developers // else #nzcv 201310037SARM gem5 Developers return new FCCmpERegD(machInst, rn, rm, cond, imm); 201410037SARM gem5 Developers default: 201510037SARM gem5 Developers return new Unknown64(machInst); 201610037SARM gem5 Developers } 201710037SARM gem5 Developers } 201810037SARM gem5 Developers case 0x2: 201910037SARM gem5 Developers { 202010037SARM gem5 Developers if (bits(machInst, 31) || 202110037SARM gem5 Developers bits(machInst, 29) || 202210037SARM gem5 Developers bits(machInst, 23)) { 202310037SARM gem5 Developers return new Unknown64(machInst); 202410037SARM gem5 Developers } 202510037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 202610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 202710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 202810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 202910037SARM gem5 Developers (bits(machInst, 22) << 4); 203010037SARM gem5 Developers switch (switchVal) { 203110037SARM gem5 Developers case 0x00: // FMUL Sd = Sn * Sm 203210037SARM gem5 Developers return new FMulS(machInst, rd, rn, rm); 203310037SARM gem5 Developers case 0x10: // FMUL Dd = Dn * Dm 203410037SARM gem5 Developers return new FMulD(machInst, rd, rn, rm); 203510037SARM gem5 Developers case 0x01: // FDIV Sd = Sn / Sm 203610037SARM gem5 Developers return new FDivS(machInst, rd, rn, rm); 203710037SARM gem5 Developers case 0x11: // FDIV Dd = Dn / Dm 203810037SARM gem5 Developers return new FDivD(machInst, rd, rn, rm); 203910037SARM gem5 Developers case 0x02: // FADD Sd = Sn + Sm 204010037SARM gem5 Developers return new FAddS(machInst, rd, rn, rm); 204110037SARM gem5 Developers case 0x12: // FADD Dd = Dn + Dm 204210037SARM gem5 Developers return new FAddD(machInst, rd, rn, rm); 204310037SARM gem5 Developers case 0x03: // FSUB Sd = Sn - Sm 204410037SARM gem5 Developers return new FSubS(machInst, rd, rn, rm); 204510037SARM gem5 Developers case 0x13: // FSUB Dd = Dn - Dm 204610037SARM gem5 Developers return new FSubD(machInst, rd, rn, rm); 204710037SARM gem5 Developers case 0x04: // FMAX Sd = max(Sn, Sm) 204810037SARM gem5 Developers return new FMaxS(machInst, rd, rn, rm); 204910037SARM gem5 Developers case 0x14: // FMAX Dd = max(Dn, Dm) 205010037SARM gem5 Developers return new FMaxD(machInst, rd, rn, rm); 205110037SARM gem5 Developers case 0x05: // FMIN Sd = min(Sn, Sm) 205210037SARM gem5 Developers return new FMinS(machInst, rd, rn, rm); 205310037SARM gem5 Developers case 0x15: // FMIN Dd = min(Dn, Dm) 205410037SARM gem5 Developers return new FMinD(machInst, rd, rn, rm); 205510037SARM gem5 Developers case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 205610037SARM gem5 Developers return new FMaxNMS(machInst, rd, rn, rm); 205710037SARM gem5 Developers case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 205810037SARM gem5 Developers return new FMaxNMD(machInst, rd, rn, rm); 205910037SARM gem5 Developers case 0x07: // FMINNM Sd = minNum(Sn, Sm) 206010037SARM gem5 Developers return new FMinNMS(machInst, rd, rn, rm); 206110037SARM gem5 Developers case 0x17: // FMINNM Dd = minNum(Dn, Dm) 206210037SARM gem5 Developers return new FMinNMD(machInst, rd, rn, rm); 206310037SARM gem5 Developers case 0x08: // FNMUL Sd = -(Sn * Sm) 206410037SARM gem5 Developers return new FNMulS(machInst, rd, rn, rm); 206510037SARM gem5 Developers case 0x18: // FNMUL Dd = -(Dn * Dm) 206610037SARM gem5 Developers return new FNMulD(machInst, rd, rn, rm); 206710037SARM gem5 Developers default: 206810037SARM gem5 Developers return new Unknown64(machInst); 206910037SARM gem5 Developers } 207010037SARM gem5 Developers } 207110037SARM gem5 Developers case 0x3: 207210037SARM gem5 Developers { 207310037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 207410037SARM gem5 Developers return new Unknown64(machInst); 207510037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 207610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 207710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 207810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 207910037SARM gem5 Developers ConditionCode cond = 208010037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 208110037SARM gem5 Developers if (type == 0) // FCSEL Sd = if cond then Sn else Sm 208210037SARM gem5 Developers return new FCSelS(machInst, rd, rn, rm, cond); 208310037SARM gem5 Developers else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 208410037SARM gem5 Developers return new FCSelD(machInst, rd, rn, rm, cond); 208510037SARM gem5 Developers else 208610037SARM gem5 Developers return new Unknown64(machInst); 208710037SARM gem5 Developers } 208812595Ssiddhesh.poyarekar@gmail.com default: 208912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 209010037SARM gem5 Developers } 209110037SARM gem5 Developers } 209212597Schunchenhsu@google.com M5_UNREACHABLE; 209310037SARM gem5 Developers } 209410037SARM gem5 Developers} 209510037SARM gem5 Developers}}; 209610037SARM gem5 Developers 209710037SARM gem5 Developersoutput decoder {{ 209810037SARM gem5 Developersnamespace Aarch64 209910037SARM gem5 Developers{ 210010037SARM gem5 Developers StaticInstPtr 210110037SARM gem5 Developers decodeAdvSIMDScalar(ExtMachInst machInst) 210210037SARM gem5 Developers { 210310037SARM gem5 Developers if (bits(machInst, 24) == 1) { 210410037SARM gem5 Developers if (bits(machInst, 10) == 0) { 210510037SARM gem5 Developers return decodeNeonScIndexedElem(machInst); 210610037SARM gem5 Developers } else if (bits(machInst, 23) == 0) { 210710037SARM gem5 Developers return decodeNeonScShiftByImm(machInst); 210810037SARM gem5 Developers } 210910037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 211010037SARM gem5 Developers if (bits(machInst, 10) == 1) { 211110037SARM gem5 Developers return decodeNeonSc3Same(machInst); 211210037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 211310037SARM gem5 Developers return decodeNeonSc3Diff(machInst); 211410037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 211510037SARM gem5 Developers return decodeNeonSc2RegMisc(machInst); 211613170Sgiacomo.travaglini@arm.com } else if (bits(machInst, 20, 17) == 0x4) { 211713170Sgiacomo.travaglini@arm.com return decodeCryptoTwoRegSHA(machInst); 211810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 211910037SARM gem5 Developers return decodeNeonScPwise(machInst); 212010037SARM gem5 Developers } else { 212110037SARM gem5 Developers return new Unknown64(machInst); 212210037SARM gem5 Developers } 212310037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0 && 212413170Sgiacomo.travaglini@arm.com bits(machInst, 15) == 0) { 212513170Sgiacomo.travaglini@arm.com if (bits(machInst, 10) == 1) { 212613170Sgiacomo.travaglini@arm.com return decodeNeonScCopy(machInst); 212713170Sgiacomo.travaglini@arm.com } else { 212813170Sgiacomo.travaglini@arm.com return decodeCryptoThreeRegSHA(machInst); 212913170Sgiacomo.travaglini@arm.com } 213010037SARM gem5 Developers } else { 213110037SARM gem5 Developers return new Unknown64(machInst); 213210037SARM gem5 Developers } 213310037SARM gem5 Developers return new FailUnimplemented("Unhandled Case6", machInst); 213410037SARM gem5 Developers } 213510037SARM gem5 Developers} 213610037SARM gem5 Developers}}; 213710037SARM gem5 Developers 213810037SARM gem5 Developersoutput decoder {{ 213910037SARM gem5 Developersnamespace Aarch64 214010037SARM gem5 Developers{ 214111165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 214210037SARM gem5 Developers StaticInstPtr 214310037SARM gem5 Developers decodeFpAdvSIMD(ExtMachInst machInst) 214410037SARM gem5 Developers { 214510037SARM gem5 Developers 214610037SARM gem5 Developers if (bits(machInst, 28) == 0) { 214710037SARM gem5 Developers if (bits(machInst, 31) == 0) { 214811165SRekai.GonzalezAlberquilla@arm.com return decodeAdvSIMD<DecoderFeatures>(machInst); 214910037SARM gem5 Developers } else { 215010037SARM gem5 Developers return new Unknown64(machInst); 215110037SARM gem5 Developers } 215210037SARM gem5 Developers } else if (bits(machInst, 30) == 0) { 215310037SARM gem5 Developers return decodeFp(machInst); 215410037SARM gem5 Developers } else if (bits(machInst, 31) == 0) { 215510037SARM gem5 Developers return decodeAdvSIMDScalar(machInst); 215610037SARM gem5 Developers } else { 215710037SARM gem5 Developers return new Unknown64(machInst); 215810037SARM gem5 Developers } 215910037SARM gem5 Developers } 216010037SARM gem5 Developers} 216110037SARM gem5 Developers}}; 216210037SARM gem5 Developers 216311165SRekai.GonzalezAlberquilla@arm.comlet {{ 216411165SRekai.GonzalezAlberquilla@arm.com decoder_output =''' 216511165SRekai.GonzalezAlberquilla@arm.comnamespace Aarch64 216611165SRekai.GonzalezAlberquilla@arm.com{''' 216711165SRekai.GonzalezAlberquilla@arm.com for decoderFlavour, type_dict in decoders.iteritems(): 216811165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 216911165SRekai.GonzalezAlberquilla@arm.comtemplate StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); 217011165SRekai.GonzalezAlberquilla@arm.com''' % { "df" : decoderFlavour } 217111165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 217211165SRekai.GonzalezAlberquilla@arm.com}''' 217311165SRekai.GonzalezAlberquilla@arm.com}}; 217411165SRekai.GonzalezAlberquilla@arm.com 217510037SARM gem5 Developersoutput decoder {{ 217610037SARM gem5 Developersnamespace Aarch64 217710037SARM gem5 Developers{ 217810037SARM gem5 Developers StaticInstPtr 217910037SARM gem5 Developers decodeGem5Ops(ExtMachInst machInst) 218010037SARM gem5 Developers { 218110037SARM gem5 Developers const uint32_t m5func = bits(machInst, 23, 16); 218210037SARM gem5 Developers switch (m5func) { 218312159Sandreas.sandberg@arm.com case M5OP_ARM: return new Arm(machInst); 218412159Sandreas.sandberg@arm.com case M5OP_QUIESCE: return new Quiesce(machInst); 218512159Sandreas.sandberg@arm.com case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst); 218612159Sandreas.sandberg@arm.com case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst); 218712159Sandreas.sandberg@arm.com case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst); 218812159Sandreas.sandberg@arm.com case M5OP_RPNS: return new Rpns64(machInst); 218912159Sandreas.sandberg@arm.com case M5OP_WAKE_CPU: return new WakeCPU64(machInst); 219012159Sandreas.sandberg@arm.com case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); 219112159Sandreas.sandberg@arm.com case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); 219212159Sandreas.sandberg@arm.com case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); 219312159Sandreas.sandberg@arm.com case M5OP_EXIT: return new M5exit64(machInst); 219412159Sandreas.sandberg@arm.com case M5OP_FAIL: return new M5fail64(machInst); 219512159Sandreas.sandberg@arm.com case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); 219612159Sandreas.sandberg@arm.com case M5OP_INIT_PARAM: return new Initparam64(machInst); 219712159Sandreas.sandberg@arm.com case M5OP_RESET_STATS: return new Resetstats64(machInst); 219812159Sandreas.sandberg@arm.com case M5OP_DUMP_STATS: return new Dumpstats64(machInst); 219912159Sandreas.sandberg@arm.com case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst); 220012159Sandreas.sandberg@arm.com case M5OP_CHECKPOINT: return new M5checkpoint64(machInst); 220112159Sandreas.sandberg@arm.com case M5OP_WRITE_FILE: return new M5writefile64(machInst); 220212159Sandreas.sandberg@arm.com case M5OP_READ_FILE: return new M5readfile64(machInst); 220312159Sandreas.sandberg@arm.com case M5OP_DEBUG_BREAK: return new M5break(machInst); 220412159Sandreas.sandberg@arm.com case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); 220512159Sandreas.sandberg@arm.com case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst); 220612159Sandreas.sandberg@arm.com case M5OP_PANIC: return new M5panic(machInst); 220712159Sandreas.sandberg@arm.com case M5OP_WORK_BEGIN: return new M5workbegin64(machInst); 220812159Sandreas.sandberg@arm.com case M5OP_WORK_END: return new M5workend64(machInst); 220910037SARM gem5 Developers default: return new Unknown64(machInst); 221010037SARM gem5 Developers } 221110037SARM gem5 Developers } 221210037SARM gem5 Developers} 221310037SARM gem5 Developers}}; 221410037SARM gem5 Developers 221510037SARM gem5 Developersdef format Aarch64() {{ 221610037SARM gem5 Developers decode_block = ''' 221710037SARM gem5 Developers { 221810037SARM gem5 Developers using namespace Aarch64; 221910037SARM gem5 Developers if (bits(machInst, 27) == 0x0) { 222010037SARM gem5 Developers if (bits(machInst, 28) == 0x0) 222110037SARM gem5 Developers return new Unknown64(machInst); 222210037SARM gem5 Developers else if (bits(machInst, 26) == 0) 222310037SARM gem5 Developers // bit 28:26=100 222410037SARM gem5 Developers return decodeDataProcImm(machInst); 222510037SARM gem5 Developers else 222610037SARM gem5 Developers // bit 28:26=101 222710037SARM gem5 Developers return decodeBranchExcSys(machInst); 222810037SARM gem5 Developers } else if (bits(machInst, 25) == 0) { 222910037SARM gem5 Developers // bit 27=1, 25=0 223010037SARM gem5 Developers return decodeLoadsStores(machInst); 223110037SARM gem5 Developers } else if (bits(machInst, 26) == 0) { 223210037SARM gem5 Developers // bit 27:25=101 223310037SARM gem5 Developers return decodeDataProcReg(machInst); 223410037SARM gem5 Developers } else if (bits(machInst, 24) == 1 && 223510037SARM gem5 Developers bits(machInst, 31, 28) == 0xF) { 223610037SARM gem5 Developers return decodeGem5Ops(machInst); 223710037SARM gem5 Developers } else { 223810037SARM gem5 Developers // bit 27:25=111 223911165SRekai.GonzalezAlberquilla@arm.com switch(decoderFlavour){ 224011165SRekai.GonzalezAlberquilla@arm.com default: 224111165SRekai.GonzalezAlberquilla@arm.com return decodeFpAdvSIMD<GenericDecoder>(machInst); 224211165SRekai.GonzalezAlberquilla@arm.com } 224310037SARM gem5 Developers } 224410037SARM gem5 Developers } 224510037SARM gem5 Developers ''' 224610037SARM gem5 Developers}}; 2247