aarch64.isa revision 12673
112531Sandreas.sandberg@arm.com// Copyright (c) 2011-2018 ARM Limited 210037SARM gem5 Developers// All rights reserved 310037SARM gem5 Developers// 410037SARM gem5 Developers// The license below extends only to copyright in the software and shall 510037SARM gem5 Developers// not be construed as granting a license to any other intellectual 610037SARM gem5 Developers// property including but not limited to intellectual property relating 710037SARM gem5 Developers// to a hardware implementation of the functionality of the software 810037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers// 1310037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1410037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1510037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1610037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1710037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1910037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2010037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2110037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2210037SARM gem5 Developers// this software without specific prior written permission. 2310037SARM gem5 Developers// 2410037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510037SARM gem5 Developers// 3610037SARM gem5 Developers// Authors: Gabe Black 3710037SARM gem5 Developers// Thomas Grocutt 3810037SARM gem5 Developers// Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developersoutput header {{ 4210037SARM gem5 Developersnamespace Aarch64 4310037SARM gem5 Developers{ 4410037SARM gem5 Developers StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 4510037SARM gem5 Developers StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 4610037SARM gem5 Developers StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 4710037SARM gem5 Developers StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 4810037SARM gem5 Developers 4911165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5010037SARM gem5 Developers StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 5110037SARM gem5 Developers StaticInstPtr decodeFp(ExtMachInst machInst); 5211165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5310037SARM gem5 Developers StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 5410037SARM gem5 Developers StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 5510037SARM gem5 Developers 5610037SARM gem5 Developers StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 5710037SARM gem5 Developers} 5810037SARM gem5 Developers}}; 5910037SARM gem5 Developers 6010037SARM gem5 Developersoutput decoder {{ 6110037SARM gem5 Developersnamespace Aarch64 6210037SARM gem5 Developers{ 6310037SARM gem5 Developers StaticInstPtr 6410037SARM gem5 Developers decodeDataProcImm(ExtMachInst machInst) 6510037SARM gem5 Developers { 6610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 6710037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 6810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 6910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 7010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 7110037SARM gem5 Developers 7210037SARM gem5 Developers uint8_t opc = bits(machInst, 30, 29); 7310037SARM gem5 Developers bool sf = bits(machInst, 31); 7410037SARM gem5 Developers bool n = bits(machInst, 22); 7510037SARM gem5 Developers uint8_t immr = bits(machInst, 21, 16); 7610037SARM gem5 Developers uint8_t imms = bits(machInst, 15, 10); 7710037SARM gem5 Developers switch (bits(machInst, 25, 23)) { 7810037SARM gem5 Developers case 0x0: 7910037SARM gem5 Developers case 0x1: 8010037SARM gem5 Developers { 8110037SARM gem5 Developers uint64_t immlo = bits(machInst, 30, 29); 8210037SARM gem5 Developers uint64_t immhi = bits(machInst, 23, 5); 8310037SARM gem5 Developers uint64_t imm = (immlo << 0) | (immhi << 2); 8410037SARM gem5 Developers if (bits(machInst, 31) == 0) 8510337SAndrew.Bardsley@arm.com return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 8610037SARM gem5 Developers else 8710337SAndrew.Bardsley@arm.com return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 8810037SARM gem5 Developers sext<33>(imm << 12)); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers case 0x2: 9110037SARM gem5 Developers case 0x3: 9210037SARM gem5 Developers { 9310037SARM gem5 Developers uint32_t imm12 = bits(machInst, 21, 10); 9410037SARM gem5 Developers uint8_t shift = bits(machInst, 23, 22); 9510037SARM gem5 Developers uint32_t imm; 9610037SARM gem5 Developers if (shift == 0x0) 9710037SARM gem5 Developers imm = imm12 << 0; 9810037SARM gem5 Developers else if (shift == 0x1) 9910037SARM gem5 Developers imm = imm12 << 12; 10010037SARM gem5 Developers else 10110037SARM gem5 Developers return new Unknown64(machInst); 10210037SARM gem5 Developers switch (opc) { 10310037SARM gem5 Developers case 0x0: 10410037SARM gem5 Developers return new AddXImm(machInst, rdsp, rnsp, imm); 10510037SARM gem5 Developers case 0x1: 10610337SAndrew.Bardsley@arm.com return new AddXImmCc(machInst, rdzr, rnsp, imm); 10710037SARM gem5 Developers case 0x2: 10810037SARM gem5 Developers return new SubXImm(machInst, rdsp, rnsp, imm); 10910037SARM gem5 Developers case 0x3: 11010337SAndrew.Bardsley@arm.com return new SubXImmCc(machInst, rdzr, rnsp, imm); 11112595Ssiddhesh.poyarekar@gmail.com default: 11212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 11310037SARM gem5 Developers } 11410037SARM gem5 Developers } 11510037SARM gem5 Developers case 0x4: 11610037SARM gem5 Developers { 11710037SARM gem5 Developers if (!sf && n) 11810037SARM gem5 Developers return new Unknown64(machInst); 11910037SARM gem5 Developers // len = MSB(n:NOT(imms)), len < 1 is undefined. 12010037SARM gem5 Developers uint8_t len = 0; 12110037SARM gem5 Developers if (n) { 12210037SARM gem5 Developers len = 6; 12310037SARM gem5 Developers } else if (imms == 0x3f || imms == 0x3e) { 12410037SARM gem5 Developers return new Unknown64(machInst); 12510037SARM gem5 Developers } else { 12610037SARM gem5 Developers len = findMsbSet(imms ^ 0x3f); 12710037SARM gem5 Developers } 12810037SARM gem5 Developers // Generate r, s, and size. 12910037SARM gem5 Developers uint64_t r = bits(immr, len - 1, 0); 13010037SARM gem5 Developers uint64_t s = bits(imms, len - 1, 0); 13110037SARM gem5 Developers uint8_t size = 1 << len; 13210037SARM gem5 Developers if (s == size - 1) 13310037SARM gem5 Developers return new Unknown64(machInst); 13410037SARM gem5 Developers // Generate the pattern with s 1s, rotated by r, with size bits. 13510037SARM gem5 Developers uint64_t pattern = mask(s + 1); 13610037SARM gem5 Developers if (r) { 13710037SARM gem5 Developers pattern = (pattern >> r) | (pattern << (size - r)); 13810037SARM gem5 Developers pattern &= mask(size); 13910037SARM gem5 Developers } 14010037SARM gem5 Developers uint8_t width = sf ? 64 : 32; 14110037SARM gem5 Developers // Replicate that to fill up the immediate. 14210037SARM gem5 Developers for (unsigned i = 1; i < (width / size); i *= 2) 14310037SARM gem5 Developers pattern |= (pattern << (i * size)); 14410037SARM gem5 Developers uint64_t imm = pattern; 14510037SARM gem5 Developers 14610037SARM gem5 Developers switch (opc) { 14710037SARM gem5 Developers case 0x0: 14810037SARM gem5 Developers return new AndXImm(machInst, rdsp, rn, imm); 14910037SARM gem5 Developers case 0x1: 15010037SARM gem5 Developers return new OrrXImm(machInst, rdsp, rn, imm); 15110037SARM gem5 Developers case 0x2: 15210037SARM gem5 Developers return new EorXImm(machInst, rdsp, rn, imm); 15310037SARM gem5 Developers case 0x3: 15410337SAndrew.Bardsley@arm.com return new AndXImmCc(machInst, rdzr, rn, imm); 15512595Ssiddhesh.poyarekar@gmail.com default: 15612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 15710037SARM gem5 Developers } 15810037SARM gem5 Developers } 15910037SARM gem5 Developers case 0x5: 16010037SARM gem5 Developers { 16110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 16210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 16310037SARM gem5 Developers uint32_t imm16 = bits(machInst, 20, 5); 16410037SARM gem5 Developers uint32_t hw = bits(machInst, 22, 21); 16510037SARM gem5 Developers switch (opc) { 16610037SARM gem5 Developers case 0x0: 16710337SAndrew.Bardsley@arm.com return new Movn(machInst, rdzr, imm16, hw * 16); 16810037SARM gem5 Developers case 0x1: 16910037SARM gem5 Developers return new Unknown64(machInst); 17010037SARM gem5 Developers case 0x2: 17110337SAndrew.Bardsley@arm.com return new Movz(machInst, rdzr, imm16, hw * 16); 17210037SARM gem5 Developers case 0x3: 17310337SAndrew.Bardsley@arm.com return new Movk(machInst, rdzr, imm16, hw * 16); 17412595Ssiddhesh.poyarekar@gmail.com default: 17512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 17610037SARM gem5 Developers } 17710037SARM gem5 Developers } 17810037SARM gem5 Developers case 0x6: 17910037SARM gem5 Developers if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 18010037SARM gem5 Developers return new Unknown64(machInst); 18110037SARM gem5 Developers switch (opc) { 18210037SARM gem5 Developers case 0x0: 18310337SAndrew.Bardsley@arm.com return new Sbfm64(machInst, rdzr, rn, immr, imms); 18410037SARM gem5 Developers case 0x1: 18510337SAndrew.Bardsley@arm.com return new Bfm64(machInst, rdzr, rn, immr, imms); 18610037SARM gem5 Developers case 0x2: 18710337SAndrew.Bardsley@arm.com return new Ubfm64(machInst, rdzr, rn, immr, imms); 18810037SARM gem5 Developers case 0x3: 18910037SARM gem5 Developers return new Unknown64(machInst); 19012595Ssiddhesh.poyarekar@gmail.com default: 19112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 19210037SARM gem5 Developers } 19310037SARM gem5 Developers case 0x7: 19410037SARM gem5 Developers { 19510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 19610037SARM gem5 Developers if (opc || bits(machInst, 21)) 19710037SARM gem5 Developers return new Unknown64(machInst); 19810037SARM gem5 Developers else 19910337SAndrew.Bardsley@arm.com return new Extr64(machInst, rdzr, rn, rm, imms); 20010037SARM gem5 Developers } 20110037SARM gem5 Developers } 20210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case8", machInst); 20310037SARM gem5 Developers } 20410037SARM gem5 Developers} 20510037SARM gem5 Developers}}; 20610037SARM gem5 Developers 20710037SARM gem5 Developersoutput decoder {{ 20810037SARM gem5 Developersnamespace Aarch64 20910037SARM gem5 Developers{ 21010037SARM gem5 Developers StaticInstPtr 21110037SARM gem5 Developers decodeBranchExcSys(ExtMachInst machInst) 21210037SARM gem5 Developers { 21310037SARM gem5 Developers switch (bits(machInst, 30, 29)) { 21410037SARM gem5 Developers case 0x0: 21510037SARM gem5 Developers { 21610037SARM gem5 Developers int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 21710037SARM gem5 Developers if (bits(machInst, 31) == 0) 21810037SARM gem5 Developers return new B64(machInst, imm); 21910037SARM gem5 Developers else 22010037SARM gem5 Developers return new Bl64(machInst, imm); 22110037SARM gem5 Developers } 22210037SARM gem5 Developers case 0x1: 22310037SARM gem5 Developers { 22410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 22510037SARM gem5 Developers if (bits(machInst, 25) == 0) { 22610037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 22710037SARM gem5 Developers if (bits(machInst, 24) == 0) 22810037SARM gem5 Developers return new Cbz64(machInst, imm, rt); 22910037SARM gem5 Developers else 23010037SARM gem5 Developers return new Cbnz64(machInst, imm, rt); 23110037SARM gem5 Developers } else { 23210037SARM gem5 Developers uint64_t bitmask = 0x1; 23310037SARM gem5 Developers bitmask <<= bits(machInst, 23, 19); 23410037SARM gem5 Developers int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 23510037SARM gem5 Developers if (bits(machInst, 31)) 23610037SARM gem5 Developers bitmask <<= 32; 23710037SARM gem5 Developers if (bits(machInst, 24) == 0) 23810037SARM gem5 Developers return new Tbz64(machInst, bitmask, imm, rt); 23910037SARM gem5 Developers else 24010037SARM gem5 Developers return new Tbnz64(machInst, bitmask, imm, rt); 24110037SARM gem5 Developers } 24210037SARM gem5 Developers } 24310037SARM gem5 Developers case 0x2: 24410037SARM gem5 Developers // bit 30:26=10101 24510037SARM gem5 Developers if (bits(machInst, 31) == 0) { 24610037SARM gem5 Developers if (bits(machInst, 25, 24) || bits(machInst, 4)) 24710037SARM gem5 Developers return new Unknown64(machInst); 24810037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 24910037SARM gem5 Developers ConditionCode condCode = 25010037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 25110037SARM gem5 Developers return new BCond64(machInst, imm, condCode); 25210037SARM gem5 Developers } else if (bits(machInst, 25, 24) == 0x0) { 25312538Sgiacomo.travaglini@arm.com 25410037SARM gem5 Developers if (bits(machInst, 4, 2)) 25510037SARM gem5 Developers return new Unknown64(machInst); 25612538Sgiacomo.travaglini@arm.com 25712538Sgiacomo.travaglini@arm.com auto imm16 = bits(machInst, 20, 5); 25810037SARM gem5 Developers uint8_t decVal = (bits(machInst, 1, 0) << 0) | 25910037SARM gem5 Developers (bits(machInst, 23, 21) << 2); 26012538Sgiacomo.travaglini@arm.com 26110037SARM gem5 Developers switch (decVal) { 26210037SARM gem5 Developers case 0x01: 26312538Sgiacomo.travaglini@arm.com return new Svc64(machInst, imm16); 26410037SARM gem5 Developers case 0x02: 26512538Sgiacomo.travaglini@arm.com return new Hvc64(machInst, imm16); 26610037SARM gem5 Developers case 0x03: 26712538Sgiacomo.travaglini@arm.com return new Smc64(machInst, imm16); 26810037SARM gem5 Developers case 0x04: 26912538Sgiacomo.travaglini@arm.com return new Brk64(machInst, imm16); 27010037SARM gem5 Developers case 0x08: 27112538Sgiacomo.travaglini@arm.com return new Hlt64(machInst, imm16); 27210037SARM gem5 Developers case 0x15: 27310037SARM gem5 Developers return new FailUnimplemented("dcps1", machInst); 27410037SARM gem5 Developers case 0x16: 27510037SARM gem5 Developers return new FailUnimplemented("dcps2", machInst); 27610037SARM gem5 Developers case 0x17: 27710037SARM gem5 Developers return new FailUnimplemented("dcps3", machInst); 27810037SARM gem5 Developers default: 27910037SARM gem5 Developers return new Unknown64(machInst); 28010037SARM gem5 Developers } 28110037SARM gem5 Developers } else if (bits(machInst, 25, 22) == 0x4) { 28210037SARM gem5 Developers // bit 31:22=1101010100 28310037SARM gem5 Developers bool l = bits(machInst, 21); 28410037SARM gem5 Developers uint8_t op0 = bits(machInst, 20, 19); 28510037SARM gem5 Developers uint8_t op1 = bits(machInst, 18, 16); 28610037SARM gem5 Developers uint8_t crn = bits(machInst, 15, 12); 28710037SARM gem5 Developers uint8_t crm = bits(machInst, 11, 8); 28810037SARM gem5 Developers uint8_t op2 = bits(machInst, 7, 5); 28910037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 29010037SARM gem5 Developers switch (op0) { 29110037SARM gem5 Developers case 0x0: 29210037SARM gem5 Developers if (rt != 0x1f || l) 29310037SARM gem5 Developers return new Unknown64(machInst); 29410037SARM gem5 Developers if (crn == 0x2 && op1 == 0x3) { 29510037SARM gem5 Developers switch (op2) { 29610037SARM gem5 Developers case 0x0: 29710037SARM gem5 Developers return new NopInst(machInst); 29810037SARM gem5 Developers case 0x1: 29910037SARM gem5 Developers return new YieldInst(machInst); 30010037SARM gem5 Developers case 0x2: 30110037SARM gem5 Developers return new WfeInst(machInst); 30210037SARM gem5 Developers case 0x3: 30310037SARM gem5 Developers return new WfiInst(machInst); 30410037SARM gem5 Developers case 0x4: 30510037SARM gem5 Developers return new SevInst(machInst); 30610037SARM gem5 Developers case 0x5: 30710037SARM gem5 Developers return new SevlInst(machInst); 30810037SARM gem5 Developers default: 30910037SARM gem5 Developers return new Unknown64(machInst); 31010037SARM gem5 Developers } 31110037SARM gem5 Developers } else if (crn == 0x3 && op1 == 0x3) { 31210037SARM gem5 Developers switch (op2) { 31310037SARM gem5 Developers case 0x2: 31410037SARM gem5 Developers return new Clrex64(machInst); 31510037SARM gem5 Developers case 0x4: 31610037SARM gem5 Developers return new Dsb64(machInst); 31710037SARM gem5 Developers case 0x5: 31810037SARM gem5 Developers return new Dmb64(machInst); 31910037SARM gem5 Developers case 0x6: 32010037SARM gem5 Developers return new Isb64(machInst); 32110037SARM gem5 Developers default: 32210037SARM gem5 Developers return new Unknown64(machInst); 32310037SARM gem5 Developers } 32410037SARM gem5 Developers } else if (crn == 0x4) { 32510037SARM gem5 Developers // MSR immediate 32610037SARM gem5 Developers switch (op1 << 3 | op2) { 32710037SARM gem5 Developers case 0x5: 32810037SARM gem5 Developers // SP 32910037SARM gem5 Developers return new MsrSP64(machInst, 33010037SARM gem5 Developers (IntRegIndex) MISCREG_SPSEL, 33110037SARM gem5 Developers INTREG_ZERO, 33210037SARM gem5 Developers crm & 0x1); 33310037SARM gem5 Developers case 0x1e: 33410037SARM gem5 Developers // DAIFSet 33510037SARM gem5 Developers return new MsrDAIFSet64( 33610037SARM gem5 Developers machInst, 33710037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 33810037SARM gem5 Developers INTREG_ZERO, 33910037SARM gem5 Developers crm); 34010037SARM gem5 Developers case 0x1f: 34110037SARM gem5 Developers // DAIFClr 34210037SARM gem5 Developers return new MsrDAIFClr64( 34310037SARM gem5 Developers machInst, 34410037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 34510037SARM gem5 Developers INTREG_ZERO, 34610037SARM gem5 Developers crm); 34710037SARM gem5 Developers default: 34810037SARM gem5 Developers return new Unknown64(machInst); 34910037SARM gem5 Developers } 35010037SARM gem5 Developers } else { 35110037SARM gem5 Developers return new Unknown64(machInst); 35210037SARM gem5 Developers } 35310037SARM gem5 Developers break; 35410037SARM gem5 Developers case 0x1: 35510037SARM gem5 Developers case 0x2: 35610037SARM gem5 Developers case 0x3: 35710037SARM gem5 Developers { 35810037SARM gem5 Developers // bit 31:22=1101010100, 20:19=11 35910037SARM gem5 Developers bool read = l; 36010037SARM gem5 Developers MiscRegIndex miscReg = 36110037SARM gem5 Developers decodeAArch64SysReg(op0, op1, crn, crm, op2); 36210037SARM gem5 Developers if (read) { 36310037SARM gem5 Developers if ((miscReg == MISCREG_DC_CIVAC_Xt) || 36410037SARM gem5 Developers (miscReg == MISCREG_DC_CVAC_Xt) || 36512359Snikos.nikoleris@arm.com (miscReg == MISCREG_DC_IVAC_Xt) || 36610037SARM gem5 Developers (miscReg == MISCREG_DC_ZVA_Xt)) { 36710037SARM gem5 Developers return new Unknown64(machInst); 36810037SARM gem5 Developers } 36910037SARM gem5 Developers } 37010037SARM gem5 Developers // Check for invalid registers 37110037SARM gem5 Developers if (miscReg == MISCREG_UNKNOWN) { 37212673Sgiacomo.travaglini@arm.com auto full_mnemonic = 37312673Sgiacomo.travaglini@arm.com csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", 37412673Sgiacomo.travaglini@arm.com read ? "mrs" : "msr", 37512673Sgiacomo.travaglini@arm.com op0, op1, crn, crm, op2); 37612673Sgiacomo.travaglini@arm.com 37712673Sgiacomo.travaglini@arm.com return new FailUnimplemented(read ? "mrs" : "msr", 37812673Sgiacomo.travaglini@arm.com machInst, full_mnemonic); 37912673Sgiacomo.travaglini@arm.com 38010037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 38110037SARM gem5 Developers if (miscReg == MISCREG_NZCV) { 38210037SARM gem5 Developers if (read) 38310037SARM gem5 Developers return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 38410037SARM gem5 Developers else 38510037SARM gem5 Developers return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 38610037SARM gem5 Developers } 38710037SARM gem5 Developers uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 38810506SAli.Saidi@ARM.com if (read) { 38912280Sgiacomo.travaglini@arm.com StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); 39010506SAli.Saidi@ARM.com if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 39110506SAli.Saidi@ARM.com si->setFlag(StaticInst::IsUnverifiable); 39210506SAli.Saidi@ARM.com return si; 39312280Sgiacomo.travaglini@arm.com } else { 39412359Snikos.nikoleris@arm.com switch (miscReg) { 39512359Snikos.nikoleris@arm.com case MISCREG_DC_ZVA_Xt: 39612359Snikos.nikoleris@arm.com return new Dczva(machInst, rt, miscReg, iss); 39712359Snikos.nikoleris@arm.com case MISCREG_DC_CVAU_Xt: 39812359Snikos.nikoleris@arm.com return new Dccvau(machInst, rt, miscReg, iss); 39912359Snikos.nikoleris@arm.com case MISCREG_DC_CVAC_Xt: 40012359Snikos.nikoleris@arm.com return new Dccvac(machInst, rt, miscReg, iss); 40112359Snikos.nikoleris@arm.com case MISCREG_DC_CIVAC_Xt: 40212359Snikos.nikoleris@arm.com return new Dccivac(machInst, rt, miscReg, iss); 40312359Snikos.nikoleris@arm.com case MISCREG_DC_IVAC_Xt: 40412359Snikos.nikoleris@arm.com return new Dcivac(machInst, rt, miscReg, iss); 40512359Snikos.nikoleris@arm.com default: 40612359Snikos.nikoleris@arm.com return new Msr64(machInst, miscReg, rt, iss); 40712359Snikos.nikoleris@arm.com } 40812280Sgiacomo.travaglini@arm.com } 40910037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 41010037SARM gem5 Developers std::string full_mnem = csprintf("%s %s", 41110037SARM gem5 Developers read ? "mrs" : "msr", miscRegName[miscReg]); 41210037SARM gem5 Developers return new WarnUnimplemented(read ? "mrs" : "msr", 41310037SARM gem5 Developers machInst, full_mnem); 41410037SARM gem5 Developers } else { 41510173SMitchell.Hayenga@ARM.com return new FailUnimplemented(read ? "mrs" : "msr", 41610173SMitchell.Hayenga@ARM.com machInst, 41710173SMitchell.Hayenga@ARM.com csprintf("%s %s", 41810173SMitchell.Hayenga@ARM.com read ? "mrs" : "msr", 41910173SMitchell.Hayenga@ARM.com miscRegName[miscReg])); 42010037SARM gem5 Developers } 42110037SARM gem5 Developers } 42210037SARM gem5 Developers break; 42312595Ssiddhesh.poyarekar@gmail.com default: 42412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 42510037SARM gem5 Developers } 42610037SARM gem5 Developers } else if (bits(machInst, 25) == 0x1) { 42710037SARM gem5 Developers uint8_t opc = bits(machInst, 24, 21); 42810037SARM gem5 Developers uint8_t op2 = bits(machInst, 20, 16); 42910037SARM gem5 Developers uint8_t op3 = bits(machInst, 15, 10); 43010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 43110037SARM gem5 Developers uint8_t op4 = bits(machInst, 4, 0); 43210037SARM gem5 Developers if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 43310037SARM gem5 Developers return new Unknown64(machInst); 43410037SARM gem5 Developers switch (opc) { 43510037SARM gem5 Developers case 0x0: 43610037SARM gem5 Developers return new Br64(machInst, rn); 43710037SARM gem5 Developers case 0x1: 43810037SARM gem5 Developers return new Blr64(machInst, rn); 43910037SARM gem5 Developers case 0x2: 44010037SARM gem5 Developers return new Ret64(machInst, rn); 44110037SARM gem5 Developers case 0x4: 44210037SARM gem5 Developers if (rn != 0x1f) 44310037SARM gem5 Developers return new Unknown64(machInst); 44410037SARM gem5 Developers return new Eret64(machInst); 44510037SARM gem5 Developers case 0x5: 44610037SARM gem5 Developers if (rn != 0x1f) 44710037SARM gem5 Developers return new Unknown64(machInst); 44810037SARM gem5 Developers return new FailUnimplemented("dret", machInst); 44912595Ssiddhesh.poyarekar@gmail.com default: 45012595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 45110037SARM gem5 Developers } 45210037SARM gem5 Developers } 45312595Ssiddhesh.poyarekar@gmail.com M5_FALLTHROUGH; 45410037SARM gem5 Developers default: 45510037SARM gem5 Developers return new Unknown64(machInst); 45610037SARM gem5 Developers } 45710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case7", machInst); 45810037SARM gem5 Developers } 45910037SARM gem5 Developers} 46010037SARM gem5 Developers}}; 46110037SARM gem5 Developers 46210037SARM gem5 Developersoutput decoder {{ 46310037SARM gem5 Developersnamespace Aarch64 46410037SARM gem5 Developers{ 46510037SARM gem5 Developers StaticInstPtr 46610037SARM gem5 Developers decodeLoadsStores(ExtMachInst machInst) 46710037SARM gem5 Developers { 46810037SARM gem5 Developers // bit 27,25=10 46910037SARM gem5 Developers switch (bits(machInst, 29, 28)) { 47010037SARM gem5 Developers case 0x0: 47110037SARM gem5 Developers if (bits(machInst, 26) == 0) { 47210037SARM gem5 Developers if (bits(machInst, 24) != 0) 47310037SARM gem5 Developers return new Unknown64(machInst); 47410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 47510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 47610037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 47710037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 47810037SARM gem5 Developers IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 47910037SARM gem5 Developers uint8_t opc = (bits(machInst, 15) << 0) | 48010037SARM gem5 Developers (bits(machInst, 23, 21) << 1); 48110037SARM gem5 Developers uint8_t size = bits(machInst, 31, 30); 48210037SARM gem5 Developers switch (opc) { 48310037SARM gem5 Developers case 0x0: 48410037SARM gem5 Developers switch (size) { 48510037SARM gem5 Developers case 0x0: 48610037SARM gem5 Developers return new STXRB64(machInst, rt, rnsp, rs); 48710037SARM gem5 Developers case 0x1: 48810037SARM gem5 Developers return new STXRH64(machInst, rt, rnsp, rs); 48910037SARM gem5 Developers case 0x2: 49010037SARM gem5 Developers return new STXRW64(machInst, rt, rnsp, rs); 49110037SARM gem5 Developers case 0x3: 49210037SARM gem5 Developers return new STXRX64(machInst, rt, rnsp, rs); 49312595Ssiddhesh.poyarekar@gmail.com default: 49412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 49510037SARM gem5 Developers } 49610037SARM gem5 Developers case 0x1: 49710037SARM gem5 Developers switch (size) { 49810037SARM gem5 Developers case 0x0: 49910037SARM gem5 Developers return new STLXRB64(machInst, rt, rnsp, rs); 50010037SARM gem5 Developers case 0x1: 50110037SARM gem5 Developers return new STLXRH64(machInst, rt, rnsp, rs); 50210037SARM gem5 Developers case 0x2: 50310037SARM gem5 Developers return new STLXRW64(machInst, rt, rnsp, rs); 50410037SARM gem5 Developers case 0x3: 50510037SARM gem5 Developers return new STLXRX64(machInst, rt, rnsp, rs); 50612595Ssiddhesh.poyarekar@gmail.com default: 50712595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 50810037SARM gem5 Developers } 50910037SARM gem5 Developers case 0x2: 51010037SARM gem5 Developers switch (size) { 51110037SARM gem5 Developers case 0x0: 51210037SARM gem5 Developers case 0x1: 51310037SARM gem5 Developers return new Unknown64(machInst); 51410037SARM gem5 Developers case 0x2: 51510037SARM gem5 Developers return new STXPW64(machInst, rs, rt, rt2, rnsp); 51610037SARM gem5 Developers case 0x3: 51710037SARM gem5 Developers return new STXPX64(machInst, rs, rt, rt2, rnsp); 51812595Ssiddhesh.poyarekar@gmail.com default: 51912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 52010037SARM gem5 Developers } 52110037SARM gem5 Developers 52210037SARM gem5 Developers case 0x3: 52310037SARM gem5 Developers switch (size) { 52410037SARM gem5 Developers case 0x0: 52510037SARM gem5 Developers case 0x1: 52610037SARM gem5 Developers return new Unknown64(machInst); 52710037SARM gem5 Developers case 0x2: 52810037SARM gem5 Developers return new STLXPW64(machInst, rs, rt, rt2, rnsp); 52910037SARM gem5 Developers case 0x3: 53010037SARM gem5 Developers return new STLXPX64(machInst, rs, rt, rt2, rnsp); 53112595Ssiddhesh.poyarekar@gmail.com default: 53212595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 53310037SARM gem5 Developers } 53410037SARM gem5 Developers 53510037SARM gem5 Developers case 0x4: 53610037SARM gem5 Developers switch (size) { 53710037SARM gem5 Developers case 0x0: 53810037SARM gem5 Developers return new LDXRB64(machInst, rt, rnsp, rs); 53910037SARM gem5 Developers case 0x1: 54010037SARM gem5 Developers return new LDXRH64(machInst, rt, rnsp, rs); 54110037SARM gem5 Developers case 0x2: 54210037SARM gem5 Developers return new LDXRW64(machInst, rt, rnsp, rs); 54310037SARM gem5 Developers case 0x3: 54410037SARM gem5 Developers return new LDXRX64(machInst, rt, rnsp, rs); 54512595Ssiddhesh.poyarekar@gmail.com default: 54612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 54710037SARM gem5 Developers } 54810037SARM gem5 Developers case 0x5: 54910037SARM gem5 Developers switch (size) { 55010037SARM gem5 Developers case 0x0: 55110037SARM gem5 Developers return new LDAXRB64(machInst, rt, rnsp, rs); 55210037SARM gem5 Developers case 0x1: 55310037SARM gem5 Developers return new LDAXRH64(machInst, rt, rnsp, rs); 55410037SARM gem5 Developers case 0x2: 55510037SARM gem5 Developers return new LDAXRW64(machInst, rt, rnsp, rs); 55610037SARM gem5 Developers case 0x3: 55710037SARM gem5 Developers return new LDAXRX64(machInst, rt, rnsp, rs); 55812595Ssiddhesh.poyarekar@gmail.com default: 55912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 56010037SARM gem5 Developers } 56110037SARM gem5 Developers case 0x6: 56210037SARM gem5 Developers switch (size) { 56310037SARM gem5 Developers case 0x0: 56410037SARM gem5 Developers case 0x1: 56510037SARM gem5 Developers return new Unknown64(machInst); 56610037SARM gem5 Developers case 0x2: 56710037SARM gem5 Developers return new LDXPW64(machInst, rt, rt2, rnsp); 56810037SARM gem5 Developers case 0x3: 56910037SARM gem5 Developers return new LDXPX64(machInst, rt, rt2, rnsp); 57012595Ssiddhesh.poyarekar@gmail.com default: 57112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 57210037SARM gem5 Developers } 57310037SARM gem5 Developers 57410037SARM gem5 Developers case 0x7: 57510037SARM gem5 Developers switch (size) { 57610037SARM gem5 Developers case 0x0: 57710037SARM gem5 Developers case 0x1: 57810037SARM gem5 Developers return new Unknown64(machInst); 57910037SARM gem5 Developers case 0x2: 58010037SARM gem5 Developers return new LDAXPW64(machInst, rt, rt2, rnsp); 58110037SARM gem5 Developers case 0x3: 58210037SARM gem5 Developers return new LDAXPX64(machInst, rt, rt2, rnsp); 58312595Ssiddhesh.poyarekar@gmail.com default: 58412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 58510037SARM gem5 Developers } 58610037SARM gem5 Developers 58710037SARM gem5 Developers case 0x9: 58810037SARM gem5 Developers switch (size) { 58910037SARM gem5 Developers case 0x0: 59010037SARM gem5 Developers return new STLRB64(machInst, rt, rnsp); 59110037SARM gem5 Developers case 0x1: 59210037SARM gem5 Developers return new STLRH64(machInst, rt, rnsp); 59310037SARM gem5 Developers case 0x2: 59410037SARM gem5 Developers return new STLRW64(machInst, rt, rnsp); 59510037SARM gem5 Developers case 0x3: 59610037SARM gem5 Developers return new STLRX64(machInst, rt, rnsp); 59712595Ssiddhesh.poyarekar@gmail.com default: 59812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 59910037SARM gem5 Developers } 60010037SARM gem5 Developers case 0xd: 60110037SARM gem5 Developers switch (size) { 60210037SARM gem5 Developers case 0x0: 60310037SARM gem5 Developers return new LDARB64(machInst, rt, rnsp); 60410037SARM gem5 Developers case 0x1: 60510037SARM gem5 Developers return new LDARH64(machInst, rt, rnsp); 60610037SARM gem5 Developers case 0x2: 60710037SARM gem5 Developers return new LDARW64(machInst, rt, rnsp); 60810037SARM gem5 Developers case 0x3: 60910037SARM gem5 Developers return new LDARX64(machInst, rt, rnsp); 61012595Ssiddhesh.poyarekar@gmail.com default: 61112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 61210037SARM gem5 Developers } 61310037SARM gem5 Developers default: 61410037SARM gem5 Developers return new Unknown64(machInst); 61510037SARM gem5 Developers } 61610037SARM gem5 Developers } else if (bits(machInst, 31)) { 61710037SARM gem5 Developers return new Unknown64(machInst); 61810037SARM gem5 Developers } else { 61910037SARM gem5 Developers return decodeNeonMem(machInst); 62010037SARM gem5 Developers } 62110037SARM gem5 Developers case 0x1: 62210037SARM gem5 Developers { 62310037SARM gem5 Developers if (bits(machInst, 24) != 0) 62410037SARM gem5 Developers return new Unknown64(machInst); 62510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 26) << 0) | 62610037SARM gem5 Developers (bits(machInst, 31, 30) << 1); 62710037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 62810037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 62910037SARM gem5 Developers switch (switchVal) { 63010037SARM gem5 Developers case 0x0: 63110037SARM gem5 Developers return new LDRWL64_LIT(machInst, rt, imm); 63210037SARM gem5 Developers case 0x1: 63310037SARM gem5 Developers return new LDRSFP64_LIT(machInst, rt, imm); 63410037SARM gem5 Developers case 0x2: 63510037SARM gem5 Developers return new LDRXL64_LIT(machInst, rt, imm); 63610037SARM gem5 Developers case 0x3: 63710037SARM gem5 Developers return new LDRDFP64_LIT(machInst, rt, imm); 63810037SARM gem5 Developers case 0x4: 63910037SARM gem5 Developers return new LDRSWL64_LIT(machInst, rt, imm); 64010037SARM gem5 Developers case 0x5: 64110037SARM gem5 Developers return new BigFpMemLit("ldr", machInst, rt, imm); 64210037SARM gem5 Developers case 0x6: 64310037SARM gem5 Developers return new PRFM64_LIT(machInst, rt, imm); 64410037SARM gem5 Developers default: 64510037SARM gem5 Developers return new Unknown64(machInst); 64610037SARM gem5 Developers } 64710037SARM gem5 Developers } 64810037SARM gem5 Developers case 0x2: 64910037SARM gem5 Developers { 65010037SARM gem5 Developers uint8_t opc = bits(machInst, 31, 30); 65110037SARM gem5 Developers if (opc >= 3) 65210037SARM gem5 Developers return new Unknown64(machInst); 65310037SARM gem5 Developers uint32_t size = 0; 65410037SARM gem5 Developers bool fp = bits(machInst, 26); 65510037SARM gem5 Developers bool load = bits(machInst, 22); 65610037SARM gem5 Developers if (fp) { 65710037SARM gem5 Developers size = 4 << opc; 65810037SARM gem5 Developers } else { 65910037SARM gem5 Developers if ((opc == 1) && !load) 66010037SARM gem5 Developers return new Unknown64(machInst); 66110037SARM gem5 Developers size = (opc == 0 || opc == 1) ? 4 : 8; 66210037SARM gem5 Developers } 66310037SARM gem5 Developers uint8_t type = bits(machInst, 24, 23); 66410037SARM gem5 Developers int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 66510037SARM gem5 Developers 66610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 66710037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 66810037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 66910037SARM gem5 Developers 67010037SARM gem5 Developers bool noAlloc = (type == 0); 67110037SARM gem5 Developers bool signExt = !noAlloc && !fp && opc == 1; 67210037SARM gem5 Developers PairMemOp::AddrMode mode; 67310037SARM gem5 Developers const char *mnemonic = NULL; 67410037SARM gem5 Developers switch (type) { 67510037SARM gem5 Developers case 0x0: 67610037SARM gem5 Developers case 0x2: 67710037SARM gem5 Developers mode = PairMemOp::AddrMd_Offset; 67810037SARM gem5 Developers break; 67910037SARM gem5 Developers case 0x1: 68010037SARM gem5 Developers mode = PairMemOp::AddrMd_PostIndex; 68110037SARM gem5 Developers break; 68210037SARM gem5 Developers case 0x3: 68310037SARM gem5 Developers mode = PairMemOp::AddrMd_PreIndex; 68410037SARM gem5 Developers break; 68510037SARM gem5 Developers default: 68610037SARM gem5 Developers return new Unknown64(machInst); 68710037SARM gem5 Developers } 68810037SARM gem5 Developers if (load) { 68910037SARM gem5 Developers if (noAlloc) 69010037SARM gem5 Developers mnemonic = "ldnp"; 69110037SARM gem5 Developers else if (signExt) 69210037SARM gem5 Developers mnemonic = "ldpsw"; 69310037SARM gem5 Developers else 69410037SARM gem5 Developers mnemonic = "ldp"; 69510037SARM gem5 Developers } else { 69610037SARM gem5 Developers if (noAlloc) 69710037SARM gem5 Developers mnemonic = "stnp"; 69810037SARM gem5 Developers else 69910037SARM gem5 Developers mnemonic = "stp"; 70010037SARM gem5 Developers } 70110037SARM gem5 Developers 70210037SARM gem5 Developers return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 70310037SARM gem5 Developers signExt, false, false, imm, mode, rn, rt, rt2); 70410037SARM gem5 Developers } 70510037SARM gem5 Developers // bit 29:27=111, 25=0 70610037SARM gem5 Developers case 0x3: 70710037SARM gem5 Developers { 70810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 70910037SARM gem5 Developers (bits(machInst, 26) << 2) | 71010037SARM gem5 Developers (bits(machInst, 31, 30) << 3); 71110037SARM gem5 Developers if (bits(machInst, 24) == 1) { 71210037SARM gem5 Developers uint64_t imm12 = bits(machInst, 21, 10); 71310037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 71410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 71510037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 71610037SARM gem5 Developers switch (switchVal) { 71710037SARM gem5 Developers case 0x00: 71810037SARM gem5 Developers return new STRB64_IMM(machInst, rt, rnsp, imm12); 71910037SARM gem5 Developers case 0x01: 72010037SARM gem5 Developers return new LDRB64_IMM(machInst, rt, rnsp, imm12); 72110037SARM gem5 Developers case 0x02: 72210037SARM gem5 Developers return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 72310037SARM gem5 Developers case 0x03: 72410037SARM gem5 Developers return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 72510037SARM gem5 Developers case 0x04: 72610037SARM gem5 Developers return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 72710037SARM gem5 Developers case 0x05: 72810037SARM gem5 Developers return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 72910037SARM gem5 Developers case 0x06: 73010037SARM gem5 Developers return new BigFpMemImm("str", machInst, false, 73110037SARM gem5 Developers rt, rnsp, imm12 << 4); 73210037SARM gem5 Developers case 0x07: 73310037SARM gem5 Developers return new BigFpMemImm("ldr", machInst, true, 73410037SARM gem5 Developers rt, rnsp, imm12 << 4); 73510037SARM gem5 Developers case 0x08: 73610037SARM gem5 Developers return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 73710037SARM gem5 Developers case 0x09: 73810037SARM gem5 Developers return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 73910037SARM gem5 Developers case 0x0a: 74010037SARM gem5 Developers return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 74110037SARM gem5 Developers case 0x0b: 74210037SARM gem5 Developers return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 74310037SARM gem5 Developers case 0x0c: 74410037SARM gem5 Developers return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 74510037SARM gem5 Developers case 0x0d: 74610037SARM gem5 Developers return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 74710037SARM gem5 Developers case 0x10: 74810037SARM gem5 Developers return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 74910037SARM gem5 Developers case 0x11: 75010037SARM gem5 Developers return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 75110037SARM gem5 Developers case 0x12: 75210037SARM gem5 Developers return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 75310037SARM gem5 Developers case 0x14: 75410037SARM gem5 Developers return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 75510037SARM gem5 Developers case 0x15: 75610037SARM gem5 Developers return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 75710037SARM gem5 Developers case 0x18: 75810037SARM gem5 Developers return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 75910037SARM gem5 Developers case 0x19: 76010037SARM gem5 Developers return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 76110037SARM gem5 Developers case 0x1a: 76210037SARM gem5 Developers return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 76310037SARM gem5 Developers case 0x1c: 76410037SARM gem5 Developers return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 76510037SARM gem5 Developers case 0x1d: 76610037SARM gem5 Developers return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 76710037SARM gem5 Developers default: 76810037SARM gem5 Developers return new Unknown64(machInst); 76910037SARM gem5 Developers } 77010037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 77110037SARM gem5 Developers if (bits(machInst, 11, 10) != 0x2) 77210037SARM gem5 Developers return new Unknown64(machInst); 77310037SARM gem5 Developers if (!bits(machInst, 14)) 77410037SARM gem5 Developers return new Unknown64(machInst); 77510037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 77610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 77710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 77810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 77910037SARM gem5 Developers ArmExtendType type = 78010037SARM gem5 Developers (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 78110037SARM gem5 Developers uint8_t s = bits(machInst, 12); 78210037SARM gem5 Developers switch (switchVal) { 78310037SARM gem5 Developers case 0x00: 78410037SARM gem5 Developers return new STRB64_REG(machInst, rt, rnsp, rm, type, 0); 78510037SARM gem5 Developers case 0x01: 78610037SARM gem5 Developers return new LDRB64_REG(machInst, rt, rnsp, rm, type, 0); 78710037SARM gem5 Developers case 0x02: 78810037SARM gem5 Developers return new LDRSBX64_REG(machInst, rt, rnsp, rm, type, 0); 78910037SARM gem5 Developers case 0x03: 79010037SARM gem5 Developers return new LDRSBW64_REG(machInst, rt, rnsp, rm, type, 0); 79110037SARM gem5 Developers case 0x04: 79210037SARM gem5 Developers return new STRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 79310037SARM gem5 Developers case 0x05: 79410037SARM gem5 Developers return new LDRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 79510037SARM gem5 Developers case 0x6: 79610037SARM gem5 Developers return new BigFpMemReg("str", machInst, false, 79710037SARM gem5 Developers rt, rnsp, rm, type, s * 4); 79810037SARM gem5 Developers case 0x7: 79910037SARM gem5 Developers return new BigFpMemReg("ldr", machInst, true, 80010037SARM gem5 Developers rt, rnsp, rm, type, s * 4); 80110037SARM gem5 Developers case 0x08: 80210037SARM gem5 Developers return new STRH64_REG(machInst, rt, rnsp, rm, type, s); 80310037SARM gem5 Developers case 0x09: 80410037SARM gem5 Developers return new LDRH64_REG(machInst, rt, rnsp, rm, type, s); 80510037SARM gem5 Developers case 0x0a: 80610037SARM gem5 Developers return new LDRSHX64_REG(machInst, rt, rnsp, rm, type, s); 80710037SARM gem5 Developers case 0x0b: 80810037SARM gem5 Developers return new LDRSHW64_REG(machInst, rt, rnsp, rm, type, s); 80910037SARM gem5 Developers case 0x0c: 81010037SARM gem5 Developers return new STRHFP64_REG(machInst, rt, rnsp, rm, type, s); 81110037SARM gem5 Developers case 0x0d: 81210037SARM gem5 Developers return new LDRHFP64_REG(machInst, rt, rnsp, rm, type, s); 81310037SARM gem5 Developers case 0x10: 81410037SARM gem5 Developers return new STRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 81510037SARM gem5 Developers case 0x11: 81610037SARM gem5 Developers return new LDRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 81710037SARM gem5 Developers case 0x12: 81810037SARM gem5 Developers return new LDRSW64_REG(machInst, rt, rnsp, rm, type, s * 2); 81910037SARM gem5 Developers case 0x14: 82010037SARM gem5 Developers return new STRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 82110037SARM gem5 Developers case 0x15: 82210037SARM gem5 Developers return new LDRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 82310037SARM gem5 Developers case 0x18: 82410037SARM gem5 Developers return new STRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 82510037SARM gem5 Developers case 0x19: 82610037SARM gem5 Developers return new LDRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 82710037SARM gem5 Developers case 0x1a: 82810037SARM gem5 Developers return new PRFM64_REG(machInst, rt, rnsp, rm, type, s * 3); 82910037SARM gem5 Developers case 0x1c: 83010037SARM gem5 Developers return new STRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 83110037SARM gem5 Developers case 0x1d: 83210037SARM gem5 Developers return new LDRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 83310037SARM gem5 Developers default: 83410037SARM gem5 Developers return new Unknown64(machInst); 83510037SARM gem5 Developers } 83610037SARM gem5 Developers } else { 83710037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0 83810037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 83910037SARM gem5 Developers case 0x0: 84010037SARM gem5 Developers { 84110037SARM gem5 Developers IntRegIndex rt = 84210037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 84310037SARM gem5 Developers IntRegIndex rn = 84410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 84510037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 84610037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 84710037SARM gem5 Developers switch (switchVal) { 84810037SARM gem5 Developers case 0x00: 84910037SARM gem5 Developers return new STURB64_IMM(machInst, rt, rnsp, imm); 85010037SARM gem5 Developers case 0x01: 85110037SARM gem5 Developers return new LDURB64_IMM(machInst, rt, rnsp, imm); 85210037SARM gem5 Developers case 0x02: 85310037SARM gem5 Developers return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 85410037SARM gem5 Developers case 0x03: 85510037SARM gem5 Developers return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 85610037SARM gem5 Developers case 0x04: 85710037SARM gem5 Developers return new STURBFP64_IMM(machInst, rt, rnsp, imm); 85810037SARM gem5 Developers case 0x05: 85910037SARM gem5 Developers return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 86010037SARM gem5 Developers case 0x06: 86110037SARM gem5 Developers return new BigFpMemImm("stur", machInst, false, 86210037SARM gem5 Developers rt, rnsp, imm); 86310037SARM gem5 Developers case 0x07: 86410037SARM gem5 Developers return new BigFpMemImm("ldur", machInst, true, 86510037SARM gem5 Developers rt, rnsp, imm); 86610037SARM gem5 Developers case 0x08: 86710037SARM gem5 Developers return new STURH64_IMM(machInst, rt, rnsp, imm); 86810037SARM gem5 Developers case 0x09: 86910037SARM gem5 Developers return new LDURH64_IMM(machInst, rt, rnsp, imm); 87010037SARM gem5 Developers case 0x0a: 87110037SARM gem5 Developers return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 87210037SARM gem5 Developers case 0x0b: 87310037SARM gem5 Developers return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 87410037SARM gem5 Developers case 0x0c: 87510037SARM gem5 Developers return new STURHFP64_IMM(machInst, rt, rnsp, imm); 87610037SARM gem5 Developers case 0x0d: 87710037SARM gem5 Developers return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 87810037SARM gem5 Developers case 0x10: 87910037SARM gem5 Developers return new STURW64_IMM(machInst, rt, rnsp, imm); 88010037SARM gem5 Developers case 0x11: 88110037SARM gem5 Developers return new LDURW64_IMM(machInst, rt, rnsp, imm); 88210037SARM gem5 Developers case 0x12: 88310037SARM gem5 Developers return new LDURSW64_IMM(machInst, rt, rnsp, imm); 88410037SARM gem5 Developers case 0x14: 88510037SARM gem5 Developers return new STURSFP64_IMM(machInst, rt, rnsp, imm); 88610037SARM gem5 Developers case 0x15: 88710037SARM gem5 Developers return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 88810037SARM gem5 Developers case 0x18: 88910037SARM gem5 Developers return new STURX64_IMM(machInst, rt, rnsp, imm); 89010037SARM gem5 Developers case 0x19: 89110037SARM gem5 Developers return new LDURX64_IMM(machInst, rt, rnsp, imm); 89210037SARM gem5 Developers case 0x1a: 89310037SARM gem5 Developers return new PRFUM64_IMM(machInst, rt, rnsp, imm); 89410037SARM gem5 Developers case 0x1c: 89510037SARM gem5 Developers return new STURDFP64_IMM(machInst, rt, rnsp, imm); 89610037SARM gem5 Developers case 0x1d: 89710037SARM gem5 Developers return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 89810037SARM gem5 Developers default: 89910037SARM gem5 Developers return new Unknown64(machInst); 90010037SARM gem5 Developers } 90110037SARM gem5 Developers } 90210037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0, 11:10=01 90310037SARM gem5 Developers case 0x1: 90410037SARM gem5 Developers { 90510037SARM gem5 Developers IntRegIndex rt = 90610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 90710037SARM gem5 Developers IntRegIndex rn = 90810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 90910037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 91010037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 91110037SARM gem5 Developers switch (switchVal) { 91210037SARM gem5 Developers case 0x00: 91310037SARM gem5 Developers return new STRB64_POST(machInst, rt, rnsp, imm); 91410037SARM gem5 Developers case 0x01: 91510037SARM gem5 Developers return new LDRB64_POST(machInst, rt, rnsp, imm); 91610037SARM gem5 Developers case 0x02: 91710037SARM gem5 Developers return new LDRSBX64_POST(machInst, rt, rnsp, imm); 91810037SARM gem5 Developers case 0x03: 91910037SARM gem5 Developers return new LDRSBW64_POST(machInst, rt, rnsp, imm); 92010037SARM gem5 Developers case 0x04: 92110037SARM gem5 Developers return new STRBFP64_POST(machInst, rt, rnsp, imm); 92210037SARM gem5 Developers case 0x05: 92310037SARM gem5 Developers return new LDRBFP64_POST(machInst, rt, rnsp, imm); 92410037SARM gem5 Developers case 0x06: 92510037SARM gem5 Developers return new BigFpMemPost("str", machInst, false, 92610037SARM gem5 Developers rt, rnsp, imm); 92710037SARM gem5 Developers case 0x07: 92810037SARM gem5 Developers return new BigFpMemPost("ldr", machInst, true, 92910037SARM gem5 Developers rt, rnsp, imm); 93010037SARM gem5 Developers case 0x08: 93110037SARM gem5 Developers return new STRH64_POST(machInst, rt, rnsp, imm); 93210037SARM gem5 Developers case 0x09: 93310037SARM gem5 Developers return new LDRH64_POST(machInst, rt, rnsp, imm); 93410037SARM gem5 Developers case 0x0a: 93510037SARM gem5 Developers return new LDRSHX64_POST(machInst, rt, rnsp, imm); 93610037SARM gem5 Developers case 0x0b: 93710037SARM gem5 Developers return new LDRSHW64_POST(machInst, rt, rnsp, imm); 93810037SARM gem5 Developers case 0x0c: 93910037SARM gem5 Developers return new STRHFP64_POST(machInst, rt, rnsp, imm); 94010037SARM gem5 Developers case 0x0d: 94110037SARM gem5 Developers return new LDRHFP64_POST(machInst, rt, rnsp, imm); 94210037SARM gem5 Developers case 0x10: 94310037SARM gem5 Developers return new STRW64_POST(machInst, rt, rnsp, imm); 94410037SARM gem5 Developers case 0x11: 94510037SARM gem5 Developers return new LDRW64_POST(machInst, rt, rnsp, imm); 94610037SARM gem5 Developers case 0x12: 94710037SARM gem5 Developers return new LDRSW64_POST(machInst, rt, rnsp, imm); 94810037SARM gem5 Developers case 0x14: 94910037SARM gem5 Developers return new STRSFP64_POST(machInst, rt, rnsp, imm); 95010037SARM gem5 Developers case 0x15: 95110037SARM gem5 Developers return new LDRSFP64_POST(machInst, rt, rnsp, imm); 95210037SARM gem5 Developers case 0x18: 95310037SARM gem5 Developers return new STRX64_POST(machInst, rt, rnsp, imm); 95410037SARM gem5 Developers case 0x19: 95510037SARM gem5 Developers return new LDRX64_POST(machInst, rt, rnsp, imm); 95610037SARM gem5 Developers case 0x1c: 95710037SARM gem5 Developers return new STRDFP64_POST(machInst, rt, rnsp, imm); 95810037SARM gem5 Developers case 0x1d: 95910037SARM gem5 Developers return new LDRDFP64_POST(machInst, rt, rnsp, imm); 96010037SARM gem5 Developers default: 96110037SARM gem5 Developers return new Unknown64(machInst); 96210037SARM gem5 Developers } 96310037SARM gem5 Developers } 96410037SARM gem5 Developers case 0x2: 96510037SARM gem5 Developers { 96610037SARM gem5 Developers IntRegIndex rt = 96710037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 96810037SARM gem5 Developers IntRegIndex rn = 96910037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 97010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 97110037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 97210037SARM gem5 Developers switch (switchVal) { 97310037SARM gem5 Developers case 0x00: 97410037SARM gem5 Developers return new STTRB64_IMM(machInst, rt, rnsp, imm); 97510037SARM gem5 Developers case 0x01: 97610037SARM gem5 Developers return new LDTRB64_IMM(machInst, rt, rnsp, imm); 97710037SARM gem5 Developers case 0x02: 97810037SARM gem5 Developers return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 97910037SARM gem5 Developers case 0x03: 98010037SARM gem5 Developers return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 98110037SARM gem5 Developers case 0x08: 98210037SARM gem5 Developers return new STTRH64_IMM(machInst, rt, rnsp, imm); 98310037SARM gem5 Developers case 0x09: 98410037SARM gem5 Developers return new LDTRH64_IMM(machInst, rt, rnsp, imm); 98510037SARM gem5 Developers case 0x0a: 98610037SARM gem5 Developers return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 98710037SARM gem5 Developers case 0x0b: 98810037SARM gem5 Developers return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 98910037SARM gem5 Developers case 0x10: 99010037SARM gem5 Developers return new STTRW64_IMM(machInst, rt, rnsp, imm); 99110037SARM gem5 Developers case 0x11: 99210037SARM gem5 Developers return new LDTRW64_IMM(machInst, rt, rnsp, imm); 99310037SARM gem5 Developers case 0x12: 99410037SARM gem5 Developers return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 99510037SARM gem5 Developers case 0x18: 99610037SARM gem5 Developers return new STTRX64_IMM(machInst, rt, rnsp, imm); 99710037SARM gem5 Developers case 0x19: 99810037SARM gem5 Developers return new LDTRX64_IMM(machInst, rt, rnsp, imm); 99910037SARM gem5 Developers default: 100010037SARM gem5 Developers return new Unknown64(machInst); 100110037SARM gem5 Developers } 100210037SARM gem5 Developers } 100310037SARM gem5 Developers case 0x3: 100410037SARM gem5 Developers { 100510037SARM gem5 Developers IntRegIndex rt = 100610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 100710037SARM gem5 Developers IntRegIndex rn = 100810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 100910037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 101010037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 101110037SARM gem5 Developers switch (switchVal) { 101210037SARM gem5 Developers case 0x00: 101310037SARM gem5 Developers return new STRB64_PRE(machInst, rt, rnsp, imm); 101410037SARM gem5 Developers case 0x01: 101510037SARM gem5 Developers return new LDRB64_PRE(machInst, rt, rnsp, imm); 101610037SARM gem5 Developers case 0x02: 101710037SARM gem5 Developers return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 101810037SARM gem5 Developers case 0x03: 101910037SARM gem5 Developers return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 102010037SARM gem5 Developers case 0x04: 102110037SARM gem5 Developers return new STRBFP64_PRE(machInst, rt, rnsp, imm); 102210037SARM gem5 Developers case 0x05: 102310037SARM gem5 Developers return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 102410037SARM gem5 Developers case 0x06: 102510037SARM gem5 Developers return new BigFpMemPre("str", machInst, false, 102610037SARM gem5 Developers rt, rnsp, imm); 102710037SARM gem5 Developers case 0x07: 102810037SARM gem5 Developers return new BigFpMemPre("ldr", machInst, true, 102910037SARM gem5 Developers rt, rnsp, imm); 103010037SARM gem5 Developers case 0x08: 103110037SARM gem5 Developers return new STRH64_PRE(machInst, rt, rnsp, imm); 103210037SARM gem5 Developers case 0x09: 103310037SARM gem5 Developers return new LDRH64_PRE(machInst, rt, rnsp, imm); 103410037SARM gem5 Developers case 0x0a: 103510037SARM gem5 Developers return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 103610037SARM gem5 Developers case 0x0b: 103710037SARM gem5 Developers return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 103810037SARM gem5 Developers case 0x0c: 103910037SARM gem5 Developers return new STRHFP64_PRE(machInst, rt, rnsp, imm); 104010037SARM gem5 Developers case 0x0d: 104110037SARM gem5 Developers return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 104210037SARM gem5 Developers case 0x10: 104310037SARM gem5 Developers return new STRW64_PRE(machInst, rt, rnsp, imm); 104410037SARM gem5 Developers case 0x11: 104510037SARM gem5 Developers return new LDRW64_PRE(machInst, rt, rnsp, imm); 104610037SARM gem5 Developers case 0x12: 104710037SARM gem5 Developers return new LDRSW64_PRE(machInst, rt, rnsp, imm); 104810037SARM gem5 Developers case 0x14: 104910037SARM gem5 Developers return new STRSFP64_PRE(machInst, rt, rnsp, imm); 105010037SARM gem5 Developers case 0x15: 105110037SARM gem5 Developers return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 105210037SARM gem5 Developers case 0x18: 105310037SARM gem5 Developers return new STRX64_PRE(machInst, rt, rnsp, imm); 105410037SARM gem5 Developers case 0x19: 105510037SARM gem5 Developers return new LDRX64_PRE(machInst, rt, rnsp, imm); 105610037SARM gem5 Developers case 0x1c: 105710037SARM gem5 Developers return new STRDFP64_PRE(machInst, rt, rnsp, imm); 105810037SARM gem5 Developers case 0x1d: 105910037SARM gem5 Developers return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 106010037SARM gem5 Developers default: 106110037SARM gem5 Developers return new Unknown64(machInst); 106210037SARM gem5 Developers } 106310037SARM gem5 Developers } 106412595Ssiddhesh.poyarekar@gmail.com default: 106512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 106610037SARM gem5 Developers } 106710037SARM gem5 Developers } 106810037SARM gem5 Developers } 106912595Ssiddhesh.poyarekar@gmail.com default: 107012595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 107110037SARM gem5 Developers } 107210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case1", machInst); 107310037SARM gem5 Developers } 107410037SARM gem5 Developers} 107510037SARM gem5 Developers}}; 107610037SARM gem5 Developers 107710037SARM gem5 Developersoutput decoder {{ 107810037SARM gem5 Developersnamespace Aarch64 107910037SARM gem5 Developers{ 108010037SARM gem5 Developers StaticInstPtr 108110037SARM gem5 Developers decodeDataProcReg(ExtMachInst machInst) 108210037SARM gem5 Developers { 108310037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 28) << 1) | 108410037SARM gem5 Developers (bits(machInst, 24) << 0); 108510037SARM gem5 Developers switch (switchVal) { 108610037SARM gem5 Developers case 0x0: 108710037SARM gem5 Developers { 108810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 21) << 0) | 108910037SARM gem5 Developers (bits(machInst, 30, 29) << 1); 109010037SARM gem5 Developers ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 109110037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 109210037SARM gem5 Developers bool sf = bits(machInst, 31); 109310037SARM gem5 Developers if (!sf && (imm6 & 0x20)) 109410037SARM gem5 Developers return new Unknown64(machInst); 109510037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 109610337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 109710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 109810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 109910037SARM gem5 Developers 110010037SARM gem5 Developers switch (switchVal) { 110110037SARM gem5 Developers case 0x0: 110210337SAndrew.Bardsley@arm.com return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 110310037SARM gem5 Developers case 0x1: 110410337SAndrew.Bardsley@arm.com return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 110510037SARM gem5 Developers case 0x2: 110610337SAndrew.Bardsley@arm.com return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 110710037SARM gem5 Developers case 0x3: 110810337SAndrew.Bardsley@arm.com return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 110910037SARM gem5 Developers case 0x4: 111010337SAndrew.Bardsley@arm.com return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 111110037SARM gem5 Developers case 0x5: 111210337SAndrew.Bardsley@arm.com return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 111310037SARM gem5 Developers case 0x6: 111410337SAndrew.Bardsley@arm.com return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 111510037SARM gem5 Developers case 0x7: 111610337SAndrew.Bardsley@arm.com return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 111712595Ssiddhesh.poyarekar@gmail.com default: 111812595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 111910037SARM gem5 Developers } 112010037SARM gem5 Developers } 112110037SARM gem5 Developers case 0x1: 112210037SARM gem5 Developers { 112310037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 112410037SARM gem5 Developers if (bits(machInst, 21) == 0) { 112510037SARM gem5 Developers ArmShiftType type = 112610037SARM gem5 Developers (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 112710037SARM gem5 Developers if (type == ROR) 112810037SARM gem5 Developers return new Unknown64(machInst); 112910037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 113010037SARM gem5 Developers if (!bits(machInst, 31) && bits(imm6, 5)) 113110037SARM gem5 Developers return new Unknown64(machInst); 113210037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 113310337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 113410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 113510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 113610037SARM gem5 Developers switch (switchVal) { 113710037SARM gem5 Developers case 0x0: 113810337SAndrew.Bardsley@arm.com return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 113910037SARM gem5 Developers case 0x1: 114010337SAndrew.Bardsley@arm.com return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 114110037SARM gem5 Developers case 0x2: 114210337SAndrew.Bardsley@arm.com return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 114310037SARM gem5 Developers case 0x3: 114410337SAndrew.Bardsley@arm.com return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 114512595Ssiddhesh.poyarekar@gmail.com default: 114612595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 114710037SARM gem5 Developers } 114810037SARM gem5 Developers } else { 114910037SARM gem5 Developers if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 115010037SARM gem5 Developers return new Unknown64(machInst); 115110037SARM gem5 Developers ArmExtendType type = 115210037SARM gem5 Developers (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 115310037SARM gem5 Developers uint8_t imm3 = bits(machInst, 12, 10); 115410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 115510037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 115610337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 115710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 115810037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 115910037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 116010037SARM gem5 Developers 116110037SARM gem5 Developers switch (switchVal) { 116210037SARM gem5 Developers case 0x0: 116310037SARM gem5 Developers return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 116410037SARM gem5 Developers case 0x1: 116510337SAndrew.Bardsley@arm.com return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 116610037SARM gem5 Developers case 0x2: 116710037SARM gem5 Developers return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 116810037SARM gem5 Developers case 0x3: 116910337SAndrew.Bardsley@arm.com return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 117012595Ssiddhesh.poyarekar@gmail.com default: 117112595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 117210037SARM gem5 Developers } 117310037SARM gem5 Developers } 117410037SARM gem5 Developers } 117510037SARM gem5 Developers case 0x2: 117610037SARM gem5 Developers { 117710037SARM gem5 Developers if (bits(machInst, 21) == 1) 117810037SARM gem5 Developers return new Unknown64(machInst); 117910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 118010337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 118110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 118210037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 118310037SARM gem5 Developers switch (bits(machInst, 23, 22)) { 118410037SARM gem5 Developers case 0x0: 118510037SARM gem5 Developers { 118610037SARM gem5 Developers if (bits(machInst, 15, 10)) 118710037SARM gem5 Developers return new Unknown64(machInst); 118810037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 118910037SARM gem5 Developers switch (switchVal) { 119010037SARM gem5 Developers case 0x0: 119110337SAndrew.Bardsley@arm.com return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 119210037SARM gem5 Developers case 0x1: 119310337SAndrew.Bardsley@arm.com return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 119410037SARM gem5 Developers case 0x2: 119510337SAndrew.Bardsley@arm.com return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 119610037SARM gem5 Developers case 0x3: 119710337SAndrew.Bardsley@arm.com return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 119812595Ssiddhesh.poyarekar@gmail.com default: 119912595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 120010037SARM gem5 Developers } 120110037SARM gem5 Developers } 120210037SARM gem5 Developers case 0x1: 120310037SARM gem5 Developers { 120410037SARM gem5 Developers if ((bits(machInst, 4) == 1) || 120510037SARM gem5 Developers (bits(machInst, 10) == 1) || 120610037SARM gem5 Developers (bits(machInst, 29) == 0)) { 120710037SARM gem5 Developers return new Unknown64(machInst); 120810037SARM gem5 Developers } 120910037SARM gem5 Developers ConditionCode cond = 121010037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 121110037SARM gem5 Developers uint8_t flags = bits(machInst, 3, 0); 121210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 121310037SARM gem5 Developers if (bits(machInst, 11) == 0) { 121410037SARM gem5 Developers IntRegIndex rm = 121510037SARM gem5 Developers (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 121610037SARM gem5 Developers if (bits(machInst, 30) == 0) { 121710037SARM gem5 Developers return new CcmnReg64(machInst, rn, rm, cond, flags); 121810037SARM gem5 Developers } else { 121910037SARM gem5 Developers return new CcmpReg64(machInst, rn, rm, cond, flags); 122010037SARM gem5 Developers } 122110037SARM gem5 Developers } else { 122210037SARM gem5 Developers uint8_t imm5 = bits(machInst, 20, 16); 122310037SARM gem5 Developers if (bits(machInst, 30) == 0) { 122410037SARM gem5 Developers return new CcmnImm64(machInst, rn, imm5, cond, flags); 122510037SARM gem5 Developers } else { 122610037SARM gem5 Developers return new CcmpImm64(machInst, rn, imm5, cond, flags); 122710037SARM gem5 Developers } 122810037SARM gem5 Developers } 122910037SARM gem5 Developers } 123010037SARM gem5 Developers case 0x2: 123110037SARM gem5 Developers { 123210037SARM gem5 Developers if (bits(machInst, 29) == 1 || 123310037SARM gem5 Developers bits(machInst, 11) == 1) { 123410037SARM gem5 Developers return new Unknown64(machInst); 123510037SARM gem5 Developers } 123610037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 10) << 0) | 123710037SARM gem5 Developers (bits(machInst, 30) << 1); 123810037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 123910337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 124010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 124110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 124210037SARM gem5 Developers ConditionCode cond = 124310037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 124410037SARM gem5 Developers switch (switchVal) { 124510037SARM gem5 Developers case 0x0: 124610337SAndrew.Bardsley@arm.com return new Csel64(machInst, rdzr, rn, rm, cond); 124710037SARM gem5 Developers case 0x1: 124810337SAndrew.Bardsley@arm.com return new Csinc64(machInst, rdzr, rn, rm, cond); 124910037SARM gem5 Developers case 0x2: 125010337SAndrew.Bardsley@arm.com return new Csinv64(machInst, rdzr, rn, rm, cond); 125110037SARM gem5 Developers case 0x3: 125210337SAndrew.Bardsley@arm.com return new Csneg64(machInst, rdzr, rn, rm, cond); 125312595Ssiddhesh.poyarekar@gmail.com default: 125412595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 125510037SARM gem5 Developers } 125610037SARM gem5 Developers } 125710037SARM gem5 Developers case 0x3: 125810037SARM gem5 Developers if (bits(machInst, 30) == 0) { 125910037SARM gem5 Developers if (bits(machInst, 29) != 0) 126010037SARM gem5 Developers return new Unknown64(machInst); 126110037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 126210037SARM gem5 Developers switch (switchVal) { 126310037SARM gem5 Developers case 0x2: 126410337SAndrew.Bardsley@arm.com return new Udiv64(machInst, rdzr, rn, rm); 126510037SARM gem5 Developers case 0x3: 126610337SAndrew.Bardsley@arm.com return new Sdiv64(machInst, rdzr, rn, rm); 126710037SARM gem5 Developers case 0x8: 126810337SAndrew.Bardsley@arm.com return new Lslv64(machInst, rdzr, rn, rm); 126910037SARM gem5 Developers case 0x9: 127010337SAndrew.Bardsley@arm.com return new Lsrv64(machInst, rdzr, rn, rm); 127110037SARM gem5 Developers case 0xa: 127210337SAndrew.Bardsley@arm.com return new Asrv64(machInst, rdzr, rn, rm); 127310037SARM gem5 Developers case 0xb: 127410337SAndrew.Bardsley@arm.com return new Rorv64(machInst, rdzr, rn, rm); 127512258Sgiacomo.travaglini@arm.com case 0x10: 127612258Sgiacomo.travaglini@arm.com return new Crc32b64(machInst, rdzr, rn, rm); 127712258Sgiacomo.travaglini@arm.com case 0x11: 127812258Sgiacomo.travaglini@arm.com return new Crc32h64(machInst, rdzr, rn, rm); 127912258Sgiacomo.travaglini@arm.com case 0x12: 128012258Sgiacomo.travaglini@arm.com return new Crc32w64(machInst, rdzr, rn, rm); 128112258Sgiacomo.travaglini@arm.com case 0x13: 128212258Sgiacomo.travaglini@arm.com return new Crc32x64(machInst, rdzr, rn, rm); 128312258Sgiacomo.travaglini@arm.com case 0x14: 128412258Sgiacomo.travaglini@arm.com return new Crc32cb64(machInst, rdzr, rn, rm); 128512258Sgiacomo.travaglini@arm.com case 0x15: 128612258Sgiacomo.travaglini@arm.com return new Crc32ch64(machInst, rdzr, rn, rm); 128712258Sgiacomo.travaglini@arm.com case 0x16: 128812258Sgiacomo.travaglini@arm.com return new Crc32cw64(machInst, rdzr, rn, rm); 128912258Sgiacomo.travaglini@arm.com case 0x17: 129012258Sgiacomo.travaglini@arm.com return new Crc32cx64(machInst, rdzr, rn, rm); 129110037SARM gem5 Developers default: 129210037SARM gem5 Developers return new Unknown64(machInst); 129310037SARM gem5 Developers } 129410037SARM gem5 Developers } else { 129510037SARM gem5 Developers if (bits(machInst, 20, 16) != 0 || 129610037SARM gem5 Developers bits(machInst, 29) != 0) { 129710037SARM gem5 Developers return new Unknown64(machInst); 129810037SARM gem5 Developers } 129910037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 130010037SARM gem5 Developers switch (switchVal) { 130110037SARM gem5 Developers case 0x0: 130210337SAndrew.Bardsley@arm.com return new Rbit64(machInst, rdzr, rn); 130310037SARM gem5 Developers case 0x1: 130410337SAndrew.Bardsley@arm.com return new Rev1664(machInst, rdzr, rn); 130510037SARM gem5 Developers case 0x2: 130610037SARM gem5 Developers if (bits(machInst, 31) == 0) 130710337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 130810037SARM gem5 Developers else 130910337SAndrew.Bardsley@arm.com return new Rev3264(machInst, rdzr, rn); 131010037SARM gem5 Developers case 0x3: 131110037SARM gem5 Developers if (bits(machInst, 31) != 1) 131210037SARM gem5 Developers return new Unknown64(machInst); 131310337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 131410037SARM gem5 Developers case 0x4: 131510337SAndrew.Bardsley@arm.com return new Clz64(machInst, rdzr, rn); 131610037SARM gem5 Developers case 0x5: 131710337SAndrew.Bardsley@arm.com return new Cls64(machInst, rdzr, rn); 131812595Ssiddhesh.poyarekar@gmail.com default: 131912595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 132010037SARM gem5 Developers } 132110037SARM gem5 Developers } 132212595Ssiddhesh.poyarekar@gmail.com default: 132312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 132410037SARM gem5 Developers } 132510037SARM gem5 Developers } 132610037SARM gem5 Developers case 0x3: 132710037SARM gem5 Developers { 132810037SARM gem5 Developers if (bits(machInst, 30, 29) != 0x0 || 132910037SARM gem5 Developers (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 133010037SARM gem5 Developers return new Unknown64(machInst); 133110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 133210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 133310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 133410037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 133510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 133610037SARM gem5 Developers switch (bits(machInst, 23, 21)) { 133710037SARM gem5 Developers case 0x0: 133810037SARM gem5 Developers if (bits(machInst, 15) == 0) 133910337SAndrew.Bardsley@arm.com return new Madd64(machInst, rdzr, ra, rn, rm); 134010037SARM gem5 Developers else 134110337SAndrew.Bardsley@arm.com return new Msub64(machInst, rdzr, ra, rn, rm); 134210037SARM gem5 Developers case 0x1: 134310037SARM gem5 Developers if (bits(machInst, 15) == 0) 134410337SAndrew.Bardsley@arm.com return new Smaddl64(machInst, rdzr, ra, rn, rm); 134510037SARM gem5 Developers else 134610337SAndrew.Bardsley@arm.com return new Smsubl64(machInst, rdzr, ra, rn, rm); 134710037SARM gem5 Developers case 0x2: 134810037SARM gem5 Developers if (bits(machInst, 15) != 0) 134910037SARM gem5 Developers return new Unknown64(machInst); 135010337SAndrew.Bardsley@arm.com return new Smulh64(machInst, rdzr, rn, rm); 135110037SARM gem5 Developers case 0x5: 135210037SARM gem5 Developers if (bits(machInst, 15) == 0) 135310337SAndrew.Bardsley@arm.com return new Umaddl64(machInst, rdzr, ra, rn, rm); 135410037SARM gem5 Developers else 135510337SAndrew.Bardsley@arm.com return new Umsubl64(machInst, rdzr, ra, rn, rm); 135610037SARM gem5 Developers case 0x6: 135710037SARM gem5 Developers if (bits(machInst, 15) != 0) 135810037SARM gem5 Developers return new Unknown64(machInst); 135910337SAndrew.Bardsley@arm.com return new Umulh64(machInst, rdzr, rn, rm); 136010037SARM gem5 Developers default: 136110037SARM gem5 Developers return new Unknown64(machInst); 136210037SARM gem5 Developers } 136310037SARM gem5 Developers } 136412595Ssiddhesh.poyarekar@gmail.com default: 136512595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 136610037SARM gem5 Developers } 136710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case2", machInst); 136810037SARM gem5 Developers } 136910037SARM gem5 Developers} 137010037SARM gem5 Developers}}; 137110037SARM gem5 Developers 137210037SARM gem5 Developersoutput decoder {{ 137310037SARM gem5 Developersnamespace Aarch64 137410037SARM gem5 Developers{ 137511165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 137610037SARM gem5 Developers StaticInstPtr 137710037SARM gem5 Developers decodeAdvSIMD(ExtMachInst machInst) 137810037SARM gem5 Developers { 137910037SARM gem5 Developers if (bits(machInst, 24) == 1) { 138010037SARM gem5 Developers if (bits(machInst, 10) == 0) { 138111165SRekai.GonzalezAlberquilla@arm.com return decodeNeonIndexedElem<DecoderFeatures>(machInst); 138210037SARM gem5 Developers } else if (bits(machInst, 23) == 1) { 138310037SARM gem5 Developers return new Unknown64(machInst); 138410037SARM gem5 Developers } else { 138510037SARM gem5 Developers if (bits(machInst, 22, 19)) { 138610037SARM gem5 Developers return decodeNeonShiftByImm(machInst); 138710037SARM gem5 Developers } else { 138810037SARM gem5 Developers return decodeNeonModImm(machInst); 138910037SARM gem5 Developers } 139010037SARM gem5 Developers } 139110037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 139210037SARM gem5 Developers if (bits(machInst, 10) == 1) { 139311165SRekai.GonzalezAlberquilla@arm.com return decodeNeon3Same<DecoderFeatures>(machInst); 139410037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 139510037SARM gem5 Developers return decodeNeon3Diff(machInst); 139610037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 139710037SARM gem5 Developers return decodeNeon2RegMisc(machInst); 139810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 139910037SARM gem5 Developers return decodeNeonAcrossLanes(machInst); 140010037SARM gem5 Developers } else { 140110037SARM gem5 Developers return new Unknown64(machInst); 140210037SARM gem5 Developers } 140310037SARM gem5 Developers } else if (bits(machInst, 24) || 140410037SARM gem5 Developers bits(machInst, 21) || 140510037SARM gem5 Developers bits(machInst, 15)) { 140610037SARM gem5 Developers return new Unknown64(machInst); 140710037SARM gem5 Developers } else if (bits(machInst, 10) == 1) { 140810037SARM gem5 Developers if (bits(machInst, 23, 22)) 140910037SARM gem5 Developers return new Unknown64(machInst); 141010037SARM gem5 Developers return decodeNeonCopy(machInst); 141110037SARM gem5 Developers } else if (bits(machInst, 29) == 1) { 141210037SARM gem5 Developers return decodeNeonExt(machInst); 141310037SARM gem5 Developers } else if (bits(machInst, 11) == 1) { 141410037SARM gem5 Developers return decodeNeonZipUzpTrn(machInst); 141510037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0x0) { 141610037SARM gem5 Developers return decodeNeonTblTbx(machInst); 141710037SARM gem5 Developers } else { 141810037SARM gem5 Developers return new Unknown64(machInst); 141910037SARM gem5 Developers } 142010037SARM gem5 Developers return new FailUnimplemented("Unhandled Case3", machInst); 142110037SARM gem5 Developers } 142210037SARM gem5 Developers} 142310037SARM gem5 Developers}}; 142410037SARM gem5 Developers 142510037SARM gem5 Developers 142610037SARM gem5 Developersoutput decoder {{ 142710037SARM gem5 Developersnamespace Aarch64 142810037SARM gem5 Developers{ 142910037SARM gem5 Developers StaticInstPtr 143010037SARM gem5 Developers // bit 30=0, 28:25=1111 143110037SARM gem5 Developers decodeFp(ExtMachInst machInst) 143210037SARM gem5 Developers { 143310037SARM gem5 Developers if (bits(machInst, 24) == 1) { 143410037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 143510037SARM gem5 Developers return new Unknown64(machInst); 143610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 143710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 143810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 143910037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 144010037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 144110037SARM gem5 Developers (bits(machInst, 15) << 0); 144210037SARM gem5 Developers switch (switchVal) { 144310037SARM gem5 Developers case 0x0: // FMADD Sd = Sa + Sn*Sm 144410037SARM gem5 Developers return new FMAddS(machInst, rd, rn, rm, ra); 144510037SARM gem5 Developers case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 144610037SARM gem5 Developers return new FMSubS(machInst, rd, rn, rm, ra); 144710037SARM gem5 Developers case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 144810037SARM gem5 Developers return new FNMAddS(machInst, rd, rn, rm, ra); 144910037SARM gem5 Developers case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 145010037SARM gem5 Developers return new FNMSubS(machInst, rd, rn, rm, ra); 145110037SARM gem5 Developers case 0x4: // FMADD Dd = Da + Dn*Dm 145210037SARM gem5 Developers return new FMAddD(machInst, rd, rn, rm, ra); 145310037SARM gem5 Developers case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 145410037SARM gem5 Developers return new FMSubD(machInst, rd, rn, rm, ra); 145510037SARM gem5 Developers case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 145610037SARM gem5 Developers return new FNMAddD(machInst, rd, rn, rm, ra); 145710037SARM gem5 Developers case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 145810037SARM gem5 Developers return new FNMSubD(machInst, rd, rn, rm, ra); 145910037SARM gem5 Developers default: 146010037SARM gem5 Developers return new Unknown64(machInst); 146110037SARM gem5 Developers } 146210037SARM gem5 Developers } else if (bits(machInst, 21) == 0) { 146310037SARM gem5 Developers bool s = bits(machInst, 29); 146410037SARM gem5 Developers if (s) 146510037SARM gem5 Developers return new Unknown64(machInst); 146610037SARM gem5 Developers uint8_t switchVal = bits(machInst, 20, 16); 146710037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 146810037SARM gem5 Developers uint8_t scale = bits(machInst, 15, 10); 146910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 147010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 147110037SARM gem5 Developers if (bits(machInst, 18, 17) == 3 && scale != 0) 147210037SARM gem5 Developers return new Unknown64(machInst); 147310037SARM gem5 Developers // 30:24=0011110, 21=0 147410037SARM gem5 Developers switch (switchVal) { 147510037SARM gem5 Developers case 0x00: 147610037SARM gem5 Developers return new FailUnimplemented("fcvtns", machInst); 147710037SARM gem5 Developers case 0x01: 147810037SARM gem5 Developers return new FailUnimplemented("fcvtnu", machInst); 147910037SARM gem5 Developers case 0x02: 148010037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 148110037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 148210037SARM gem5 Developers return new FcvtSFixedFpSW(machInst, rd, rn, scale); 148310037SARM gem5 Developers case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 148410037SARM gem5 Developers return new FcvtSFixedFpDW(machInst, rd, rn, scale); 148510037SARM gem5 Developers case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 148610037SARM gem5 Developers return new FcvtSFixedFpSX(machInst, rd, rn, scale); 148710037SARM gem5 Developers case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 148810037SARM gem5 Developers return new FcvtSFixedFpDX(machInst, rd, rn, scale); 148910037SARM gem5 Developers default: 149010037SARM gem5 Developers return new Unknown64(machInst); 149110037SARM gem5 Developers } 149210037SARM gem5 Developers case 0x03: 149310037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 149410037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 149510037SARM gem5 Developers return new FcvtUFixedFpSW(machInst, rd, rn, scale); 149610037SARM gem5 Developers case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 149710037SARM gem5 Developers return new FcvtUFixedFpDW(machInst, rd, rn, scale); 149810037SARM gem5 Developers case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 149910037SARM gem5 Developers return new FcvtUFixedFpSX(machInst, rd, rn, scale); 150010037SARM gem5 Developers case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 150110037SARM gem5 Developers return new FcvtUFixedFpDX(machInst, rd, rn, scale); 150210037SARM gem5 Developers default: 150310037SARM gem5 Developers return new Unknown64(machInst); 150410037SARM gem5 Developers } 150510037SARM gem5 Developers case 0x04: 150610037SARM gem5 Developers return new FailUnimplemented("fcvtas", machInst); 150710037SARM gem5 Developers case 0x05: 150810037SARM gem5 Developers return new FailUnimplemented("fcvtau", machInst); 150910037SARM gem5 Developers case 0x08: 151010037SARM gem5 Developers return new FailUnimplemented("fcvtps", machInst); 151110037SARM gem5 Developers case 0x09: 151210037SARM gem5 Developers return new FailUnimplemented("fcvtpu", machInst); 151310037SARM gem5 Developers case 0x0e: 151410037SARM gem5 Developers return new FailUnimplemented("fmov elem. to 64", machInst); 151510037SARM gem5 Developers case 0x0f: 151610037SARM gem5 Developers return new FailUnimplemented("fmov 64 bit", machInst); 151710037SARM gem5 Developers case 0x10: 151810037SARM gem5 Developers return new FailUnimplemented("fcvtms", machInst); 151910037SARM gem5 Developers case 0x11: 152010037SARM gem5 Developers return new FailUnimplemented("fcvtmu", machInst); 152110037SARM gem5 Developers case 0x18: 152210037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 152310037SARM gem5 Developers case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 152410037SARM gem5 Developers return new FcvtFpSFixedSW(machInst, rd, rn, scale); 152510037SARM gem5 Developers case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 152610037SARM gem5 Developers return new FcvtFpSFixedDW(machInst, rd, rn, scale); 152710037SARM gem5 Developers case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 152810037SARM gem5 Developers return new FcvtFpSFixedSX(machInst, rd, rn, scale); 152910037SARM gem5 Developers case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 153010037SARM gem5 Developers return new FcvtFpSFixedDX(machInst, rd, rn, scale); 153110037SARM gem5 Developers default: 153210037SARM gem5 Developers return new Unknown64(machInst); 153310037SARM gem5 Developers } 153410037SARM gem5 Developers case 0x19: 153510037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 153610037SARM gem5 Developers case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 153710037SARM gem5 Developers return new FcvtFpUFixedSW(machInst, rd, rn, scale); 153810037SARM gem5 Developers case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 153910037SARM gem5 Developers return new FcvtFpUFixedDW(machInst, rd, rn, scale); 154010037SARM gem5 Developers case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 154110037SARM gem5 Developers return new FcvtFpUFixedSX(machInst, rd, rn, scale); 154210037SARM gem5 Developers case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 154310037SARM gem5 Developers return new FcvtFpUFixedDX(machInst, rd, rn, scale); 154410037SARM gem5 Developers default: 154510037SARM gem5 Developers return new Unknown64(machInst); 154610037SARM gem5 Developers } 154712595Ssiddhesh.poyarekar@gmail.com default: 154812595Ssiddhesh.poyarekar@gmail.com return new Unknown64(machInst); 154910037SARM gem5 Developers } 155010037SARM gem5 Developers } else { 155110037SARM gem5 Developers // 30=0, 28:24=11110, 21=1 155210037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 155310037SARM gem5 Developers uint8_t imm8 = bits(machInst, 20, 13); 155410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 155510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 155610037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 155710037SARM gem5 Developers case 0x0: 155810037SARM gem5 Developers if (bits(machInst, 12) == 1) { 155910037SARM gem5 Developers if (bits(machInst, 31) || 156010037SARM gem5 Developers bits(machInst, 29) || 156110037SARM gem5 Developers bits(machInst, 9, 5)) { 156210037SARM gem5 Developers return new Unknown64(machInst); 156310037SARM gem5 Developers } 156410037SARM gem5 Developers // 31:29=000, 28:24=11110, 21=1, 12:10=100 156510037SARM gem5 Developers if (type == 0) { 156610037SARM gem5 Developers // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 156710037SARM gem5 Developers // :imm8<5:0>:Zeros(19) 156810037SARM gem5 Developers uint32_t imm = vfp_modified_imm(imm8, false); 156910037SARM gem5 Developers return new FmovImmS(machInst, rd, imm); 157010037SARM gem5 Developers } else if (type == 1) { 157110037SARM gem5 Developers // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 157210037SARM gem5 Developers // :imm8<5:0>:Zeros(48) 157310037SARM gem5 Developers uint64_t imm = vfp_modified_imm(imm8, true); 157410037SARM gem5 Developers return new FmovImmD(machInst, rd, imm); 157510037SARM gem5 Developers } else { 157610037SARM gem5 Developers return new Unknown64(machInst); 157710037SARM gem5 Developers } 157810037SARM gem5 Developers } else if (bits(machInst, 13) == 1) { 157910037SARM gem5 Developers if (bits(machInst, 31) || 158010037SARM gem5 Developers bits(machInst, 29) || 158110037SARM gem5 Developers bits(machInst, 15, 14) || 158210037SARM gem5 Developers bits(machInst, 23) || 158310037SARM gem5 Developers bits(machInst, 2, 0)) { 158410037SARM gem5 Developers return new Unknown64(machInst); 158510037SARM gem5 Developers } 158610037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 158710037SARM gem5 Developers (bits(machInst, 22) << 2); 158810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) 158910037SARM gem5 Developers bits(machInst, 20, 16); 159010037SARM gem5 Developers // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 159110037SARM gem5 Developers switch (switchVal) { 159210037SARM gem5 Developers case 0x0: 159310037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,Sm) 159410037SARM gem5 Developers return new FCmpRegS(machInst, rn, rm); 159510037SARM gem5 Developers case 0x1: 159610037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,0.0) 159710037SARM gem5 Developers return new FCmpImmS(machInst, rn, 0); 159810037SARM gem5 Developers case 0x2: 159910037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,Sm) 160010037SARM gem5 Developers return new FCmpERegS(machInst, rn, rm); 160110037SARM gem5 Developers case 0x3: 160210037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,0.0) 160310037SARM gem5 Developers return new FCmpEImmS(machInst, rn, 0); 160410037SARM gem5 Developers case 0x4: 160510037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,Dm) 160610037SARM gem5 Developers return new FCmpRegD(machInst, rn, rm); 160710037SARM gem5 Developers case 0x5: 160810037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,0.0) 160910037SARM gem5 Developers return new FCmpImmD(machInst, rn, 0); 161010037SARM gem5 Developers case 0x6: 161110037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,Dm) 161210037SARM gem5 Developers return new FCmpERegD(machInst, rn, rm); 161310037SARM gem5 Developers case 0x7: 161410037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,0.0) 161510037SARM gem5 Developers return new FCmpEImmD(machInst, rn, 0); 161610037SARM gem5 Developers default: 161710037SARM gem5 Developers return new Unknown64(machInst); 161810037SARM gem5 Developers } 161910037SARM gem5 Developers } else if (bits(machInst, 14) == 1) { 162010037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 162110037SARM gem5 Developers return new Unknown64(machInst); 162210037SARM gem5 Developers uint8_t opcode = bits(machInst, 20, 15); 162310037SARM gem5 Developers // Bits 31:24=00011110, 21=1, 14:10=10000 162410037SARM gem5 Developers switch (opcode) { 162510037SARM gem5 Developers case 0x0: 162610037SARM gem5 Developers if (type == 0) 162710037SARM gem5 Developers // FMOV Sd = Sn 162810037SARM gem5 Developers return new FmovRegS(machInst, rd, rn); 162910037SARM gem5 Developers else if (type == 1) 163010037SARM gem5 Developers // FMOV Dd = Dn 163110037SARM gem5 Developers return new FmovRegD(machInst, rd, rn); 163210037SARM gem5 Developers break; 163310037SARM gem5 Developers case 0x1: 163410037SARM gem5 Developers if (type == 0) 163510037SARM gem5 Developers // FABS Sd = abs(Sn) 163610037SARM gem5 Developers return new FAbsS(machInst, rd, rn); 163710037SARM gem5 Developers else if (type == 1) 163810037SARM gem5 Developers // FABS Dd = abs(Dn) 163910037SARM gem5 Developers return new FAbsD(machInst, rd, rn); 164010037SARM gem5 Developers break; 164110037SARM gem5 Developers case 0x2: 164210037SARM gem5 Developers if (type == 0) 164310037SARM gem5 Developers // FNEG Sd = -Sn 164410037SARM gem5 Developers return new FNegS(machInst, rd, rn); 164510037SARM gem5 Developers else if (type == 1) 164610037SARM gem5 Developers // FNEG Dd = -Dn 164710037SARM gem5 Developers return new FNegD(machInst, rd, rn); 164810037SARM gem5 Developers break; 164910037SARM gem5 Developers case 0x3: 165010037SARM gem5 Developers if (type == 0) 165110037SARM gem5 Developers // FSQRT Sd = sqrt(Sn) 165210037SARM gem5 Developers return new FSqrtS(machInst, rd, rn); 165310037SARM gem5 Developers else if (type == 1) 165410037SARM gem5 Developers // FSQRT Dd = sqrt(Dn) 165510037SARM gem5 Developers return new FSqrtD(machInst, rd, rn); 165610037SARM gem5 Developers break; 165710037SARM gem5 Developers case 0x4: 165810037SARM gem5 Developers if (type == 1) 165910037SARM gem5 Developers // FCVT Sd = convertFormat(Dn) 166010037SARM gem5 Developers return new FcvtFpDFpS(machInst, rd, rn); 166110037SARM gem5 Developers else if (type == 3) 166210037SARM gem5 Developers // FCVT Sd = convertFormat(Hn) 166310037SARM gem5 Developers return new FcvtFpHFpS(machInst, rd, rn); 166410037SARM gem5 Developers break; 166510037SARM gem5 Developers case 0x5: 166610037SARM gem5 Developers if (type == 0) 166710037SARM gem5 Developers // FCVT Dd = convertFormat(Sn) 166810037SARM gem5 Developers return new FCvtFpSFpD(machInst, rd, rn); 166910037SARM gem5 Developers else if (type == 3) 167010037SARM gem5 Developers // FCVT Dd = convertFormat(Hn) 167110037SARM gem5 Developers return new FcvtFpHFpD(machInst, rd, rn); 167210037SARM gem5 Developers break; 167310037SARM gem5 Developers case 0x7: 167410037SARM gem5 Developers if (type == 0) 167510037SARM gem5 Developers // FCVT Hd = convertFormat(Sn) 167610037SARM gem5 Developers return new FcvtFpSFpH(machInst, rd, rn); 167710037SARM gem5 Developers else if (type == 1) 167810037SARM gem5 Developers // FCVT Hd = convertFormat(Dn) 167910037SARM gem5 Developers return new FcvtFpDFpH(machInst, rd, rn); 168010037SARM gem5 Developers break; 168110037SARM gem5 Developers case 0x8: 168210037SARM gem5 Developers if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 168310037SARM gem5 Developers return new FRIntNS(machInst, rd, rn); 168410037SARM gem5 Developers else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 168510037SARM gem5 Developers return new FRIntND(machInst, rd, rn); 168610037SARM gem5 Developers break; 168710037SARM gem5 Developers case 0x9: 168810037SARM gem5 Developers if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 168910037SARM gem5 Developers return new FRIntPS(machInst, rd, rn); 169010037SARM gem5 Developers else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 169110037SARM gem5 Developers return new FRIntPD(machInst, rd, rn); 169210037SARM gem5 Developers break; 169310037SARM gem5 Developers case 0xa: 169410037SARM gem5 Developers if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 169510037SARM gem5 Developers return new FRIntMS(machInst, rd, rn); 169610037SARM gem5 Developers else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 169710037SARM gem5 Developers return new FRIntMD(machInst, rd, rn); 169810037SARM gem5 Developers break; 169910037SARM gem5 Developers case 0xb: 170010037SARM gem5 Developers if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 170110037SARM gem5 Developers return new FRIntZS(machInst, rd, rn); 170210037SARM gem5 Developers else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 170310037SARM gem5 Developers return new FRIntZD(machInst, rd, rn); 170410037SARM gem5 Developers break; 170510037SARM gem5 Developers case 0xc: 170610037SARM gem5 Developers if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 170710037SARM gem5 Developers return new FRIntAS(machInst, rd, rn); 170810037SARM gem5 Developers else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 170910037SARM gem5 Developers return new FRIntAD(machInst, rd, rn); 171010037SARM gem5 Developers break; 171110037SARM gem5 Developers case 0xe: 171210037SARM gem5 Developers if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 171310037SARM gem5 Developers return new FRIntXS(machInst, rd, rn); 171410037SARM gem5 Developers else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 171510037SARM gem5 Developers return new FRIntXD(machInst, rd, rn); 171610037SARM gem5 Developers break; 171710037SARM gem5 Developers case 0xf: 171810037SARM gem5 Developers if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 171910037SARM gem5 Developers return new FRIntIS(machInst, rd, rn); 172010037SARM gem5 Developers else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 172110037SARM gem5 Developers return new FRIntID(machInst, rd, rn); 172210037SARM gem5 Developers break; 172310037SARM gem5 Developers default: 172410037SARM gem5 Developers return new Unknown64(machInst); 172510037SARM gem5 Developers } 172610037SARM gem5 Developers return new Unknown64(machInst); 172710037SARM gem5 Developers } else if (bits(machInst, 15) == 1) { 172810037SARM gem5 Developers return new Unknown64(machInst); 172910037SARM gem5 Developers } else { 173010037SARM gem5 Developers if (bits(machInst, 29)) 173110037SARM gem5 Developers return new Unknown64(machInst); 173210037SARM gem5 Developers uint8_t rmode = bits(machInst, 20, 19); 173310037SARM gem5 Developers uint8_t switchVal1 = bits(machInst, 18, 16); 173410037SARM gem5 Developers uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 173510037SARM gem5 Developers // 30:24=0011110, 21=1, 15:10=000000 173610037SARM gem5 Developers switch (switchVal1) { 173710037SARM gem5 Developers case 0x0: 173810037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 173910037SARM gem5 Developers case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 174010037SARM gem5 Developers return new FcvtFpSIntWSN(machInst, rd, rn); 174110037SARM gem5 Developers case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 174210037SARM gem5 Developers return new FcvtFpSIntWSP(machInst, rd, rn); 174310037SARM gem5 Developers case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 174410037SARM gem5 Developers return new FcvtFpSIntWSM(machInst, rd, rn); 174510037SARM gem5 Developers case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 174610037SARM gem5 Developers return new FcvtFpSIntWSZ(machInst, rd, rn); 174710037SARM gem5 Developers case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 174810037SARM gem5 Developers return new FcvtFpSIntXSN(machInst, rd, rn); 174910037SARM gem5 Developers case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 175010037SARM gem5 Developers return new FcvtFpSIntXSP(machInst, rd, rn); 175110037SARM gem5 Developers case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 175210037SARM gem5 Developers return new FcvtFpSIntXSM(machInst, rd, rn); 175310037SARM gem5 Developers case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 175410037SARM gem5 Developers return new FcvtFpSIntXSZ(machInst, rd, rn); 175510037SARM gem5 Developers case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 175610037SARM gem5 Developers return new FcvtFpSIntWDN(machInst, rd, rn); 175710037SARM gem5 Developers case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 175810037SARM gem5 Developers return new FcvtFpSIntWDP(machInst, rd, rn); 175910037SARM gem5 Developers case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 176010037SARM gem5 Developers return new FcvtFpSIntWDM(machInst, rd, rn); 176110037SARM gem5 Developers case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 176210037SARM gem5 Developers return new FcvtFpSIntWDZ(machInst, rd, rn); 176310037SARM gem5 Developers case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 176410037SARM gem5 Developers return new FcvtFpSIntXDN(machInst, rd, rn); 176510037SARM gem5 Developers case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 176610037SARM gem5 Developers return new FcvtFpSIntXDP(machInst, rd, rn); 176710037SARM gem5 Developers case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 176810037SARM gem5 Developers return new FcvtFpSIntXDM(machInst, rd, rn); 176910037SARM gem5 Developers case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 177010037SARM gem5 Developers return new FcvtFpSIntXDZ(machInst, rd, rn); 177110037SARM gem5 Developers default: 177210037SARM gem5 Developers return new Unknown64(machInst); 177310037SARM gem5 Developers } 177410037SARM gem5 Developers case 0x1: 177510037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 177610037SARM gem5 Developers case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 177710037SARM gem5 Developers return new FcvtFpUIntWSN(machInst, rd, rn); 177810037SARM gem5 Developers case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 177910037SARM gem5 Developers return new FcvtFpUIntWSP(machInst, rd, rn); 178010037SARM gem5 Developers case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 178110037SARM gem5 Developers return new FcvtFpUIntWSM(machInst, rd, rn); 178210037SARM gem5 Developers case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 178310037SARM gem5 Developers return new FcvtFpUIntWSZ(machInst, rd, rn); 178410037SARM gem5 Developers case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 178510037SARM gem5 Developers return new FcvtFpUIntXSN(machInst, rd, rn); 178610037SARM gem5 Developers case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 178710037SARM gem5 Developers return new FcvtFpUIntXSP(machInst, rd, rn); 178810037SARM gem5 Developers case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 178910037SARM gem5 Developers return new FcvtFpUIntXSM(machInst, rd, rn); 179010037SARM gem5 Developers case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 179110037SARM gem5 Developers return new FcvtFpUIntXSZ(machInst, rd, rn); 179210037SARM gem5 Developers case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 179310037SARM gem5 Developers return new FcvtFpUIntWDN(machInst, rd, rn); 179410037SARM gem5 Developers case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 179510037SARM gem5 Developers return new FcvtFpUIntWDP(machInst, rd, rn); 179610037SARM gem5 Developers case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 179710037SARM gem5 Developers return new FcvtFpUIntWDM(machInst, rd, rn); 179810037SARM gem5 Developers case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 179910037SARM gem5 Developers return new FcvtFpUIntWDZ(machInst, rd, rn); 180010037SARM gem5 Developers case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 180110037SARM gem5 Developers return new FcvtFpUIntXDN(machInst, rd, rn); 180210037SARM gem5 Developers case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 180310037SARM gem5 Developers return new FcvtFpUIntXDP(machInst, rd, rn); 180410037SARM gem5 Developers case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 180510037SARM gem5 Developers return new FcvtFpUIntXDM(machInst, rd, rn); 180610037SARM gem5 Developers case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 180710037SARM gem5 Developers return new FcvtFpUIntXDZ(machInst, rd, rn); 180810037SARM gem5 Developers default: 180910037SARM gem5 Developers return new Unknown64(machInst); 181010037SARM gem5 Developers } 181110037SARM gem5 Developers case 0x2: 181210037SARM gem5 Developers if (rmode != 0) 181310037SARM gem5 Developers return new Unknown64(machInst); 181410037SARM gem5 Developers switch (switchVal2) { 181510037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn) 181610037SARM gem5 Developers return new FcvtWSIntFpS(machInst, rd, rn); 181710037SARM gem5 Developers case 1: // SCVTF Sd = convertFromInt(Xn) 181810037SARM gem5 Developers return new FcvtXSIntFpS(machInst, rd, rn); 181910037SARM gem5 Developers case 2: // SCVTF Dd = convertFromInt(Wn) 182010037SARM gem5 Developers return new FcvtWSIntFpD(machInst, rd, rn); 182110037SARM gem5 Developers case 3: // SCVTF Dd = convertFromInt(Xn) 182210037SARM gem5 Developers return new FcvtXSIntFpD(machInst, rd, rn); 182310037SARM gem5 Developers default: 182410037SARM gem5 Developers return new Unknown64(machInst); 182510037SARM gem5 Developers } 182610037SARM gem5 Developers case 0x3: 182710037SARM gem5 Developers switch (switchVal2) { 182810037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn) 182910037SARM gem5 Developers return new FcvtWUIntFpS(machInst, rd, rn); 183010037SARM gem5 Developers case 1: // UCVTF Sd = convertFromInt(Xn) 183110037SARM gem5 Developers return new FcvtXUIntFpS(machInst, rd, rn); 183210037SARM gem5 Developers case 2: // UCVTF Dd = convertFromInt(Wn) 183310037SARM gem5 Developers return new FcvtWUIntFpD(machInst, rd, rn); 183410037SARM gem5 Developers case 3: // UCVTF Dd = convertFromInt(Xn) 183510037SARM gem5 Developers return new FcvtXUIntFpD(machInst, rd, rn); 183610037SARM gem5 Developers default: 183710037SARM gem5 Developers return new Unknown64(machInst); 183810037SARM gem5 Developers } 183910037SARM gem5 Developers case 0x4: 184010037SARM gem5 Developers if (rmode != 0) 184110037SARM gem5 Developers return new Unknown64(machInst); 184210037SARM gem5 Developers switch (switchVal2) { 184310037SARM gem5 Developers case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 184410037SARM gem5 Developers return new FcvtFpSIntWSA(machInst, rd, rn); 184510037SARM gem5 Developers case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 184610037SARM gem5 Developers return new FcvtFpSIntXSA(machInst, rd, rn); 184710037SARM gem5 Developers case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 184810037SARM gem5 Developers return new FcvtFpSIntWDA(machInst, rd, rn); 184910037SARM gem5 Developers case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 185010037SARM gem5 Developers return new FcvtFpSIntXDA(machInst, rd, rn); 185110037SARM gem5 Developers default: 185210037SARM gem5 Developers return new Unknown64(machInst); 185310037SARM gem5 Developers } 185410037SARM gem5 Developers case 0x5: 185510037SARM gem5 Developers switch (switchVal2) { 185610037SARM gem5 Developers case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 185710037SARM gem5 Developers return new FcvtFpUIntWSA(machInst, rd, rn); 185810037SARM gem5 Developers case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 185910037SARM gem5 Developers return new FcvtFpUIntXSA(machInst, rd, rn); 186010037SARM gem5 Developers case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 186110037SARM gem5 Developers return new FcvtFpUIntWDA(machInst, rd, rn); 186210037SARM gem5 Developers case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 186310037SARM gem5 Developers return new FcvtFpUIntXDA(machInst, rd, rn); 186410037SARM gem5 Developers default: 186510037SARM gem5 Developers return new Unknown64(machInst); 186610037SARM gem5 Developers } 186710037SARM gem5 Developers case 0x06: 186810037SARM gem5 Developers switch (switchVal2) { 186910037SARM gem5 Developers case 0: // FMOV Wd = Sn 187010037SARM gem5 Developers if (rmode != 0) 187110037SARM gem5 Developers return new Unknown64(machInst); 187210037SARM gem5 Developers return new FmovRegCoreW(machInst, rd, rn); 187310037SARM gem5 Developers case 3: // FMOV Xd = Dn 187410037SARM gem5 Developers if (rmode != 0) 187510037SARM gem5 Developers return new Unknown64(machInst); 187610037SARM gem5 Developers return new FmovRegCoreX(machInst, rd, rn); 187710037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 187810037SARM gem5 Developers if (rmode != 1) 187910037SARM gem5 Developers return new Unknown64(machInst); 188010037SARM gem5 Developers return new FmovURegCoreX(machInst, rd, rn); 188110037SARM gem5 Developers default: 188210037SARM gem5 Developers return new Unknown64(machInst); 188310037SARM gem5 Developers } 188410037SARM gem5 Developers break; 188510037SARM gem5 Developers case 0x07: 188610037SARM gem5 Developers switch (switchVal2) { 188710037SARM gem5 Developers case 0: // FMOV Sd = Wn 188810037SARM gem5 Developers if (rmode != 0) 188910037SARM gem5 Developers return new Unknown64(machInst); 189010037SARM gem5 Developers return new FmovCoreRegW(machInst, rd, rn); 189110037SARM gem5 Developers case 3: // FMOV Xd = Dn 189210037SARM gem5 Developers if (rmode != 0) 189310037SARM gem5 Developers return new Unknown64(machInst); 189410037SARM gem5 Developers return new FmovCoreRegX(machInst, rd, rn); 189510037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 189610037SARM gem5 Developers if (rmode != 1) 189710037SARM gem5 Developers return new Unknown64(machInst); 189810037SARM gem5 Developers return new FmovUCoreRegX(machInst, rd, rn); 189910037SARM gem5 Developers default: 190010037SARM gem5 Developers return new Unknown64(machInst); 190110037SARM gem5 Developers } 190210037SARM gem5 Developers break; 190310037SARM gem5 Developers default: // Warning! missing cases in switch statement above, that still need to be added 190410037SARM gem5 Developers return new Unknown64(machInst); 190510037SARM gem5 Developers } 190610037SARM gem5 Developers } 190712597Schunchenhsu@google.com M5_UNREACHABLE; 190810037SARM gem5 Developers case 0x1: 190910037SARM gem5 Developers { 191010037SARM gem5 Developers if (bits(machInst, 31) || 191110037SARM gem5 Developers bits(machInst, 29) || 191210037SARM gem5 Developers bits(machInst, 23)) { 191310037SARM gem5 Developers return new Unknown64(machInst); 191410037SARM gem5 Developers } 191510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 191610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 191710037SARM gem5 Developers uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 191810037SARM gem5 Developers ConditionCode cond = 191910037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 192010037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4) << 0) | 192110037SARM gem5 Developers (bits(machInst, 22) << 1); 192210037SARM gem5 Developers // 31:23=000111100, 21=1, 11:10=01 192310037SARM gem5 Developers switch (switchVal) { 192410037SARM gem5 Developers case 0x0: 192510037SARM gem5 Developers // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 192610037SARM gem5 Developers return new FCCmpRegS(machInst, rn, rm, cond, imm); 192710037SARM gem5 Developers case 0x1: 192810037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Sn,Sm) 192910037SARM gem5 Developers // else #nzcv 193010037SARM gem5 Developers return new FCCmpERegS(machInst, rn, rm, cond, imm); 193110037SARM gem5 Developers case 0x2: 193210037SARM gem5 Developers // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 193310037SARM gem5 Developers return new FCCmpRegD(machInst, rn, rm, cond, imm); 193410037SARM gem5 Developers case 0x3: 193510037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Dn,Dm) 193610037SARM gem5 Developers // else #nzcv 193710037SARM gem5 Developers return new FCCmpERegD(machInst, rn, rm, cond, imm); 193810037SARM gem5 Developers default: 193910037SARM gem5 Developers return new Unknown64(machInst); 194010037SARM gem5 Developers } 194110037SARM gem5 Developers } 194210037SARM gem5 Developers case 0x2: 194310037SARM gem5 Developers { 194410037SARM gem5 Developers if (bits(machInst, 31) || 194510037SARM gem5 Developers bits(machInst, 29) || 194610037SARM gem5 Developers bits(machInst, 23)) { 194710037SARM gem5 Developers return new Unknown64(machInst); 194810037SARM gem5 Developers } 194910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 195010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 195110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 195210037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 195310037SARM gem5 Developers (bits(machInst, 22) << 4); 195410037SARM gem5 Developers switch (switchVal) { 195510037SARM gem5 Developers case 0x00: // FMUL Sd = Sn * Sm 195610037SARM gem5 Developers return new FMulS(machInst, rd, rn, rm); 195710037SARM gem5 Developers case 0x10: // FMUL Dd = Dn * Dm 195810037SARM gem5 Developers return new FMulD(machInst, rd, rn, rm); 195910037SARM gem5 Developers case 0x01: // FDIV Sd = Sn / Sm 196010037SARM gem5 Developers return new FDivS(machInst, rd, rn, rm); 196110037SARM gem5 Developers case 0x11: // FDIV Dd = Dn / Dm 196210037SARM gem5 Developers return new FDivD(machInst, rd, rn, rm); 196310037SARM gem5 Developers case 0x02: // FADD Sd = Sn + Sm 196410037SARM gem5 Developers return new FAddS(machInst, rd, rn, rm); 196510037SARM gem5 Developers case 0x12: // FADD Dd = Dn + Dm 196610037SARM gem5 Developers return new FAddD(machInst, rd, rn, rm); 196710037SARM gem5 Developers case 0x03: // FSUB Sd = Sn - Sm 196810037SARM gem5 Developers return new FSubS(machInst, rd, rn, rm); 196910037SARM gem5 Developers case 0x13: // FSUB Dd = Dn - Dm 197010037SARM gem5 Developers return new FSubD(machInst, rd, rn, rm); 197110037SARM gem5 Developers case 0x04: // FMAX Sd = max(Sn, Sm) 197210037SARM gem5 Developers return new FMaxS(machInst, rd, rn, rm); 197310037SARM gem5 Developers case 0x14: // FMAX Dd = max(Dn, Dm) 197410037SARM gem5 Developers return new FMaxD(machInst, rd, rn, rm); 197510037SARM gem5 Developers case 0x05: // FMIN Sd = min(Sn, Sm) 197610037SARM gem5 Developers return new FMinS(machInst, rd, rn, rm); 197710037SARM gem5 Developers case 0x15: // FMIN Dd = min(Dn, Dm) 197810037SARM gem5 Developers return new FMinD(machInst, rd, rn, rm); 197910037SARM gem5 Developers case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 198010037SARM gem5 Developers return new FMaxNMS(machInst, rd, rn, rm); 198110037SARM gem5 Developers case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 198210037SARM gem5 Developers return new FMaxNMD(machInst, rd, rn, rm); 198310037SARM gem5 Developers case 0x07: // FMINNM Sd = minNum(Sn, Sm) 198410037SARM gem5 Developers return new FMinNMS(machInst, rd, rn, rm); 198510037SARM gem5 Developers case 0x17: // FMINNM Dd = minNum(Dn, Dm) 198610037SARM gem5 Developers return new FMinNMD(machInst, rd, rn, rm); 198710037SARM gem5 Developers case 0x08: // FNMUL Sd = -(Sn * Sm) 198810037SARM gem5 Developers return new FNMulS(machInst, rd, rn, rm); 198910037SARM gem5 Developers case 0x18: // FNMUL Dd = -(Dn * Dm) 199010037SARM gem5 Developers return new FNMulD(machInst, rd, rn, rm); 199110037SARM gem5 Developers default: 199210037SARM gem5 Developers return new Unknown64(machInst); 199310037SARM gem5 Developers } 199410037SARM gem5 Developers } 199510037SARM gem5 Developers case 0x3: 199610037SARM gem5 Developers { 199710037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 199810037SARM gem5 Developers return new Unknown64(machInst); 199910037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 200010037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 200110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 200210037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 200310037SARM gem5 Developers ConditionCode cond = 200410037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 200510037SARM gem5 Developers if (type == 0) // FCSEL Sd = if cond then Sn else Sm 200610037SARM gem5 Developers return new FCSelS(machInst, rd, rn, rm, cond); 200710037SARM gem5 Developers else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 200810037SARM gem5 Developers return new FCSelD(machInst, rd, rn, rm, cond); 200910037SARM gem5 Developers else 201010037SARM gem5 Developers return new Unknown64(machInst); 201110037SARM gem5 Developers } 201212595Ssiddhesh.poyarekar@gmail.com default: 201312595Ssiddhesh.poyarekar@gmail.com M5_UNREACHABLE; 201410037SARM gem5 Developers } 201510037SARM gem5 Developers } 201612597Schunchenhsu@google.com M5_UNREACHABLE; 201710037SARM gem5 Developers } 201810037SARM gem5 Developers} 201910037SARM gem5 Developers}}; 202010037SARM gem5 Developers 202110037SARM gem5 Developersoutput decoder {{ 202210037SARM gem5 Developersnamespace Aarch64 202310037SARM gem5 Developers{ 202410037SARM gem5 Developers StaticInstPtr 202510037SARM gem5 Developers decodeAdvSIMDScalar(ExtMachInst machInst) 202610037SARM gem5 Developers { 202710037SARM gem5 Developers if (bits(machInst, 24) == 1) { 202810037SARM gem5 Developers if (bits(machInst, 10) == 0) { 202910037SARM gem5 Developers return decodeNeonScIndexedElem(machInst); 203010037SARM gem5 Developers } else if (bits(machInst, 23) == 0) { 203110037SARM gem5 Developers return decodeNeonScShiftByImm(machInst); 203210037SARM gem5 Developers } 203310037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 203410037SARM gem5 Developers if (bits(machInst, 10) == 1) { 203510037SARM gem5 Developers return decodeNeonSc3Same(machInst); 203610037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 203710037SARM gem5 Developers return decodeNeonSc3Diff(machInst); 203810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 203910037SARM gem5 Developers return decodeNeonSc2RegMisc(machInst); 204010037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 204110037SARM gem5 Developers return decodeNeonScPwise(machInst); 204210037SARM gem5 Developers } else { 204310037SARM gem5 Developers return new Unknown64(machInst); 204410037SARM gem5 Developers } 204510037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0 && 204610037SARM gem5 Developers bits(machInst, 15) == 0 && 204710037SARM gem5 Developers bits(machInst, 10) == 1) { 204810037SARM gem5 Developers return decodeNeonScCopy(machInst); 204910037SARM gem5 Developers } else { 205010037SARM gem5 Developers return new Unknown64(machInst); 205110037SARM gem5 Developers } 205210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case6", machInst); 205310037SARM gem5 Developers } 205410037SARM gem5 Developers} 205510037SARM gem5 Developers}}; 205610037SARM gem5 Developers 205710037SARM gem5 Developersoutput decoder {{ 205810037SARM gem5 Developersnamespace Aarch64 205910037SARM gem5 Developers{ 206011165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 206110037SARM gem5 Developers StaticInstPtr 206210037SARM gem5 Developers decodeFpAdvSIMD(ExtMachInst machInst) 206310037SARM gem5 Developers { 206410037SARM gem5 Developers 206510037SARM gem5 Developers if (bits(machInst, 28) == 0) { 206610037SARM gem5 Developers if (bits(machInst, 31) == 0) { 206711165SRekai.GonzalezAlberquilla@arm.com return decodeAdvSIMD<DecoderFeatures>(machInst); 206810037SARM gem5 Developers } else { 206910037SARM gem5 Developers return new Unknown64(machInst); 207010037SARM gem5 Developers } 207110037SARM gem5 Developers } else if (bits(machInst, 30) == 0) { 207210037SARM gem5 Developers return decodeFp(machInst); 207310037SARM gem5 Developers } else if (bits(machInst, 31) == 0) { 207410037SARM gem5 Developers return decodeAdvSIMDScalar(machInst); 207510037SARM gem5 Developers } else { 207610037SARM gem5 Developers return new Unknown64(machInst); 207710037SARM gem5 Developers } 207810037SARM gem5 Developers } 207910037SARM gem5 Developers} 208010037SARM gem5 Developers}}; 208110037SARM gem5 Developers 208211165SRekai.GonzalezAlberquilla@arm.comlet {{ 208311165SRekai.GonzalezAlberquilla@arm.com decoder_output =''' 208411165SRekai.GonzalezAlberquilla@arm.comnamespace Aarch64 208511165SRekai.GonzalezAlberquilla@arm.com{''' 208611165SRekai.GonzalezAlberquilla@arm.com for decoderFlavour, type_dict in decoders.iteritems(): 208711165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 208811165SRekai.GonzalezAlberquilla@arm.comtemplate StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); 208911165SRekai.GonzalezAlberquilla@arm.com''' % { "df" : decoderFlavour } 209011165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 209111165SRekai.GonzalezAlberquilla@arm.com}''' 209211165SRekai.GonzalezAlberquilla@arm.com}}; 209311165SRekai.GonzalezAlberquilla@arm.com 209410037SARM gem5 Developersoutput decoder {{ 209510037SARM gem5 Developersnamespace Aarch64 209610037SARM gem5 Developers{ 209710037SARM gem5 Developers StaticInstPtr 209810037SARM gem5 Developers decodeGem5Ops(ExtMachInst machInst) 209910037SARM gem5 Developers { 210010037SARM gem5 Developers const uint32_t m5func = bits(machInst, 23, 16); 210110037SARM gem5 Developers switch (m5func) { 210212159Sandreas.sandberg@arm.com case M5OP_ARM: return new Arm(machInst); 210312159Sandreas.sandberg@arm.com case M5OP_QUIESCE: return new Quiesce(machInst); 210412159Sandreas.sandberg@arm.com case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst); 210512159Sandreas.sandberg@arm.com case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst); 210612159Sandreas.sandberg@arm.com case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst); 210712159Sandreas.sandberg@arm.com case M5OP_RPNS: return new Rpns64(machInst); 210812159Sandreas.sandberg@arm.com case M5OP_WAKE_CPU: return new WakeCPU64(machInst); 210912159Sandreas.sandberg@arm.com case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); 211012159Sandreas.sandberg@arm.com case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); 211112159Sandreas.sandberg@arm.com case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); 211212159Sandreas.sandberg@arm.com case M5OP_EXIT: return new M5exit64(machInst); 211312159Sandreas.sandberg@arm.com case M5OP_FAIL: return new M5fail64(machInst); 211412159Sandreas.sandberg@arm.com case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); 211512159Sandreas.sandberg@arm.com case M5OP_INIT_PARAM: return new Initparam64(machInst); 211612159Sandreas.sandberg@arm.com case M5OP_RESET_STATS: return new Resetstats64(machInst); 211712159Sandreas.sandberg@arm.com case M5OP_DUMP_STATS: return new Dumpstats64(machInst); 211812159Sandreas.sandberg@arm.com case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst); 211912159Sandreas.sandberg@arm.com case M5OP_CHECKPOINT: return new M5checkpoint64(machInst); 212012159Sandreas.sandberg@arm.com case M5OP_WRITE_FILE: return new M5writefile64(machInst); 212112159Sandreas.sandberg@arm.com case M5OP_READ_FILE: return new M5readfile64(machInst); 212212159Sandreas.sandberg@arm.com case M5OP_DEBUG_BREAK: return new M5break(machInst); 212312159Sandreas.sandberg@arm.com case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); 212412159Sandreas.sandberg@arm.com case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst); 212512159Sandreas.sandberg@arm.com case M5OP_PANIC: return new M5panic(machInst); 212612159Sandreas.sandberg@arm.com case M5OP_WORK_BEGIN: return new M5workbegin64(machInst); 212712159Sandreas.sandberg@arm.com case M5OP_WORK_END: return new M5workend64(machInst); 212810037SARM gem5 Developers default: return new Unknown64(machInst); 212910037SARM gem5 Developers } 213010037SARM gem5 Developers } 213110037SARM gem5 Developers} 213210037SARM gem5 Developers}}; 213310037SARM gem5 Developers 213410037SARM gem5 Developersdef format Aarch64() {{ 213510037SARM gem5 Developers decode_block = ''' 213610037SARM gem5 Developers { 213710037SARM gem5 Developers using namespace Aarch64; 213810037SARM gem5 Developers if (bits(machInst, 27) == 0x0) { 213910037SARM gem5 Developers if (bits(machInst, 28) == 0x0) 214010037SARM gem5 Developers return new Unknown64(machInst); 214110037SARM gem5 Developers else if (bits(machInst, 26) == 0) 214210037SARM gem5 Developers // bit 28:26=100 214310037SARM gem5 Developers return decodeDataProcImm(machInst); 214410037SARM gem5 Developers else 214510037SARM gem5 Developers // bit 28:26=101 214610037SARM gem5 Developers return decodeBranchExcSys(machInst); 214710037SARM gem5 Developers } else if (bits(machInst, 25) == 0) { 214810037SARM gem5 Developers // bit 27=1, 25=0 214910037SARM gem5 Developers return decodeLoadsStores(machInst); 215010037SARM gem5 Developers } else if (bits(machInst, 26) == 0) { 215110037SARM gem5 Developers // bit 27:25=101 215210037SARM gem5 Developers return decodeDataProcReg(machInst); 215310037SARM gem5 Developers } else if (bits(machInst, 24) == 1 && 215410037SARM gem5 Developers bits(machInst, 31, 28) == 0xF) { 215510037SARM gem5 Developers return decodeGem5Ops(machInst); 215610037SARM gem5 Developers } else { 215710037SARM gem5 Developers // bit 27:25=111 215811165SRekai.GonzalezAlberquilla@arm.com switch(decoderFlavour){ 215911165SRekai.GonzalezAlberquilla@arm.com default: 216011165SRekai.GonzalezAlberquilla@arm.com return decodeFpAdvSIMD<GenericDecoder>(machInst); 216111165SRekai.GonzalezAlberquilla@arm.com } 216210037SARM gem5 Developers } 216310037SARM gem5 Developers } 216410037SARM gem5 Developers ''' 216510037SARM gem5 Developers}}; 2166