aarch64.isa revision 12538
112531Sandreas.sandberg@arm.com// Copyright (c) 2011-2018 ARM Limited 210037SARM gem5 Developers// All rights reserved 310037SARM gem5 Developers// 410037SARM gem5 Developers// The license below extends only to copyright in the software and shall 510037SARM gem5 Developers// not be construed as granting a license to any other intellectual 610037SARM gem5 Developers// property including but not limited to intellectual property relating 710037SARM gem5 Developers// to a hardware implementation of the functionality of the software 810037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers// 1310037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1410037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1510037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1610037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1710037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1910037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2010037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2110037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2210037SARM gem5 Developers// this software without specific prior written permission. 2310037SARM gem5 Developers// 2410037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510037SARM gem5 Developers// 3610037SARM gem5 Developers// Authors: Gabe Black 3710037SARM gem5 Developers// Thomas Grocutt 3810037SARM gem5 Developers// Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developersoutput header {{ 4210037SARM gem5 Developersnamespace Aarch64 4310037SARM gem5 Developers{ 4410037SARM gem5 Developers StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 4510037SARM gem5 Developers StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 4610037SARM gem5 Developers StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 4710037SARM gem5 Developers StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 4810037SARM gem5 Developers 4911165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5010037SARM gem5 Developers StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 5110037SARM gem5 Developers StaticInstPtr decodeFp(ExtMachInst machInst); 5211165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 5310037SARM gem5 Developers StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 5410037SARM gem5 Developers StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 5510037SARM gem5 Developers 5610037SARM gem5 Developers StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 5710037SARM gem5 Developers} 5810037SARM gem5 Developers}}; 5910037SARM gem5 Developers 6010037SARM gem5 Developersoutput decoder {{ 6110037SARM gem5 Developersnamespace Aarch64 6210037SARM gem5 Developers{ 6310037SARM gem5 Developers StaticInstPtr 6410037SARM gem5 Developers decodeDataProcImm(ExtMachInst machInst) 6510037SARM gem5 Developers { 6610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 6710037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 6810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 6910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 7010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 7110037SARM gem5 Developers 7210037SARM gem5 Developers uint8_t opc = bits(machInst, 30, 29); 7310037SARM gem5 Developers bool sf = bits(machInst, 31); 7410037SARM gem5 Developers bool n = bits(machInst, 22); 7510037SARM gem5 Developers uint8_t immr = bits(machInst, 21, 16); 7610037SARM gem5 Developers uint8_t imms = bits(machInst, 15, 10); 7710037SARM gem5 Developers switch (bits(machInst, 25, 23)) { 7810037SARM gem5 Developers case 0x0: 7910037SARM gem5 Developers case 0x1: 8010037SARM gem5 Developers { 8110037SARM gem5 Developers uint64_t immlo = bits(machInst, 30, 29); 8210037SARM gem5 Developers uint64_t immhi = bits(machInst, 23, 5); 8310037SARM gem5 Developers uint64_t imm = (immlo << 0) | (immhi << 2); 8410037SARM gem5 Developers if (bits(machInst, 31) == 0) 8510337SAndrew.Bardsley@arm.com return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 8610037SARM gem5 Developers else 8710337SAndrew.Bardsley@arm.com return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 8810037SARM gem5 Developers sext<33>(imm << 12)); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers case 0x2: 9110037SARM gem5 Developers case 0x3: 9210037SARM gem5 Developers { 9310037SARM gem5 Developers uint32_t imm12 = bits(machInst, 21, 10); 9410037SARM gem5 Developers uint8_t shift = bits(machInst, 23, 22); 9510037SARM gem5 Developers uint32_t imm; 9610037SARM gem5 Developers if (shift == 0x0) 9710037SARM gem5 Developers imm = imm12 << 0; 9810037SARM gem5 Developers else if (shift == 0x1) 9910037SARM gem5 Developers imm = imm12 << 12; 10010037SARM gem5 Developers else 10110037SARM gem5 Developers return new Unknown64(machInst); 10210037SARM gem5 Developers switch (opc) { 10310037SARM gem5 Developers case 0x0: 10410037SARM gem5 Developers return new AddXImm(machInst, rdsp, rnsp, imm); 10510037SARM gem5 Developers case 0x1: 10610337SAndrew.Bardsley@arm.com return new AddXImmCc(machInst, rdzr, rnsp, imm); 10710037SARM gem5 Developers case 0x2: 10810037SARM gem5 Developers return new SubXImm(machInst, rdsp, rnsp, imm); 10910037SARM gem5 Developers case 0x3: 11010337SAndrew.Bardsley@arm.com return new SubXImmCc(machInst, rdzr, rnsp, imm); 11110037SARM gem5 Developers } 11210037SARM gem5 Developers } 11310037SARM gem5 Developers case 0x4: 11410037SARM gem5 Developers { 11510037SARM gem5 Developers if (!sf && n) 11610037SARM gem5 Developers return new Unknown64(machInst); 11710037SARM gem5 Developers // len = MSB(n:NOT(imms)), len < 1 is undefined. 11810037SARM gem5 Developers uint8_t len = 0; 11910037SARM gem5 Developers if (n) { 12010037SARM gem5 Developers len = 6; 12110037SARM gem5 Developers } else if (imms == 0x3f || imms == 0x3e) { 12210037SARM gem5 Developers return new Unknown64(machInst); 12310037SARM gem5 Developers } else { 12410037SARM gem5 Developers len = findMsbSet(imms ^ 0x3f); 12510037SARM gem5 Developers } 12610037SARM gem5 Developers // Generate r, s, and size. 12710037SARM gem5 Developers uint64_t r = bits(immr, len - 1, 0); 12810037SARM gem5 Developers uint64_t s = bits(imms, len - 1, 0); 12910037SARM gem5 Developers uint8_t size = 1 << len; 13010037SARM gem5 Developers if (s == size - 1) 13110037SARM gem5 Developers return new Unknown64(machInst); 13210037SARM gem5 Developers // Generate the pattern with s 1s, rotated by r, with size bits. 13310037SARM gem5 Developers uint64_t pattern = mask(s + 1); 13410037SARM gem5 Developers if (r) { 13510037SARM gem5 Developers pattern = (pattern >> r) | (pattern << (size - r)); 13610037SARM gem5 Developers pattern &= mask(size); 13710037SARM gem5 Developers } 13810037SARM gem5 Developers uint8_t width = sf ? 64 : 32; 13910037SARM gem5 Developers // Replicate that to fill up the immediate. 14010037SARM gem5 Developers for (unsigned i = 1; i < (width / size); i *= 2) 14110037SARM gem5 Developers pattern |= (pattern << (i * size)); 14210037SARM gem5 Developers uint64_t imm = pattern; 14310037SARM gem5 Developers 14410037SARM gem5 Developers switch (opc) { 14510037SARM gem5 Developers case 0x0: 14610037SARM gem5 Developers return new AndXImm(machInst, rdsp, rn, imm); 14710037SARM gem5 Developers case 0x1: 14810037SARM gem5 Developers return new OrrXImm(machInst, rdsp, rn, imm); 14910037SARM gem5 Developers case 0x2: 15010037SARM gem5 Developers return new EorXImm(machInst, rdsp, rn, imm); 15110037SARM gem5 Developers case 0x3: 15210337SAndrew.Bardsley@arm.com return new AndXImmCc(machInst, rdzr, rn, imm); 15310037SARM gem5 Developers } 15410037SARM gem5 Developers } 15510037SARM gem5 Developers case 0x5: 15610037SARM gem5 Developers { 15710037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 15810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 15910037SARM gem5 Developers uint32_t imm16 = bits(machInst, 20, 5); 16010037SARM gem5 Developers uint32_t hw = bits(machInst, 22, 21); 16110037SARM gem5 Developers switch (opc) { 16210037SARM gem5 Developers case 0x0: 16310337SAndrew.Bardsley@arm.com return new Movn(machInst, rdzr, imm16, hw * 16); 16410037SARM gem5 Developers case 0x1: 16510037SARM gem5 Developers return new Unknown64(machInst); 16610037SARM gem5 Developers case 0x2: 16710337SAndrew.Bardsley@arm.com return new Movz(machInst, rdzr, imm16, hw * 16); 16810037SARM gem5 Developers case 0x3: 16910337SAndrew.Bardsley@arm.com return new Movk(machInst, rdzr, imm16, hw * 16); 17010037SARM gem5 Developers } 17110037SARM gem5 Developers } 17210037SARM gem5 Developers case 0x6: 17310037SARM gem5 Developers if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 17410037SARM gem5 Developers return new Unknown64(machInst); 17510037SARM gem5 Developers switch (opc) { 17610037SARM gem5 Developers case 0x0: 17710337SAndrew.Bardsley@arm.com return new Sbfm64(machInst, rdzr, rn, immr, imms); 17810037SARM gem5 Developers case 0x1: 17910337SAndrew.Bardsley@arm.com return new Bfm64(machInst, rdzr, rn, immr, imms); 18010037SARM gem5 Developers case 0x2: 18110337SAndrew.Bardsley@arm.com return new Ubfm64(machInst, rdzr, rn, immr, imms); 18210037SARM gem5 Developers case 0x3: 18310037SARM gem5 Developers return new Unknown64(machInst); 18410037SARM gem5 Developers } 18510037SARM gem5 Developers case 0x7: 18610037SARM gem5 Developers { 18710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 18810037SARM gem5 Developers if (opc || bits(machInst, 21)) 18910037SARM gem5 Developers return new Unknown64(machInst); 19010037SARM gem5 Developers else 19110337SAndrew.Bardsley@arm.com return new Extr64(machInst, rdzr, rn, rm, imms); 19210037SARM gem5 Developers } 19310037SARM gem5 Developers } 19410037SARM gem5 Developers return new FailUnimplemented("Unhandled Case8", machInst); 19510037SARM gem5 Developers } 19610037SARM gem5 Developers} 19710037SARM gem5 Developers}}; 19810037SARM gem5 Developers 19910037SARM gem5 Developersoutput decoder {{ 20010037SARM gem5 Developersnamespace Aarch64 20110037SARM gem5 Developers{ 20210037SARM gem5 Developers StaticInstPtr 20310037SARM gem5 Developers decodeBranchExcSys(ExtMachInst machInst) 20410037SARM gem5 Developers { 20510037SARM gem5 Developers switch (bits(machInst, 30, 29)) { 20610037SARM gem5 Developers case 0x0: 20710037SARM gem5 Developers { 20810037SARM gem5 Developers int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 20910037SARM gem5 Developers if (bits(machInst, 31) == 0) 21010037SARM gem5 Developers return new B64(machInst, imm); 21110037SARM gem5 Developers else 21210037SARM gem5 Developers return new Bl64(machInst, imm); 21310037SARM gem5 Developers } 21410037SARM gem5 Developers case 0x1: 21510037SARM gem5 Developers { 21610037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 21710037SARM gem5 Developers if (bits(machInst, 25) == 0) { 21810037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 21910037SARM gem5 Developers if (bits(machInst, 24) == 0) 22010037SARM gem5 Developers return new Cbz64(machInst, imm, rt); 22110037SARM gem5 Developers else 22210037SARM gem5 Developers return new Cbnz64(machInst, imm, rt); 22310037SARM gem5 Developers } else { 22410037SARM gem5 Developers uint64_t bitmask = 0x1; 22510037SARM gem5 Developers bitmask <<= bits(machInst, 23, 19); 22610037SARM gem5 Developers int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 22710037SARM gem5 Developers if (bits(machInst, 31)) 22810037SARM gem5 Developers bitmask <<= 32; 22910037SARM gem5 Developers if (bits(machInst, 24) == 0) 23010037SARM gem5 Developers return new Tbz64(machInst, bitmask, imm, rt); 23110037SARM gem5 Developers else 23210037SARM gem5 Developers return new Tbnz64(machInst, bitmask, imm, rt); 23310037SARM gem5 Developers } 23410037SARM gem5 Developers } 23510037SARM gem5 Developers case 0x2: 23610037SARM gem5 Developers // bit 30:26=10101 23710037SARM gem5 Developers if (bits(machInst, 31) == 0) { 23810037SARM gem5 Developers if (bits(machInst, 25, 24) || bits(machInst, 4)) 23910037SARM gem5 Developers return new Unknown64(machInst); 24010037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 24110037SARM gem5 Developers ConditionCode condCode = 24210037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 24310037SARM gem5 Developers return new BCond64(machInst, imm, condCode); 24410037SARM gem5 Developers } else if (bits(machInst, 25, 24) == 0x0) { 24512538Sgiacomo.travaglini@arm.com 24610037SARM gem5 Developers if (bits(machInst, 4, 2)) 24710037SARM gem5 Developers return new Unknown64(machInst); 24812538Sgiacomo.travaglini@arm.com 24912538Sgiacomo.travaglini@arm.com auto imm16 = bits(machInst, 20, 5); 25010037SARM gem5 Developers uint8_t decVal = (bits(machInst, 1, 0) << 0) | 25110037SARM gem5 Developers (bits(machInst, 23, 21) << 2); 25212538Sgiacomo.travaglini@arm.com 25310037SARM gem5 Developers switch (decVal) { 25410037SARM gem5 Developers case 0x01: 25512538Sgiacomo.travaglini@arm.com return new Svc64(machInst, imm16); 25610037SARM gem5 Developers case 0x02: 25712538Sgiacomo.travaglini@arm.com return new Hvc64(machInst, imm16); 25810037SARM gem5 Developers case 0x03: 25912538Sgiacomo.travaglini@arm.com return new Smc64(machInst, imm16); 26010037SARM gem5 Developers case 0x04: 26112538Sgiacomo.travaglini@arm.com return new Brk64(machInst, imm16); 26210037SARM gem5 Developers case 0x08: 26312538Sgiacomo.travaglini@arm.com return new Hlt64(machInst, imm16); 26410037SARM gem5 Developers case 0x15: 26510037SARM gem5 Developers return new FailUnimplemented("dcps1", machInst); 26610037SARM gem5 Developers case 0x16: 26710037SARM gem5 Developers return new FailUnimplemented("dcps2", machInst); 26810037SARM gem5 Developers case 0x17: 26910037SARM gem5 Developers return new FailUnimplemented("dcps3", machInst); 27010037SARM gem5 Developers default: 27110037SARM gem5 Developers return new Unknown64(machInst); 27210037SARM gem5 Developers } 27310037SARM gem5 Developers } else if (bits(machInst, 25, 22) == 0x4) { 27410037SARM gem5 Developers // bit 31:22=1101010100 27510037SARM gem5 Developers bool l = bits(machInst, 21); 27610037SARM gem5 Developers uint8_t op0 = bits(machInst, 20, 19); 27710037SARM gem5 Developers uint8_t op1 = bits(machInst, 18, 16); 27810037SARM gem5 Developers uint8_t crn = bits(machInst, 15, 12); 27910037SARM gem5 Developers uint8_t crm = bits(machInst, 11, 8); 28010037SARM gem5 Developers uint8_t op2 = bits(machInst, 7, 5); 28110037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 28210037SARM gem5 Developers switch (op0) { 28310037SARM gem5 Developers case 0x0: 28410037SARM gem5 Developers if (rt != 0x1f || l) 28510037SARM gem5 Developers return new Unknown64(machInst); 28610037SARM gem5 Developers if (crn == 0x2 && op1 == 0x3) { 28710037SARM gem5 Developers switch (op2) { 28810037SARM gem5 Developers case 0x0: 28910037SARM gem5 Developers return new NopInst(machInst); 29010037SARM gem5 Developers case 0x1: 29110037SARM gem5 Developers return new YieldInst(machInst); 29210037SARM gem5 Developers case 0x2: 29310037SARM gem5 Developers return new WfeInst(machInst); 29410037SARM gem5 Developers case 0x3: 29510037SARM gem5 Developers return new WfiInst(machInst); 29610037SARM gem5 Developers case 0x4: 29710037SARM gem5 Developers return new SevInst(machInst); 29810037SARM gem5 Developers case 0x5: 29910037SARM gem5 Developers return new SevlInst(machInst); 30010037SARM gem5 Developers default: 30110037SARM gem5 Developers return new Unknown64(machInst); 30210037SARM gem5 Developers } 30310037SARM gem5 Developers } else if (crn == 0x3 && op1 == 0x3) { 30410037SARM gem5 Developers switch (op2) { 30510037SARM gem5 Developers case 0x2: 30610037SARM gem5 Developers return new Clrex64(machInst); 30710037SARM gem5 Developers case 0x4: 30810037SARM gem5 Developers return new Dsb64(machInst); 30910037SARM gem5 Developers case 0x5: 31010037SARM gem5 Developers return new Dmb64(machInst); 31110037SARM gem5 Developers case 0x6: 31210037SARM gem5 Developers return new Isb64(machInst); 31310037SARM gem5 Developers default: 31410037SARM gem5 Developers return new Unknown64(machInst); 31510037SARM gem5 Developers } 31610037SARM gem5 Developers } else if (crn == 0x4) { 31710037SARM gem5 Developers // MSR immediate 31810037SARM gem5 Developers switch (op1 << 3 | op2) { 31910037SARM gem5 Developers case 0x5: 32010037SARM gem5 Developers // SP 32110037SARM gem5 Developers return new MsrSP64(machInst, 32210037SARM gem5 Developers (IntRegIndex) MISCREG_SPSEL, 32310037SARM gem5 Developers INTREG_ZERO, 32410037SARM gem5 Developers crm & 0x1); 32510037SARM gem5 Developers case 0x1e: 32610037SARM gem5 Developers // DAIFSet 32710037SARM gem5 Developers return new MsrDAIFSet64( 32810037SARM gem5 Developers machInst, 32910037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 33010037SARM gem5 Developers INTREG_ZERO, 33110037SARM gem5 Developers crm); 33210037SARM gem5 Developers case 0x1f: 33310037SARM gem5 Developers // DAIFClr 33410037SARM gem5 Developers return new MsrDAIFClr64( 33510037SARM gem5 Developers machInst, 33610037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 33710037SARM gem5 Developers INTREG_ZERO, 33810037SARM gem5 Developers crm); 33910037SARM gem5 Developers default: 34010037SARM gem5 Developers return new Unknown64(machInst); 34110037SARM gem5 Developers } 34210037SARM gem5 Developers } else { 34310037SARM gem5 Developers return new Unknown64(machInst); 34410037SARM gem5 Developers } 34510037SARM gem5 Developers break; 34610037SARM gem5 Developers case 0x1: 34710037SARM gem5 Developers case 0x2: 34810037SARM gem5 Developers case 0x3: 34910037SARM gem5 Developers { 35010037SARM gem5 Developers // bit 31:22=1101010100, 20:19=11 35110037SARM gem5 Developers bool read = l; 35210037SARM gem5 Developers MiscRegIndex miscReg = 35310037SARM gem5 Developers decodeAArch64SysReg(op0, op1, crn, crm, op2); 35410037SARM gem5 Developers if (read) { 35510037SARM gem5 Developers if ((miscReg == MISCREG_DC_CIVAC_Xt) || 35610037SARM gem5 Developers (miscReg == MISCREG_DC_CVAC_Xt) || 35712359Snikos.nikoleris@arm.com (miscReg == MISCREG_DC_IVAC_Xt) || 35810037SARM gem5 Developers (miscReg == MISCREG_DC_ZVA_Xt)) { 35910037SARM gem5 Developers return new Unknown64(machInst); 36010037SARM gem5 Developers } 36110037SARM gem5 Developers } 36210037SARM gem5 Developers // Check for invalid registers 36310037SARM gem5 Developers if (miscReg == MISCREG_UNKNOWN) { 36410037SARM gem5 Developers return new Unknown64(machInst); 36510037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 36610037SARM gem5 Developers if (miscReg == MISCREG_NZCV) { 36710037SARM gem5 Developers if (read) 36810037SARM gem5 Developers return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 36910037SARM gem5 Developers else 37010037SARM gem5 Developers return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 37110037SARM gem5 Developers } 37210037SARM gem5 Developers uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 37310506SAli.Saidi@ARM.com if (read) { 37412280Sgiacomo.travaglini@arm.com StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss); 37510506SAli.Saidi@ARM.com if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 37610506SAli.Saidi@ARM.com si->setFlag(StaticInst::IsUnverifiable); 37710506SAli.Saidi@ARM.com return si; 37812280Sgiacomo.travaglini@arm.com } else { 37912359Snikos.nikoleris@arm.com switch (miscReg) { 38012359Snikos.nikoleris@arm.com case MISCREG_DC_ZVA_Xt: 38112359Snikos.nikoleris@arm.com return new Dczva(machInst, rt, miscReg, iss); 38212359Snikos.nikoleris@arm.com case MISCREG_DC_CVAU_Xt: 38312359Snikos.nikoleris@arm.com return new Dccvau(machInst, rt, miscReg, iss); 38412359Snikos.nikoleris@arm.com case MISCREG_DC_CVAC_Xt: 38512359Snikos.nikoleris@arm.com return new Dccvac(machInst, rt, miscReg, iss); 38612359Snikos.nikoleris@arm.com case MISCREG_DC_CIVAC_Xt: 38712359Snikos.nikoleris@arm.com return new Dccivac(machInst, rt, miscReg, iss); 38812359Snikos.nikoleris@arm.com case MISCREG_DC_IVAC_Xt: 38912359Snikos.nikoleris@arm.com return new Dcivac(machInst, rt, miscReg, iss); 39012359Snikos.nikoleris@arm.com default: 39112359Snikos.nikoleris@arm.com return new Msr64(machInst, miscReg, rt, iss); 39212359Snikos.nikoleris@arm.com } 39312280Sgiacomo.travaglini@arm.com } 39410037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 39510037SARM gem5 Developers std::string full_mnem = csprintf("%s %s", 39610037SARM gem5 Developers read ? "mrs" : "msr", miscRegName[miscReg]); 39710037SARM gem5 Developers return new WarnUnimplemented(read ? "mrs" : "msr", 39810037SARM gem5 Developers machInst, full_mnem); 39910037SARM gem5 Developers } else { 40010173SMitchell.Hayenga@ARM.com return new FailUnimplemented(read ? "mrs" : "msr", 40110173SMitchell.Hayenga@ARM.com machInst, 40210173SMitchell.Hayenga@ARM.com csprintf("%s %s", 40310173SMitchell.Hayenga@ARM.com read ? "mrs" : "msr", 40410173SMitchell.Hayenga@ARM.com miscRegName[miscReg])); 40510037SARM gem5 Developers } 40610037SARM gem5 Developers } 40710037SARM gem5 Developers break; 40810037SARM gem5 Developers } 40910037SARM gem5 Developers } else if (bits(machInst, 25) == 0x1) { 41010037SARM gem5 Developers uint8_t opc = bits(machInst, 24, 21); 41110037SARM gem5 Developers uint8_t op2 = bits(machInst, 20, 16); 41210037SARM gem5 Developers uint8_t op3 = bits(machInst, 15, 10); 41310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 41410037SARM gem5 Developers uint8_t op4 = bits(machInst, 4, 0); 41510037SARM gem5 Developers if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 41610037SARM gem5 Developers return new Unknown64(machInst); 41710037SARM gem5 Developers switch (opc) { 41810037SARM gem5 Developers case 0x0: 41910037SARM gem5 Developers return new Br64(machInst, rn); 42010037SARM gem5 Developers case 0x1: 42110037SARM gem5 Developers return new Blr64(machInst, rn); 42210037SARM gem5 Developers case 0x2: 42310037SARM gem5 Developers return new Ret64(machInst, rn); 42410037SARM gem5 Developers case 0x4: 42510037SARM gem5 Developers if (rn != 0x1f) 42610037SARM gem5 Developers return new Unknown64(machInst); 42710037SARM gem5 Developers return new Eret64(machInst); 42810037SARM gem5 Developers case 0x5: 42910037SARM gem5 Developers if (rn != 0x1f) 43010037SARM gem5 Developers return new Unknown64(machInst); 43110037SARM gem5 Developers return new FailUnimplemented("dret", machInst); 43210037SARM gem5 Developers } 43310037SARM gem5 Developers } 43410037SARM gem5 Developers default: 43510037SARM gem5 Developers return new Unknown64(machInst); 43610037SARM gem5 Developers } 43710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case7", machInst); 43810037SARM gem5 Developers } 43910037SARM gem5 Developers} 44010037SARM gem5 Developers}}; 44110037SARM gem5 Developers 44210037SARM gem5 Developersoutput decoder {{ 44310037SARM gem5 Developersnamespace Aarch64 44410037SARM gem5 Developers{ 44510037SARM gem5 Developers StaticInstPtr 44610037SARM gem5 Developers decodeLoadsStores(ExtMachInst machInst) 44710037SARM gem5 Developers { 44810037SARM gem5 Developers // bit 27,25=10 44910037SARM gem5 Developers switch (bits(machInst, 29, 28)) { 45010037SARM gem5 Developers case 0x0: 45110037SARM gem5 Developers if (bits(machInst, 26) == 0) { 45210037SARM gem5 Developers if (bits(machInst, 24) != 0) 45310037SARM gem5 Developers return new Unknown64(machInst); 45410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 45510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 45610037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 45710037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 45810037SARM gem5 Developers IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 45910037SARM gem5 Developers uint8_t opc = (bits(machInst, 15) << 0) | 46010037SARM gem5 Developers (bits(machInst, 23, 21) << 1); 46110037SARM gem5 Developers uint8_t size = bits(machInst, 31, 30); 46210037SARM gem5 Developers switch (opc) { 46310037SARM gem5 Developers case 0x0: 46410037SARM gem5 Developers switch (size) { 46510037SARM gem5 Developers case 0x0: 46610037SARM gem5 Developers return new STXRB64(machInst, rt, rnsp, rs); 46710037SARM gem5 Developers case 0x1: 46810037SARM gem5 Developers return new STXRH64(machInst, rt, rnsp, rs); 46910037SARM gem5 Developers case 0x2: 47010037SARM gem5 Developers return new STXRW64(machInst, rt, rnsp, rs); 47110037SARM gem5 Developers case 0x3: 47210037SARM gem5 Developers return new STXRX64(machInst, rt, rnsp, rs); 47310037SARM gem5 Developers } 47410037SARM gem5 Developers case 0x1: 47510037SARM gem5 Developers switch (size) { 47610037SARM gem5 Developers case 0x0: 47710037SARM gem5 Developers return new STLXRB64(machInst, rt, rnsp, rs); 47810037SARM gem5 Developers case 0x1: 47910037SARM gem5 Developers return new STLXRH64(machInst, rt, rnsp, rs); 48010037SARM gem5 Developers case 0x2: 48110037SARM gem5 Developers return new STLXRW64(machInst, rt, rnsp, rs); 48210037SARM gem5 Developers case 0x3: 48310037SARM gem5 Developers return new STLXRX64(machInst, rt, rnsp, rs); 48410037SARM gem5 Developers } 48510037SARM gem5 Developers case 0x2: 48610037SARM gem5 Developers switch (size) { 48710037SARM gem5 Developers case 0x0: 48810037SARM gem5 Developers case 0x1: 48910037SARM gem5 Developers return new Unknown64(machInst); 49010037SARM gem5 Developers case 0x2: 49110037SARM gem5 Developers return new STXPW64(machInst, rs, rt, rt2, rnsp); 49210037SARM gem5 Developers case 0x3: 49310037SARM gem5 Developers return new STXPX64(machInst, rs, rt, rt2, rnsp); 49410037SARM gem5 Developers } 49510037SARM gem5 Developers 49610037SARM gem5 Developers case 0x3: 49710037SARM gem5 Developers switch (size) { 49810037SARM gem5 Developers case 0x0: 49910037SARM gem5 Developers case 0x1: 50010037SARM gem5 Developers return new Unknown64(machInst); 50110037SARM gem5 Developers case 0x2: 50210037SARM gem5 Developers return new STLXPW64(machInst, rs, rt, rt2, rnsp); 50310037SARM gem5 Developers case 0x3: 50410037SARM gem5 Developers return new STLXPX64(machInst, rs, rt, rt2, rnsp); 50510037SARM gem5 Developers } 50610037SARM gem5 Developers 50710037SARM gem5 Developers case 0x4: 50810037SARM gem5 Developers switch (size) { 50910037SARM gem5 Developers case 0x0: 51010037SARM gem5 Developers return new LDXRB64(machInst, rt, rnsp, rs); 51110037SARM gem5 Developers case 0x1: 51210037SARM gem5 Developers return new LDXRH64(machInst, rt, rnsp, rs); 51310037SARM gem5 Developers case 0x2: 51410037SARM gem5 Developers return new LDXRW64(machInst, rt, rnsp, rs); 51510037SARM gem5 Developers case 0x3: 51610037SARM gem5 Developers return new LDXRX64(machInst, rt, rnsp, rs); 51710037SARM gem5 Developers } 51810037SARM gem5 Developers case 0x5: 51910037SARM gem5 Developers switch (size) { 52010037SARM gem5 Developers case 0x0: 52110037SARM gem5 Developers return new LDAXRB64(machInst, rt, rnsp, rs); 52210037SARM gem5 Developers case 0x1: 52310037SARM gem5 Developers return new LDAXRH64(machInst, rt, rnsp, rs); 52410037SARM gem5 Developers case 0x2: 52510037SARM gem5 Developers return new LDAXRW64(machInst, rt, rnsp, rs); 52610037SARM gem5 Developers case 0x3: 52710037SARM gem5 Developers return new LDAXRX64(machInst, rt, rnsp, rs); 52810037SARM gem5 Developers } 52910037SARM gem5 Developers case 0x6: 53010037SARM gem5 Developers switch (size) { 53110037SARM gem5 Developers case 0x0: 53210037SARM gem5 Developers case 0x1: 53310037SARM gem5 Developers return new Unknown64(machInst); 53410037SARM gem5 Developers case 0x2: 53510037SARM gem5 Developers return new LDXPW64(machInst, rt, rt2, rnsp); 53610037SARM gem5 Developers case 0x3: 53710037SARM gem5 Developers return new LDXPX64(machInst, rt, rt2, rnsp); 53810037SARM gem5 Developers } 53910037SARM gem5 Developers 54010037SARM gem5 Developers case 0x7: 54110037SARM gem5 Developers switch (size) { 54210037SARM gem5 Developers case 0x0: 54310037SARM gem5 Developers case 0x1: 54410037SARM gem5 Developers return new Unknown64(machInst); 54510037SARM gem5 Developers case 0x2: 54610037SARM gem5 Developers return new LDAXPW64(machInst, rt, rt2, rnsp); 54710037SARM gem5 Developers case 0x3: 54810037SARM gem5 Developers return new LDAXPX64(machInst, rt, rt2, rnsp); 54910037SARM gem5 Developers } 55010037SARM gem5 Developers 55110037SARM gem5 Developers case 0x9: 55210037SARM gem5 Developers switch (size) { 55310037SARM gem5 Developers case 0x0: 55410037SARM gem5 Developers return new STLRB64(machInst, rt, rnsp); 55510037SARM gem5 Developers case 0x1: 55610037SARM gem5 Developers return new STLRH64(machInst, rt, rnsp); 55710037SARM gem5 Developers case 0x2: 55810037SARM gem5 Developers return new STLRW64(machInst, rt, rnsp); 55910037SARM gem5 Developers case 0x3: 56010037SARM gem5 Developers return new STLRX64(machInst, rt, rnsp); 56110037SARM gem5 Developers } 56210037SARM gem5 Developers case 0xd: 56310037SARM gem5 Developers switch (size) { 56410037SARM gem5 Developers case 0x0: 56510037SARM gem5 Developers return new LDARB64(machInst, rt, rnsp); 56610037SARM gem5 Developers case 0x1: 56710037SARM gem5 Developers return new LDARH64(machInst, rt, rnsp); 56810037SARM gem5 Developers case 0x2: 56910037SARM gem5 Developers return new LDARW64(machInst, rt, rnsp); 57010037SARM gem5 Developers case 0x3: 57110037SARM gem5 Developers return new LDARX64(machInst, rt, rnsp); 57210037SARM gem5 Developers } 57310037SARM gem5 Developers default: 57410037SARM gem5 Developers return new Unknown64(machInst); 57510037SARM gem5 Developers } 57610037SARM gem5 Developers } else if (bits(machInst, 31)) { 57710037SARM gem5 Developers return new Unknown64(machInst); 57810037SARM gem5 Developers } else { 57910037SARM gem5 Developers return decodeNeonMem(machInst); 58010037SARM gem5 Developers } 58110037SARM gem5 Developers case 0x1: 58210037SARM gem5 Developers { 58310037SARM gem5 Developers if (bits(machInst, 24) != 0) 58410037SARM gem5 Developers return new Unknown64(machInst); 58510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 26) << 0) | 58610037SARM gem5 Developers (bits(machInst, 31, 30) << 1); 58710037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 58810037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 58910037SARM gem5 Developers switch (switchVal) { 59010037SARM gem5 Developers case 0x0: 59110037SARM gem5 Developers return new LDRWL64_LIT(machInst, rt, imm); 59210037SARM gem5 Developers case 0x1: 59310037SARM gem5 Developers return new LDRSFP64_LIT(machInst, rt, imm); 59410037SARM gem5 Developers case 0x2: 59510037SARM gem5 Developers return new LDRXL64_LIT(machInst, rt, imm); 59610037SARM gem5 Developers case 0x3: 59710037SARM gem5 Developers return new LDRDFP64_LIT(machInst, rt, imm); 59810037SARM gem5 Developers case 0x4: 59910037SARM gem5 Developers return new LDRSWL64_LIT(machInst, rt, imm); 60010037SARM gem5 Developers case 0x5: 60110037SARM gem5 Developers return new BigFpMemLit("ldr", machInst, rt, imm); 60210037SARM gem5 Developers case 0x6: 60310037SARM gem5 Developers return new PRFM64_LIT(machInst, rt, imm); 60410037SARM gem5 Developers default: 60510037SARM gem5 Developers return new Unknown64(machInst); 60610037SARM gem5 Developers } 60710037SARM gem5 Developers } 60810037SARM gem5 Developers case 0x2: 60910037SARM gem5 Developers { 61010037SARM gem5 Developers uint8_t opc = bits(machInst, 31, 30); 61110037SARM gem5 Developers if (opc >= 3) 61210037SARM gem5 Developers return new Unknown64(machInst); 61310037SARM gem5 Developers uint32_t size = 0; 61410037SARM gem5 Developers bool fp = bits(machInst, 26); 61510037SARM gem5 Developers bool load = bits(machInst, 22); 61610037SARM gem5 Developers if (fp) { 61710037SARM gem5 Developers size = 4 << opc; 61810037SARM gem5 Developers } else { 61910037SARM gem5 Developers if ((opc == 1) && !load) 62010037SARM gem5 Developers return new Unknown64(machInst); 62110037SARM gem5 Developers size = (opc == 0 || opc == 1) ? 4 : 8; 62210037SARM gem5 Developers } 62310037SARM gem5 Developers uint8_t type = bits(machInst, 24, 23); 62410037SARM gem5 Developers int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 62510037SARM gem5 Developers 62610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 62710037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 62810037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 62910037SARM gem5 Developers 63010037SARM gem5 Developers bool noAlloc = (type == 0); 63110037SARM gem5 Developers bool signExt = !noAlloc && !fp && opc == 1; 63210037SARM gem5 Developers PairMemOp::AddrMode mode; 63310037SARM gem5 Developers const char *mnemonic = NULL; 63410037SARM gem5 Developers switch (type) { 63510037SARM gem5 Developers case 0x0: 63610037SARM gem5 Developers case 0x2: 63710037SARM gem5 Developers mode = PairMemOp::AddrMd_Offset; 63810037SARM gem5 Developers break; 63910037SARM gem5 Developers case 0x1: 64010037SARM gem5 Developers mode = PairMemOp::AddrMd_PostIndex; 64110037SARM gem5 Developers break; 64210037SARM gem5 Developers case 0x3: 64310037SARM gem5 Developers mode = PairMemOp::AddrMd_PreIndex; 64410037SARM gem5 Developers break; 64510037SARM gem5 Developers default: 64610037SARM gem5 Developers return new Unknown64(machInst); 64710037SARM gem5 Developers } 64810037SARM gem5 Developers if (load) { 64910037SARM gem5 Developers if (noAlloc) 65010037SARM gem5 Developers mnemonic = "ldnp"; 65110037SARM gem5 Developers else if (signExt) 65210037SARM gem5 Developers mnemonic = "ldpsw"; 65310037SARM gem5 Developers else 65410037SARM gem5 Developers mnemonic = "ldp"; 65510037SARM gem5 Developers } else { 65610037SARM gem5 Developers if (noAlloc) 65710037SARM gem5 Developers mnemonic = "stnp"; 65810037SARM gem5 Developers else 65910037SARM gem5 Developers mnemonic = "stp"; 66010037SARM gem5 Developers } 66110037SARM gem5 Developers 66210037SARM gem5 Developers return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 66310037SARM gem5 Developers signExt, false, false, imm, mode, rn, rt, rt2); 66410037SARM gem5 Developers } 66510037SARM gem5 Developers // bit 29:27=111, 25=0 66610037SARM gem5 Developers case 0x3: 66710037SARM gem5 Developers { 66810037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 66910037SARM gem5 Developers (bits(machInst, 26) << 2) | 67010037SARM gem5 Developers (bits(machInst, 31, 30) << 3); 67110037SARM gem5 Developers if (bits(machInst, 24) == 1) { 67210037SARM gem5 Developers uint64_t imm12 = bits(machInst, 21, 10); 67310037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 67410037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 67510037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 67610037SARM gem5 Developers switch (switchVal) { 67710037SARM gem5 Developers case 0x00: 67810037SARM gem5 Developers return new STRB64_IMM(machInst, rt, rnsp, imm12); 67910037SARM gem5 Developers case 0x01: 68010037SARM gem5 Developers return new LDRB64_IMM(machInst, rt, rnsp, imm12); 68110037SARM gem5 Developers case 0x02: 68210037SARM gem5 Developers return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 68310037SARM gem5 Developers case 0x03: 68410037SARM gem5 Developers return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 68510037SARM gem5 Developers case 0x04: 68610037SARM gem5 Developers return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 68710037SARM gem5 Developers case 0x05: 68810037SARM gem5 Developers return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 68910037SARM gem5 Developers case 0x06: 69010037SARM gem5 Developers return new BigFpMemImm("str", machInst, false, 69110037SARM gem5 Developers rt, rnsp, imm12 << 4); 69210037SARM gem5 Developers case 0x07: 69310037SARM gem5 Developers return new BigFpMemImm("ldr", machInst, true, 69410037SARM gem5 Developers rt, rnsp, imm12 << 4); 69510037SARM gem5 Developers case 0x08: 69610037SARM gem5 Developers return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 69710037SARM gem5 Developers case 0x09: 69810037SARM gem5 Developers return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 69910037SARM gem5 Developers case 0x0a: 70010037SARM gem5 Developers return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 70110037SARM gem5 Developers case 0x0b: 70210037SARM gem5 Developers return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 70310037SARM gem5 Developers case 0x0c: 70410037SARM gem5 Developers return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 70510037SARM gem5 Developers case 0x0d: 70610037SARM gem5 Developers return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 70710037SARM gem5 Developers case 0x10: 70810037SARM gem5 Developers return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 70910037SARM gem5 Developers case 0x11: 71010037SARM gem5 Developers return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 71110037SARM gem5 Developers case 0x12: 71210037SARM gem5 Developers return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 71310037SARM gem5 Developers case 0x14: 71410037SARM gem5 Developers return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 71510037SARM gem5 Developers case 0x15: 71610037SARM gem5 Developers return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 71710037SARM gem5 Developers case 0x18: 71810037SARM gem5 Developers return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 71910037SARM gem5 Developers case 0x19: 72010037SARM gem5 Developers return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 72110037SARM gem5 Developers case 0x1a: 72210037SARM gem5 Developers return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 72310037SARM gem5 Developers case 0x1c: 72410037SARM gem5 Developers return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 72510037SARM gem5 Developers case 0x1d: 72610037SARM gem5 Developers return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 72710037SARM gem5 Developers default: 72810037SARM gem5 Developers return new Unknown64(machInst); 72910037SARM gem5 Developers } 73010037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 73110037SARM gem5 Developers if (bits(machInst, 11, 10) != 0x2) 73210037SARM gem5 Developers return new Unknown64(machInst); 73310037SARM gem5 Developers if (!bits(machInst, 14)) 73410037SARM gem5 Developers return new Unknown64(machInst); 73510037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 73610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 73710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 73810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 73910037SARM gem5 Developers ArmExtendType type = 74010037SARM gem5 Developers (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 74110037SARM gem5 Developers uint8_t s = bits(machInst, 12); 74210037SARM gem5 Developers switch (switchVal) { 74310037SARM gem5 Developers case 0x00: 74410037SARM gem5 Developers return new STRB64_REG(machInst, rt, rnsp, rm, type, 0); 74510037SARM gem5 Developers case 0x01: 74610037SARM gem5 Developers return new LDRB64_REG(machInst, rt, rnsp, rm, type, 0); 74710037SARM gem5 Developers case 0x02: 74810037SARM gem5 Developers return new LDRSBX64_REG(machInst, rt, rnsp, rm, type, 0); 74910037SARM gem5 Developers case 0x03: 75010037SARM gem5 Developers return new LDRSBW64_REG(machInst, rt, rnsp, rm, type, 0); 75110037SARM gem5 Developers case 0x04: 75210037SARM gem5 Developers return new STRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 75310037SARM gem5 Developers case 0x05: 75410037SARM gem5 Developers return new LDRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 75510037SARM gem5 Developers case 0x6: 75610037SARM gem5 Developers return new BigFpMemReg("str", machInst, false, 75710037SARM gem5 Developers rt, rnsp, rm, type, s * 4); 75810037SARM gem5 Developers case 0x7: 75910037SARM gem5 Developers return new BigFpMemReg("ldr", machInst, true, 76010037SARM gem5 Developers rt, rnsp, rm, type, s * 4); 76110037SARM gem5 Developers case 0x08: 76210037SARM gem5 Developers return new STRH64_REG(machInst, rt, rnsp, rm, type, s); 76310037SARM gem5 Developers case 0x09: 76410037SARM gem5 Developers return new LDRH64_REG(machInst, rt, rnsp, rm, type, s); 76510037SARM gem5 Developers case 0x0a: 76610037SARM gem5 Developers return new LDRSHX64_REG(machInst, rt, rnsp, rm, type, s); 76710037SARM gem5 Developers case 0x0b: 76810037SARM gem5 Developers return new LDRSHW64_REG(machInst, rt, rnsp, rm, type, s); 76910037SARM gem5 Developers case 0x0c: 77010037SARM gem5 Developers return new STRHFP64_REG(machInst, rt, rnsp, rm, type, s); 77110037SARM gem5 Developers case 0x0d: 77210037SARM gem5 Developers return new LDRHFP64_REG(machInst, rt, rnsp, rm, type, s); 77310037SARM gem5 Developers case 0x10: 77410037SARM gem5 Developers return new STRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 77510037SARM gem5 Developers case 0x11: 77610037SARM gem5 Developers return new LDRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 77710037SARM gem5 Developers case 0x12: 77810037SARM gem5 Developers return new LDRSW64_REG(machInst, rt, rnsp, rm, type, s * 2); 77910037SARM gem5 Developers case 0x14: 78010037SARM gem5 Developers return new STRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 78110037SARM gem5 Developers case 0x15: 78210037SARM gem5 Developers return new LDRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 78310037SARM gem5 Developers case 0x18: 78410037SARM gem5 Developers return new STRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 78510037SARM gem5 Developers case 0x19: 78610037SARM gem5 Developers return new LDRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 78710037SARM gem5 Developers case 0x1a: 78810037SARM gem5 Developers return new PRFM64_REG(machInst, rt, rnsp, rm, type, s * 3); 78910037SARM gem5 Developers case 0x1c: 79010037SARM gem5 Developers return new STRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 79110037SARM gem5 Developers case 0x1d: 79210037SARM gem5 Developers return new LDRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 79310037SARM gem5 Developers default: 79410037SARM gem5 Developers return new Unknown64(machInst); 79510037SARM gem5 Developers } 79610037SARM gem5 Developers } else { 79710037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0 79810037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 79910037SARM gem5 Developers case 0x0: 80010037SARM gem5 Developers { 80110037SARM gem5 Developers IntRegIndex rt = 80210037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 80310037SARM gem5 Developers IntRegIndex rn = 80410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 80510037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 80610037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 80710037SARM gem5 Developers switch (switchVal) { 80810037SARM gem5 Developers case 0x00: 80910037SARM gem5 Developers return new STURB64_IMM(machInst, rt, rnsp, imm); 81010037SARM gem5 Developers case 0x01: 81110037SARM gem5 Developers return new LDURB64_IMM(machInst, rt, rnsp, imm); 81210037SARM gem5 Developers case 0x02: 81310037SARM gem5 Developers return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 81410037SARM gem5 Developers case 0x03: 81510037SARM gem5 Developers return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 81610037SARM gem5 Developers case 0x04: 81710037SARM gem5 Developers return new STURBFP64_IMM(machInst, rt, rnsp, imm); 81810037SARM gem5 Developers case 0x05: 81910037SARM gem5 Developers return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 82010037SARM gem5 Developers case 0x06: 82110037SARM gem5 Developers return new BigFpMemImm("stur", machInst, false, 82210037SARM gem5 Developers rt, rnsp, imm); 82310037SARM gem5 Developers case 0x07: 82410037SARM gem5 Developers return new BigFpMemImm("ldur", machInst, true, 82510037SARM gem5 Developers rt, rnsp, imm); 82610037SARM gem5 Developers case 0x08: 82710037SARM gem5 Developers return new STURH64_IMM(machInst, rt, rnsp, imm); 82810037SARM gem5 Developers case 0x09: 82910037SARM gem5 Developers return new LDURH64_IMM(machInst, rt, rnsp, imm); 83010037SARM gem5 Developers case 0x0a: 83110037SARM gem5 Developers return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 83210037SARM gem5 Developers case 0x0b: 83310037SARM gem5 Developers return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 83410037SARM gem5 Developers case 0x0c: 83510037SARM gem5 Developers return new STURHFP64_IMM(machInst, rt, rnsp, imm); 83610037SARM gem5 Developers case 0x0d: 83710037SARM gem5 Developers return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 83810037SARM gem5 Developers case 0x10: 83910037SARM gem5 Developers return new STURW64_IMM(machInst, rt, rnsp, imm); 84010037SARM gem5 Developers case 0x11: 84110037SARM gem5 Developers return new LDURW64_IMM(machInst, rt, rnsp, imm); 84210037SARM gem5 Developers case 0x12: 84310037SARM gem5 Developers return new LDURSW64_IMM(machInst, rt, rnsp, imm); 84410037SARM gem5 Developers case 0x14: 84510037SARM gem5 Developers return new STURSFP64_IMM(machInst, rt, rnsp, imm); 84610037SARM gem5 Developers case 0x15: 84710037SARM gem5 Developers return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 84810037SARM gem5 Developers case 0x18: 84910037SARM gem5 Developers return new STURX64_IMM(machInst, rt, rnsp, imm); 85010037SARM gem5 Developers case 0x19: 85110037SARM gem5 Developers return new LDURX64_IMM(machInst, rt, rnsp, imm); 85210037SARM gem5 Developers case 0x1a: 85310037SARM gem5 Developers return new PRFUM64_IMM(machInst, rt, rnsp, imm); 85410037SARM gem5 Developers case 0x1c: 85510037SARM gem5 Developers return new STURDFP64_IMM(machInst, rt, rnsp, imm); 85610037SARM gem5 Developers case 0x1d: 85710037SARM gem5 Developers return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 85810037SARM gem5 Developers default: 85910037SARM gem5 Developers return new Unknown64(machInst); 86010037SARM gem5 Developers } 86110037SARM gem5 Developers } 86210037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0, 11:10=01 86310037SARM gem5 Developers case 0x1: 86410037SARM gem5 Developers { 86510037SARM gem5 Developers IntRegIndex rt = 86610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 86710037SARM gem5 Developers IntRegIndex rn = 86810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 86910037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 87010037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 87110037SARM gem5 Developers switch (switchVal) { 87210037SARM gem5 Developers case 0x00: 87310037SARM gem5 Developers return new STRB64_POST(machInst, rt, rnsp, imm); 87410037SARM gem5 Developers case 0x01: 87510037SARM gem5 Developers return new LDRB64_POST(machInst, rt, rnsp, imm); 87610037SARM gem5 Developers case 0x02: 87710037SARM gem5 Developers return new LDRSBX64_POST(machInst, rt, rnsp, imm); 87810037SARM gem5 Developers case 0x03: 87910037SARM gem5 Developers return new LDRSBW64_POST(machInst, rt, rnsp, imm); 88010037SARM gem5 Developers case 0x04: 88110037SARM gem5 Developers return new STRBFP64_POST(machInst, rt, rnsp, imm); 88210037SARM gem5 Developers case 0x05: 88310037SARM gem5 Developers return new LDRBFP64_POST(machInst, rt, rnsp, imm); 88410037SARM gem5 Developers case 0x06: 88510037SARM gem5 Developers return new BigFpMemPost("str", machInst, false, 88610037SARM gem5 Developers rt, rnsp, imm); 88710037SARM gem5 Developers case 0x07: 88810037SARM gem5 Developers return new BigFpMemPost("ldr", machInst, true, 88910037SARM gem5 Developers rt, rnsp, imm); 89010037SARM gem5 Developers case 0x08: 89110037SARM gem5 Developers return new STRH64_POST(machInst, rt, rnsp, imm); 89210037SARM gem5 Developers case 0x09: 89310037SARM gem5 Developers return new LDRH64_POST(machInst, rt, rnsp, imm); 89410037SARM gem5 Developers case 0x0a: 89510037SARM gem5 Developers return new LDRSHX64_POST(machInst, rt, rnsp, imm); 89610037SARM gem5 Developers case 0x0b: 89710037SARM gem5 Developers return new LDRSHW64_POST(machInst, rt, rnsp, imm); 89810037SARM gem5 Developers case 0x0c: 89910037SARM gem5 Developers return new STRHFP64_POST(machInst, rt, rnsp, imm); 90010037SARM gem5 Developers case 0x0d: 90110037SARM gem5 Developers return new LDRHFP64_POST(machInst, rt, rnsp, imm); 90210037SARM gem5 Developers case 0x10: 90310037SARM gem5 Developers return new STRW64_POST(machInst, rt, rnsp, imm); 90410037SARM gem5 Developers case 0x11: 90510037SARM gem5 Developers return new LDRW64_POST(machInst, rt, rnsp, imm); 90610037SARM gem5 Developers case 0x12: 90710037SARM gem5 Developers return new LDRSW64_POST(machInst, rt, rnsp, imm); 90810037SARM gem5 Developers case 0x14: 90910037SARM gem5 Developers return new STRSFP64_POST(machInst, rt, rnsp, imm); 91010037SARM gem5 Developers case 0x15: 91110037SARM gem5 Developers return new LDRSFP64_POST(machInst, rt, rnsp, imm); 91210037SARM gem5 Developers case 0x18: 91310037SARM gem5 Developers return new STRX64_POST(machInst, rt, rnsp, imm); 91410037SARM gem5 Developers case 0x19: 91510037SARM gem5 Developers return new LDRX64_POST(machInst, rt, rnsp, imm); 91610037SARM gem5 Developers case 0x1c: 91710037SARM gem5 Developers return new STRDFP64_POST(machInst, rt, rnsp, imm); 91810037SARM gem5 Developers case 0x1d: 91910037SARM gem5 Developers return new LDRDFP64_POST(machInst, rt, rnsp, imm); 92010037SARM gem5 Developers default: 92110037SARM gem5 Developers return new Unknown64(machInst); 92210037SARM gem5 Developers } 92310037SARM gem5 Developers } 92410037SARM gem5 Developers case 0x2: 92510037SARM gem5 Developers { 92610037SARM gem5 Developers IntRegIndex rt = 92710037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 92810037SARM gem5 Developers IntRegIndex rn = 92910037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 93010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 93110037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 93210037SARM gem5 Developers switch (switchVal) { 93310037SARM gem5 Developers case 0x00: 93410037SARM gem5 Developers return new STTRB64_IMM(machInst, rt, rnsp, imm); 93510037SARM gem5 Developers case 0x01: 93610037SARM gem5 Developers return new LDTRB64_IMM(machInst, rt, rnsp, imm); 93710037SARM gem5 Developers case 0x02: 93810037SARM gem5 Developers return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 93910037SARM gem5 Developers case 0x03: 94010037SARM gem5 Developers return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 94110037SARM gem5 Developers case 0x08: 94210037SARM gem5 Developers return new STTRH64_IMM(machInst, rt, rnsp, imm); 94310037SARM gem5 Developers case 0x09: 94410037SARM gem5 Developers return new LDTRH64_IMM(machInst, rt, rnsp, imm); 94510037SARM gem5 Developers case 0x0a: 94610037SARM gem5 Developers return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 94710037SARM gem5 Developers case 0x0b: 94810037SARM gem5 Developers return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 94910037SARM gem5 Developers case 0x10: 95010037SARM gem5 Developers return new STTRW64_IMM(machInst, rt, rnsp, imm); 95110037SARM gem5 Developers case 0x11: 95210037SARM gem5 Developers return new LDTRW64_IMM(machInst, rt, rnsp, imm); 95310037SARM gem5 Developers case 0x12: 95410037SARM gem5 Developers return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 95510037SARM gem5 Developers case 0x18: 95610037SARM gem5 Developers return new STTRX64_IMM(machInst, rt, rnsp, imm); 95710037SARM gem5 Developers case 0x19: 95810037SARM gem5 Developers return new LDTRX64_IMM(machInst, rt, rnsp, imm); 95910037SARM gem5 Developers default: 96010037SARM gem5 Developers return new Unknown64(machInst); 96110037SARM gem5 Developers } 96210037SARM gem5 Developers } 96310037SARM gem5 Developers case 0x3: 96410037SARM gem5 Developers { 96510037SARM gem5 Developers IntRegIndex rt = 96610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 96710037SARM gem5 Developers IntRegIndex rn = 96810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 96910037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 97010037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 97110037SARM gem5 Developers switch (switchVal) { 97210037SARM gem5 Developers case 0x00: 97310037SARM gem5 Developers return new STRB64_PRE(machInst, rt, rnsp, imm); 97410037SARM gem5 Developers case 0x01: 97510037SARM gem5 Developers return new LDRB64_PRE(machInst, rt, rnsp, imm); 97610037SARM gem5 Developers case 0x02: 97710037SARM gem5 Developers return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 97810037SARM gem5 Developers case 0x03: 97910037SARM gem5 Developers return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 98010037SARM gem5 Developers case 0x04: 98110037SARM gem5 Developers return new STRBFP64_PRE(machInst, rt, rnsp, imm); 98210037SARM gem5 Developers case 0x05: 98310037SARM gem5 Developers return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 98410037SARM gem5 Developers case 0x06: 98510037SARM gem5 Developers return new BigFpMemPre("str", machInst, false, 98610037SARM gem5 Developers rt, rnsp, imm); 98710037SARM gem5 Developers case 0x07: 98810037SARM gem5 Developers return new BigFpMemPre("ldr", machInst, true, 98910037SARM gem5 Developers rt, rnsp, imm); 99010037SARM gem5 Developers case 0x08: 99110037SARM gem5 Developers return new STRH64_PRE(machInst, rt, rnsp, imm); 99210037SARM gem5 Developers case 0x09: 99310037SARM gem5 Developers return new LDRH64_PRE(machInst, rt, rnsp, imm); 99410037SARM gem5 Developers case 0x0a: 99510037SARM gem5 Developers return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 99610037SARM gem5 Developers case 0x0b: 99710037SARM gem5 Developers return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 99810037SARM gem5 Developers case 0x0c: 99910037SARM gem5 Developers return new STRHFP64_PRE(machInst, rt, rnsp, imm); 100010037SARM gem5 Developers case 0x0d: 100110037SARM gem5 Developers return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 100210037SARM gem5 Developers case 0x10: 100310037SARM gem5 Developers return new STRW64_PRE(machInst, rt, rnsp, imm); 100410037SARM gem5 Developers case 0x11: 100510037SARM gem5 Developers return new LDRW64_PRE(machInst, rt, rnsp, imm); 100610037SARM gem5 Developers case 0x12: 100710037SARM gem5 Developers return new LDRSW64_PRE(machInst, rt, rnsp, imm); 100810037SARM gem5 Developers case 0x14: 100910037SARM gem5 Developers return new STRSFP64_PRE(machInst, rt, rnsp, imm); 101010037SARM gem5 Developers case 0x15: 101110037SARM gem5 Developers return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 101210037SARM gem5 Developers case 0x18: 101310037SARM gem5 Developers return new STRX64_PRE(machInst, rt, rnsp, imm); 101410037SARM gem5 Developers case 0x19: 101510037SARM gem5 Developers return new LDRX64_PRE(machInst, rt, rnsp, imm); 101610037SARM gem5 Developers case 0x1c: 101710037SARM gem5 Developers return new STRDFP64_PRE(machInst, rt, rnsp, imm); 101810037SARM gem5 Developers case 0x1d: 101910037SARM gem5 Developers return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 102010037SARM gem5 Developers default: 102110037SARM gem5 Developers return new Unknown64(machInst); 102210037SARM gem5 Developers } 102310037SARM gem5 Developers } 102410037SARM gem5 Developers } 102510037SARM gem5 Developers } 102610037SARM gem5 Developers } 102710037SARM gem5 Developers } 102810037SARM gem5 Developers return new FailUnimplemented("Unhandled Case1", machInst); 102910037SARM gem5 Developers } 103010037SARM gem5 Developers} 103110037SARM gem5 Developers}}; 103210037SARM gem5 Developers 103310037SARM gem5 Developersoutput decoder {{ 103410037SARM gem5 Developersnamespace Aarch64 103510037SARM gem5 Developers{ 103610037SARM gem5 Developers StaticInstPtr 103710037SARM gem5 Developers decodeDataProcReg(ExtMachInst machInst) 103810037SARM gem5 Developers { 103910037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 28) << 1) | 104010037SARM gem5 Developers (bits(machInst, 24) << 0); 104110037SARM gem5 Developers switch (switchVal) { 104210037SARM gem5 Developers case 0x0: 104310037SARM gem5 Developers { 104410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 21) << 0) | 104510037SARM gem5 Developers (bits(machInst, 30, 29) << 1); 104610037SARM gem5 Developers ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 104710037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 104810037SARM gem5 Developers bool sf = bits(machInst, 31); 104910037SARM gem5 Developers if (!sf && (imm6 & 0x20)) 105010037SARM gem5 Developers return new Unknown64(machInst); 105110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 105210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 105310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 105410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 105510037SARM gem5 Developers 105610037SARM gem5 Developers switch (switchVal) { 105710037SARM gem5 Developers case 0x0: 105810337SAndrew.Bardsley@arm.com return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 105910037SARM gem5 Developers case 0x1: 106010337SAndrew.Bardsley@arm.com return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 106110037SARM gem5 Developers case 0x2: 106210337SAndrew.Bardsley@arm.com return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 106310037SARM gem5 Developers case 0x3: 106410337SAndrew.Bardsley@arm.com return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 106510037SARM gem5 Developers case 0x4: 106610337SAndrew.Bardsley@arm.com return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 106710037SARM gem5 Developers case 0x5: 106810337SAndrew.Bardsley@arm.com return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 106910037SARM gem5 Developers case 0x6: 107010337SAndrew.Bardsley@arm.com return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 107110037SARM gem5 Developers case 0x7: 107210337SAndrew.Bardsley@arm.com return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 107310037SARM gem5 Developers } 107410037SARM gem5 Developers } 107510037SARM gem5 Developers case 0x1: 107610037SARM gem5 Developers { 107710037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 107810037SARM gem5 Developers if (bits(machInst, 21) == 0) { 107910037SARM gem5 Developers ArmShiftType type = 108010037SARM gem5 Developers (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 108110037SARM gem5 Developers if (type == ROR) 108210037SARM gem5 Developers return new Unknown64(machInst); 108310037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 108410037SARM gem5 Developers if (!bits(machInst, 31) && bits(imm6, 5)) 108510037SARM gem5 Developers return new Unknown64(machInst); 108610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 108710337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 108810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 108910037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 109010037SARM gem5 Developers switch (switchVal) { 109110037SARM gem5 Developers case 0x0: 109210337SAndrew.Bardsley@arm.com return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 109310037SARM gem5 Developers case 0x1: 109410337SAndrew.Bardsley@arm.com return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 109510037SARM gem5 Developers case 0x2: 109610337SAndrew.Bardsley@arm.com return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 109710037SARM gem5 Developers case 0x3: 109810337SAndrew.Bardsley@arm.com return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 109910037SARM gem5 Developers } 110010037SARM gem5 Developers } else { 110110037SARM gem5 Developers if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 110210037SARM gem5 Developers return new Unknown64(machInst); 110310037SARM gem5 Developers ArmExtendType type = 110410037SARM gem5 Developers (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 110510037SARM gem5 Developers uint8_t imm3 = bits(machInst, 12, 10); 110610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 110710037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 110810337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 110910037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 111010037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 111110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 111210037SARM gem5 Developers 111310037SARM gem5 Developers switch (switchVal) { 111410037SARM gem5 Developers case 0x0: 111510037SARM gem5 Developers return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 111610037SARM gem5 Developers case 0x1: 111710337SAndrew.Bardsley@arm.com return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 111810037SARM gem5 Developers case 0x2: 111910037SARM gem5 Developers return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 112010037SARM gem5 Developers case 0x3: 112110337SAndrew.Bardsley@arm.com return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 112210037SARM gem5 Developers } 112310037SARM gem5 Developers } 112410037SARM gem5 Developers } 112510037SARM gem5 Developers case 0x2: 112610037SARM gem5 Developers { 112710037SARM gem5 Developers if (bits(machInst, 21) == 1) 112810037SARM gem5 Developers return new Unknown64(machInst); 112910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 113010337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 113110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 113210037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 113310037SARM gem5 Developers switch (bits(machInst, 23, 22)) { 113410037SARM gem5 Developers case 0x0: 113510037SARM gem5 Developers { 113610037SARM gem5 Developers if (bits(machInst, 15, 10)) 113710037SARM gem5 Developers return new Unknown64(machInst); 113810037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 113910037SARM gem5 Developers switch (switchVal) { 114010037SARM gem5 Developers case 0x0: 114110337SAndrew.Bardsley@arm.com return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 114210037SARM gem5 Developers case 0x1: 114310337SAndrew.Bardsley@arm.com return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 114410037SARM gem5 Developers case 0x2: 114510337SAndrew.Bardsley@arm.com return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 114610037SARM gem5 Developers case 0x3: 114710337SAndrew.Bardsley@arm.com return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 114810037SARM gem5 Developers } 114910037SARM gem5 Developers } 115010037SARM gem5 Developers case 0x1: 115110037SARM gem5 Developers { 115210037SARM gem5 Developers if ((bits(machInst, 4) == 1) || 115310037SARM gem5 Developers (bits(machInst, 10) == 1) || 115410037SARM gem5 Developers (bits(machInst, 29) == 0)) { 115510037SARM gem5 Developers return new Unknown64(machInst); 115610037SARM gem5 Developers } 115710037SARM gem5 Developers ConditionCode cond = 115810037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 115910037SARM gem5 Developers uint8_t flags = bits(machInst, 3, 0); 116010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 116110037SARM gem5 Developers if (bits(machInst, 11) == 0) { 116210037SARM gem5 Developers IntRegIndex rm = 116310037SARM gem5 Developers (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 116410037SARM gem5 Developers if (bits(machInst, 30) == 0) { 116510037SARM gem5 Developers return new CcmnReg64(machInst, rn, rm, cond, flags); 116610037SARM gem5 Developers } else { 116710037SARM gem5 Developers return new CcmpReg64(machInst, rn, rm, cond, flags); 116810037SARM gem5 Developers } 116910037SARM gem5 Developers } else { 117010037SARM gem5 Developers uint8_t imm5 = bits(machInst, 20, 16); 117110037SARM gem5 Developers if (bits(machInst, 30) == 0) { 117210037SARM gem5 Developers return new CcmnImm64(machInst, rn, imm5, cond, flags); 117310037SARM gem5 Developers } else { 117410037SARM gem5 Developers return new CcmpImm64(machInst, rn, imm5, cond, flags); 117510037SARM gem5 Developers } 117610037SARM gem5 Developers } 117710037SARM gem5 Developers } 117810037SARM gem5 Developers case 0x2: 117910037SARM gem5 Developers { 118010037SARM gem5 Developers if (bits(machInst, 29) == 1 || 118110037SARM gem5 Developers bits(machInst, 11) == 1) { 118210037SARM gem5 Developers return new Unknown64(machInst); 118310037SARM gem5 Developers } 118410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 10) << 0) | 118510037SARM gem5 Developers (bits(machInst, 30) << 1); 118610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 118710337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 118810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 118910037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 119010037SARM gem5 Developers ConditionCode cond = 119110037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 119210037SARM gem5 Developers switch (switchVal) { 119310037SARM gem5 Developers case 0x0: 119410337SAndrew.Bardsley@arm.com return new Csel64(machInst, rdzr, rn, rm, cond); 119510037SARM gem5 Developers case 0x1: 119610337SAndrew.Bardsley@arm.com return new Csinc64(machInst, rdzr, rn, rm, cond); 119710037SARM gem5 Developers case 0x2: 119810337SAndrew.Bardsley@arm.com return new Csinv64(machInst, rdzr, rn, rm, cond); 119910037SARM gem5 Developers case 0x3: 120010337SAndrew.Bardsley@arm.com return new Csneg64(machInst, rdzr, rn, rm, cond); 120110037SARM gem5 Developers } 120210037SARM gem5 Developers } 120310037SARM gem5 Developers case 0x3: 120410037SARM gem5 Developers if (bits(machInst, 30) == 0) { 120510037SARM gem5 Developers if (bits(machInst, 29) != 0) 120610037SARM gem5 Developers return new Unknown64(machInst); 120710037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 120810037SARM gem5 Developers switch (switchVal) { 120910037SARM gem5 Developers case 0x2: 121010337SAndrew.Bardsley@arm.com return new Udiv64(machInst, rdzr, rn, rm); 121110037SARM gem5 Developers case 0x3: 121210337SAndrew.Bardsley@arm.com return new Sdiv64(machInst, rdzr, rn, rm); 121310037SARM gem5 Developers case 0x8: 121410337SAndrew.Bardsley@arm.com return new Lslv64(machInst, rdzr, rn, rm); 121510037SARM gem5 Developers case 0x9: 121610337SAndrew.Bardsley@arm.com return new Lsrv64(machInst, rdzr, rn, rm); 121710037SARM gem5 Developers case 0xa: 121810337SAndrew.Bardsley@arm.com return new Asrv64(machInst, rdzr, rn, rm); 121910037SARM gem5 Developers case 0xb: 122010337SAndrew.Bardsley@arm.com return new Rorv64(machInst, rdzr, rn, rm); 122112258Sgiacomo.travaglini@arm.com case 0x10: 122212258Sgiacomo.travaglini@arm.com return new Crc32b64(machInst, rdzr, rn, rm); 122312258Sgiacomo.travaglini@arm.com case 0x11: 122412258Sgiacomo.travaglini@arm.com return new Crc32h64(machInst, rdzr, rn, rm); 122512258Sgiacomo.travaglini@arm.com case 0x12: 122612258Sgiacomo.travaglini@arm.com return new Crc32w64(machInst, rdzr, rn, rm); 122712258Sgiacomo.travaglini@arm.com case 0x13: 122812258Sgiacomo.travaglini@arm.com return new Crc32x64(machInst, rdzr, rn, rm); 122912258Sgiacomo.travaglini@arm.com case 0x14: 123012258Sgiacomo.travaglini@arm.com return new Crc32cb64(machInst, rdzr, rn, rm); 123112258Sgiacomo.travaglini@arm.com case 0x15: 123212258Sgiacomo.travaglini@arm.com return new Crc32ch64(machInst, rdzr, rn, rm); 123312258Sgiacomo.travaglini@arm.com case 0x16: 123412258Sgiacomo.travaglini@arm.com return new Crc32cw64(machInst, rdzr, rn, rm); 123512258Sgiacomo.travaglini@arm.com case 0x17: 123612258Sgiacomo.travaglini@arm.com return new Crc32cx64(machInst, rdzr, rn, rm); 123710037SARM gem5 Developers default: 123810037SARM gem5 Developers return new Unknown64(machInst); 123910037SARM gem5 Developers } 124010037SARM gem5 Developers } else { 124110037SARM gem5 Developers if (bits(machInst, 20, 16) != 0 || 124210037SARM gem5 Developers bits(machInst, 29) != 0) { 124310037SARM gem5 Developers return new Unknown64(machInst); 124410037SARM gem5 Developers } 124510037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 124610037SARM gem5 Developers switch (switchVal) { 124710037SARM gem5 Developers case 0x0: 124810337SAndrew.Bardsley@arm.com return new Rbit64(machInst, rdzr, rn); 124910037SARM gem5 Developers case 0x1: 125010337SAndrew.Bardsley@arm.com return new Rev1664(machInst, rdzr, rn); 125110037SARM gem5 Developers case 0x2: 125210037SARM gem5 Developers if (bits(machInst, 31) == 0) 125310337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 125410037SARM gem5 Developers else 125510337SAndrew.Bardsley@arm.com return new Rev3264(machInst, rdzr, rn); 125610037SARM gem5 Developers case 0x3: 125710037SARM gem5 Developers if (bits(machInst, 31) != 1) 125810037SARM gem5 Developers return new Unknown64(machInst); 125910337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 126010037SARM gem5 Developers case 0x4: 126110337SAndrew.Bardsley@arm.com return new Clz64(machInst, rdzr, rn); 126210037SARM gem5 Developers case 0x5: 126310337SAndrew.Bardsley@arm.com return new Cls64(machInst, rdzr, rn); 126410037SARM gem5 Developers } 126510037SARM gem5 Developers } 126610037SARM gem5 Developers } 126710037SARM gem5 Developers } 126810037SARM gem5 Developers case 0x3: 126910037SARM gem5 Developers { 127010037SARM gem5 Developers if (bits(machInst, 30, 29) != 0x0 || 127110037SARM gem5 Developers (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 127210037SARM gem5 Developers return new Unknown64(machInst); 127310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 127410337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 127510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 127610037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 127710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 127810037SARM gem5 Developers switch (bits(machInst, 23, 21)) { 127910037SARM gem5 Developers case 0x0: 128010037SARM gem5 Developers if (bits(machInst, 15) == 0) 128110337SAndrew.Bardsley@arm.com return new Madd64(machInst, rdzr, ra, rn, rm); 128210037SARM gem5 Developers else 128310337SAndrew.Bardsley@arm.com return new Msub64(machInst, rdzr, ra, rn, rm); 128410037SARM gem5 Developers case 0x1: 128510037SARM gem5 Developers if (bits(machInst, 15) == 0) 128610337SAndrew.Bardsley@arm.com return new Smaddl64(machInst, rdzr, ra, rn, rm); 128710037SARM gem5 Developers else 128810337SAndrew.Bardsley@arm.com return new Smsubl64(machInst, rdzr, ra, rn, rm); 128910037SARM gem5 Developers case 0x2: 129010037SARM gem5 Developers if (bits(machInst, 15) != 0) 129110037SARM gem5 Developers return new Unknown64(machInst); 129210337SAndrew.Bardsley@arm.com return new Smulh64(machInst, rdzr, rn, rm); 129310037SARM gem5 Developers case 0x5: 129410037SARM gem5 Developers if (bits(machInst, 15) == 0) 129510337SAndrew.Bardsley@arm.com return new Umaddl64(machInst, rdzr, ra, rn, rm); 129610037SARM gem5 Developers else 129710337SAndrew.Bardsley@arm.com return new Umsubl64(machInst, rdzr, ra, rn, rm); 129810037SARM gem5 Developers case 0x6: 129910037SARM gem5 Developers if (bits(machInst, 15) != 0) 130010037SARM gem5 Developers return new Unknown64(machInst); 130110337SAndrew.Bardsley@arm.com return new Umulh64(machInst, rdzr, rn, rm); 130210037SARM gem5 Developers default: 130310037SARM gem5 Developers return new Unknown64(machInst); 130410037SARM gem5 Developers } 130510037SARM gem5 Developers } 130610037SARM gem5 Developers } 130710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case2", machInst); 130810037SARM gem5 Developers } 130910037SARM gem5 Developers} 131010037SARM gem5 Developers}}; 131110037SARM gem5 Developers 131210037SARM gem5 Developersoutput decoder {{ 131310037SARM gem5 Developersnamespace Aarch64 131410037SARM gem5 Developers{ 131511165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 131610037SARM gem5 Developers StaticInstPtr 131710037SARM gem5 Developers decodeAdvSIMD(ExtMachInst machInst) 131810037SARM gem5 Developers { 131910037SARM gem5 Developers if (bits(machInst, 24) == 1) { 132010037SARM gem5 Developers if (bits(machInst, 10) == 0) { 132111165SRekai.GonzalezAlberquilla@arm.com return decodeNeonIndexedElem<DecoderFeatures>(machInst); 132210037SARM gem5 Developers } else if (bits(machInst, 23) == 1) { 132310037SARM gem5 Developers return new Unknown64(machInst); 132410037SARM gem5 Developers } else { 132510037SARM gem5 Developers if (bits(machInst, 22, 19)) { 132610037SARM gem5 Developers return decodeNeonShiftByImm(machInst); 132710037SARM gem5 Developers } else { 132810037SARM gem5 Developers return decodeNeonModImm(machInst); 132910037SARM gem5 Developers } 133010037SARM gem5 Developers } 133110037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 133210037SARM gem5 Developers if (bits(machInst, 10) == 1) { 133311165SRekai.GonzalezAlberquilla@arm.com return decodeNeon3Same<DecoderFeatures>(machInst); 133410037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 133510037SARM gem5 Developers return decodeNeon3Diff(machInst); 133610037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 133710037SARM gem5 Developers return decodeNeon2RegMisc(machInst); 133810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 133910037SARM gem5 Developers return decodeNeonAcrossLanes(machInst); 134010037SARM gem5 Developers } else { 134110037SARM gem5 Developers return new Unknown64(machInst); 134210037SARM gem5 Developers } 134310037SARM gem5 Developers } else if (bits(machInst, 24) || 134410037SARM gem5 Developers bits(machInst, 21) || 134510037SARM gem5 Developers bits(machInst, 15)) { 134610037SARM gem5 Developers return new Unknown64(machInst); 134710037SARM gem5 Developers } else if (bits(machInst, 10) == 1) { 134810037SARM gem5 Developers if (bits(machInst, 23, 22)) 134910037SARM gem5 Developers return new Unknown64(machInst); 135010037SARM gem5 Developers return decodeNeonCopy(machInst); 135110037SARM gem5 Developers } else if (bits(machInst, 29) == 1) { 135210037SARM gem5 Developers return decodeNeonExt(machInst); 135310037SARM gem5 Developers } else if (bits(machInst, 11) == 1) { 135410037SARM gem5 Developers return decodeNeonZipUzpTrn(machInst); 135510037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0x0) { 135610037SARM gem5 Developers return decodeNeonTblTbx(machInst); 135710037SARM gem5 Developers } else { 135810037SARM gem5 Developers return new Unknown64(machInst); 135910037SARM gem5 Developers } 136010037SARM gem5 Developers return new FailUnimplemented("Unhandled Case3", machInst); 136110037SARM gem5 Developers } 136210037SARM gem5 Developers} 136310037SARM gem5 Developers}}; 136410037SARM gem5 Developers 136510037SARM gem5 Developers 136610037SARM gem5 Developersoutput decoder {{ 136710037SARM gem5 Developersnamespace Aarch64 136810037SARM gem5 Developers{ 136910037SARM gem5 Developers StaticInstPtr 137010037SARM gem5 Developers // bit 30=0, 28:25=1111 137110037SARM gem5 Developers decodeFp(ExtMachInst machInst) 137210037SARM gem5 Developers { 137310037SARM gem5 Developers if (bits(machInst, 24) == 1) { 137410037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 137510037SARM gem5 Developers return new Unknown64(machInst); 137610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 137710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 137810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 137910037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 138010037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 138110037SARM gem5 Developers (bits(machInst, 15) << 0); 138210037SARM gem5 Developers switch (switchVal) { 138310037SARM gem5 Developers case 0x0: // FMADD Sd = Sa + Sn*Sm 138410037SARM gem5 Developers return new FMAddS(machInst, rd, rn, rm, ra); 138510037SARM gem5 Developers case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 138610037SARM gem5 Developers return new FMSubS(machInst, rd, rn, rm, ra); 138710037SARM gem5 Developers case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 138810037SARM gem5 Developers return new FNMAddS(machInst, rd, rn, rm, ra); 138910037SARM gem5 Developers case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 139010037SARM gem5 Developers return new FNMSubS(machInst, rd, rn, rm, ra); 139110037SARM gem5 Developers case 0x4: // FMADD Dd = Da + Dn*Dm 139210037SARM gem5 Developers return new FMAddD(machInst, rd, rn, rm, ra); 139310037SARM gem5 Developers case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 139410037SARM gem5 Developers return new FMSubD(machInst, rd, rn, rm, ra); 139510037SARM gem5 Developers case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 139610037SARM gem5 Developers return new FNMAddD(machInst, rd, rn, rm, ra); 139710037SARM gem5 Developers case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 139810037SARM gem5 Developers return new FNMSubD(machInst, rd, rn, rm, ra); 139910037SARM gem5 Developers default: 140010037SARM gem5 Developers return new Unknown64(machInst); 140110037SARM gem5 Developers } 140210037SARM gem5 Developers } else if (bits(machInst, 21) == 0) { 140310037SARM gem5 Developers bool s = bits(machInst, 29); 140410037SARM gem5 Developers if (s) 140510037SARM gem5 Developers return new Unknown64(machInst); 140610037SARM gem5 Developers uint8_t switchVal = bits(machInst, 20, 16); 140710037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 140810037SARM gem5 Developers uint8_t scale = bits(machInst, 15, 10); 140910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 141010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 141110037SARM gem5 Developers if (bits(machInst, 18, 17) == 3 && scale != 0) 141210037SARM gem5 Developers return new Unknown64(machInst); 141310037SARM gem5 Developers // 30:24=0011110, 21=0 141410037SARM gem5 Developers switch (switchVal) { 141510037SARM gem5 Developers case 0x00: 141610037SARM gem5 Developers return new FailUnimplemented("fcvtns", machInst); 141710037SARM gem5 Developers case 0x01: 141810037SARM gem5 Developers return new FailUnimplemented("fcvtnu", machInst); 141910037SARM gem5 Developers case 0x02: 142010037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 142110037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 142210037SARM gem5 Developers return new FcvtSFixedFpSW(machInst, rd, rn, scale); 142310037SARM gem5 Developers case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 142410037SARM gem5 Developers return new FcvtSFixedFpDW(machInst, rd, rn, scale); 142510037SARM gem5 Developers case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 142610037SARM gem5 Developers return new FcvtSFixedFpSX(machInst, rd, rn, scale); 142710037SARM gem5 Developers case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 142810037SARM gem5 Developers return new FcvtSFixedFpDX(machInst, rd, rn, scale); 142910037SARM gem5 Developers default: 143010037SARM gem5 Developers return new Unknown64(machInst); 143110037SARM gem5 Developers } 143210037SARM gem5 Developers case 0x03: 143310037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 143410037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 143510037SARM gem5 Developers return new FcvtUFixedFpSW(machInst, rd, rn, scale); 143610037SARM gem5 Developers case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 143710037SARM gem5 Developers return new FcvtUFixedFpDW(machInst, rd, rn, scale); 143810037SARM gem5 Developers case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 143910037SARM gem5 Developers return new FcvtUFixedFpSX(machInst, rd, rn, scale); 144010037SARM gem5 Developers case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 144110037SARM gem5 Developers return new FcvtUFixedFpDX(machInst, rd, rn, scale); 144210037SARM gem5 Developers default: 144310037SARM gem5 Developers return new Unknown64(machInst); 144410037SARM gem5 Developers } 144510037SARM gem5 Developers case 0x04: 144610037SARM gem5 Developers return new FailUnimplemented("fcvtas", machInst); 144710037SARM gem5 Developers case 0x05: 144810037SARM gem5 Developers return new FailUnimplemented("fcvtau", machInst); 144910037SARM gem5 Developers case 0x08: 145010037SARM gem5 Developers return new FailUnimplemented("fcvtps", machInst); 145110037SARM gem5 Developers case 0x09: 145210037SARM gem5 Developers return new FailUnimplemented("fcvtpu", machInst); 145310037SARM gem5 Developers case 0x0e: 145410037SARM gem5 Developers return new FailUnimplemented("fmov elem. to 64", machInst); 145510037SARM gem5 Developers case 0x0f: 145610037SARM gem5 Developers return new FailUnimplemented("fmov 64 bit", machInst); 145710037SARM gem5 Developers case 0x10: 145810037SARM gem5 Developers return new FailUnimplemented("fcvtms", machInst); 145910037SARM gem5 Developers case 0x11: 146010037SARM gem5 Developers return new FailUnimplemented("fcvtmu", machInst); 146110037SARM gem5 Developers case 0x18: 146210037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 146310037SARM gem5 Developers case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 146410037SARM gem5 Developers return new FcvtFpSFixedSW(machInst, rd, rn, scale); 146510037SARM gem5 Developers case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 146610037SARM gem5 Developers return new FcvtFpSFixedDW(machInst, rd, rn, scale); 146710037SARM gem5 Developers case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 146810037SARM gem5 Developers return new FcvtFpSFixedSX(machInst, rd, rn, scale); 146910037SARM gem5 Developers case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 147010037SARM gem5 Developers return new FcvtFpSFixedDX(machInst, rd, rn, scale); 147110037SARM gem5 Developers default: 147210037SARM gem5 Developers return new Unknown64(machInst); 147310037SARM gem5 Developers } 147410037SARM gem5 Developers case 0x19: 147510037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 147610037SARM gem5 Developers case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 147710037SARM gem5 Developers return new FcvtFpUFixedSW(machInst, rd, rn, scale); 147810037SARM gem5 Developers case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 147910037SARM gem5 Developers return new FcvtFpUFixedDW(machInst, rd, rn, scale); 148010037SARM gem5 Developers case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 148110037SARM gem5 Developers return new FcvtFpUFixedSX(machInst, rd, rn, scale); 148210037SARM gem5 Developers case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 148310037SARM gem5 Developers return new FcvtFpUFixedDX(machInst, rd, rn, scale); 148410037SARM gem5 Developers default: 148510037SARM gem5 Developers return new Unknown64(machInst); 148610037SARM gem5 Developers } 148710037SARM gem5 Developers } 148810037SARM gem5 Developers } else { 148910037SARM gem5 Developers // 30=0, 28:24=11110, 21=1 149010037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 149110037SARM gem5 Developers uint8_t imm8 = bits(machInst, 20, 13); 149210037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 149310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 149410037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 149510037SARM gem5 Developers case 0x0: 149610037SARM gem5 Developers if (bits(machInst, 12) == 1) { 149710037SARM gem5 Developers if (bits(machInst, 31) || 149810037SARM gem5 Developers bits(machInst, 29) || 149910037SARM gem5 Developers bits(machInst, 9, 5)) { 150010037SARM gem5 Developers return new Unknown64(machInst); 150110037SARM gem5 Developers } 150210037SARM gem5 Developers // 31:29=000, 28:24=11110, 21=1, 12:10=100 150310037SARM gem5 Developers if (type == 0) { 150410037SARM gem5 Developers // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 150510037SARM gem5 Developers // :imm8<5:0>:Zeros(19) 150610037SARM gem5 Developers uint32_t imm = vfp_modified_imm(imm8, false); 150710037SARM gem5 Developers return new FmovImmS(machInst, rd, imm); 150810037SARM gem5 Developers } else if (type == 1) { 150910037SARM gem5 Developers // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 151010037SARM gem5 Developers // :imm8<5:0>:Zeros(48) 151110037SARM gem5 Developers uint64_t imm = vfp_modified_imm(imm8, true); 151210037SARM gem5 Developers return new FmovImmD(machInst, rd, imm); 151310037SARM gem5 Developers } else { 151410037SARM gem5 Developers return new Unknown64(machInst); 151510037SARM gem5 Developers } 151610037SARM gem5 Developers } else if (bits(machInst, 13) == 1) { 151710037SARM gem5 Developers if (bits(machInst, 31) || 151810037SARM gem5 Developers bits(machInst, 29) || 151910037SARM gem5 Developers bits(machInst, 15, 14) || 152010037SARM gem5 Developers bits(machInst, 23) || 152110037SARM gem5 Developers bits(machInst, 2, 0)) { 152210037SARM gem5 Developers return new Unknown64(machInst); 152310037SARM gem5 Developers } 152410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 152510037SARM gem5 Developers (bits(machInst, 22) << 2); 152610037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) 152710037SARM gem5 Developers bits(machInst, 20, 16); 152810037SARM gem5 Developers // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 152910037SARM gem5 Developers switch (switchVal) { 153010037SARM gem5 Developers case 0x0: 153110037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,Sm) 153210037SARM gem5 Developers return new FCmpRegS(machInst, rn, rm); 153310037SARM gem5 Developers case 0x1: 153410037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,0.0) 153510037SARM gem5 Developers return new FCmpImmS(machInst, rn, 0); 153610037SARM gem5 Developers case 0x2: 153710037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,Sm) 153810037SARM gem5 Developers return new FCmpERegS(machInst, rn, rm); 153910037SARM gem5 Developers case 0x3: 154010037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,0.0) 154110037SARM gem5 Developers return new FCmpEImmS(machInst, rn, 0); 154210037SARM gem5 Developers case 0x4: 154310037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,Dm) 154410037SARM gem5 Developers return new FCmpRegD(machInst, rn, rm); 154510037SARM gem5 Developers case 0x5: 154610037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,0.0) 154710037SARM gem5 Developers return new FCmpImmD(machInst, rn, 0); 154810037SARM gem5 Developers case 0x6: 154910037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,Dm) 155010037SARM gem5 Developers return new FCmpERegD(machInst, rn, rm); 155110037SARM gem5 Developers case 0x7: 155210037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,0.0) 155310037SARM gem5 Developers return new FCmpEImmD(machInst, rn, 0); 155410037SARM gem5 Developers default: 155510037SARM gem5 Developers return new Unknown64(machInst); 155610037SARM gem5 Developers } 155710037SARM gem5 Developers } else if (bits(machInst, 14) == 1) { 155810037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 155910037SARM gem5 Developers return new Unknown64(machInst); 156010037SARM gem5 Developers uint8_t opcode = bits(machInst, 20, 15); 156110037SARM gem5 Developers // Bits 31:24=00011110, 21=1, 14:10=10000 156210037SARM gem5 Developers switch (opcode) { 156310037SARM gem5 Developers case 0x0: 156410037SARM gem5 Developers if (type == 0) 156510037SARM gem5 Developers // FMOV Sd = Sn 156610037SARM gem5 Developers return new FmovRegS(machInst, rd, rn); 156710037SARM gem5 Developers else if (type == 1) 156810037SARM gem5 Developers // FMOV Dd = Dn 156910037SARM gem5 Developers return new FmovRegD(machInst, rd, rn); 157010037SARM gem5 Developers break; 157110037SARM gem5 Developers case 0x1: 157210037SARM gem5 Developers if (type == 0) 157310037SARM gem5 Developers // FABS Sd = abs(Sn) 157410037SARM gem5 Developers return new FAbsS(machInst, rd, rn); 157510037SARM gem5 Developers else if (type == 1) 157610037SARM gem5 Developers // FABS Dd = abs(Dn) 157710037SARM gem5 Developers return new FAbsD(machInst, rd, rn); 157810037SARM gem5 Developers break; 157910037SARM gem5 Developers case 0x2: 158010037SARM gem5 Developers if (type == 0) 158110037SARM gem5 Developers // FNEG Sd = -Sn 158210037SARM gem5 Developers return new FNegS(machInst, rd, rn); 158310037SARM gem5 Developers else if (type == 1) 158410037SARM gem5 Developers // FNEG Dd = -Dn 158510037SARM gem5 Developers return new FNegD(machInst, rd, rn); 158610037SARM gem5 Developers break; 158710037SARM gem5 Developers case 0x3: 158810037SARM gem5 Developers if (type == 0) 158910037SARM gem5 Developers // FSQRT Sd = sqrt(Sn) 159010037SARM gem5 Developers return new FSqrtS(machInst, rd, rn); 159110037SARM gem5 Developers else if (type == 1) 159210037SARM gem5 Developers // FSQRT Dd = sqrt(Dn) 159310037SARM gem5 Developers return new FSqrtD(machInst, rd, rn); 159410037SARM gem5 Developers break; 159510037SARM gem5 Developers case 0x4: 159610037SARM gem5 Developers if (type == 1) 159710037SARM gem5 Developers // FCVT Sd = convertFormat(Dn) 159810037SARM gem5 Developers return new FcvtFpDFpS(machInst, rd, rn); 159910037SARM gem5 Developers else if (type == 3) 160010037SARM gem5 Developers // FCVT Sd = convertFormat(Hn) 160110037SARM gem5 Developers return new FcvtFpHFpS(machInst, rd, rn); 160210037SARM gem5 Developers break; 160310037SARM gem5 Developers case 0x5: 160410037SARM gem5 Developers if (type == 0) 160510037SARM gem5 Developers // FCVT Dd = convertFormat(Sn) 160610037SARM gem5 Developers return new FCvtFpSFpD(machInst, rd, rn); 160710037SARM gem5 Developers else if (type == 3) 160810037SARM gem5 Developers // FCVT Dd = convertFormat(Hn) 160910037SARM gem5 Developers return new FcvtFpHFpD(machInst, rd, rn); 161010037SARM gem5 Developers break; 161110037SARM gem5 Developers case 0x7: 161210037SARM gem5 Developers if (type == 0) 161310037SARM gem5 Developers // FCVT Hd = convertFormat(Sn) 161410037SARM gem5 Developers return new FcvtFpSFpH(machInst, rd, rn); 161510037SARM gem5 Developers else if (type == 1) 161610037SARM gem5 Developers // FCVT Hd = convertFormat(Dn) 161710037SARM gem5 Developers return new FcvtFpDFpH(machInst, rd, rn); 161810037SARM gem5 Developers break; 161910037SARM gem5 Developers case 0x8: 162010037SARM gem5 Developers if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 162110037SARM gem5 Developers return new FRIntNS(machInst, rd, rn); 162210037SARM gem5 Developers else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 162310037SARM gem5 Developers return new FRIntND(machInst, rd, rn); 162410037SARM gem5 Developers break; 162510037SARM gem5 Developers case 0x9: 162610037SARM gem5 Developers if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 162710037SARM gem5 Developers return new FRIntPS(machInst, rd, rn); 162810037SARM gem5 Developers else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 162910037SARM gem5 Developers return new FRIntPD(machInst, rd, rn); 163010037SARM gem5 Developers break; 163110037SARM gem5 Developers case 0xa: 163210037SARM gem5 Developers if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 163310037SARM gem5 Developers return new FRIntMS(machInst, rd, rn); 163410037SARM gem5 Developers else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 163510037SARM gem5 Developers return new FRIntMD(machInst, rd, rn); 163610037SARM gem5 Developers break; 163710037SARM gem5 Developers case 0xb: 163810037SARM gem5 Developers if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 163910037SARM gem5 Developers return new FRIntZS(machInst, rd, rn); 164010037SARM gem5 Developers else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 164110037SARM gem5 Developers return new FRIntZD(machInst, rd, rn); 164210037SARM gem5 Developers break; 164310037SARM gem5 Developers case 0xc: 164410037SARM gem5 Developers if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 164510037SARM gem5 Developers return new FRIntAS(machInst, rd, rn); 164610037SARM gem5 Developers else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 164710037SARM gem5 Developers return new FRIntAD(machInst, rd, rn); 164810037SARM gem5 Developers break; 164910037SARM gem5 Developers case 0xe: 165010037SARM gem5 Developers if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 165110037SARM gem5 Developers return new FRIntXS(machInst, rd, rn); 165210037SARM gem5 Developers else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 165310037SARM gem5 Developers return new FRIntXD(machInst, rd, rn); 165410037SARM gem5 Developers break; 165510037SARM gem5 Developers case 0xf: 165610037SARM gem5 Developers if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 165710037SARM gem5 Developers return new FRIntIS(machInst, rd, rn); 165810037SARM gem5 Developers else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 165910037SARM gem5 Developers return new FRIntID(machInst, rd, rn); 166010037SARM gem5 Developers break; 166110037SARM gem5 Developers default: 166210037SARM gem5 Developers return new Unknown64(machInst); 166310037SARM gem5 Developers } 166410037SARM gem5 Developers return new Unknown64(machInst); 166510037SARM gem5 Developers } else if (bits(machInst, 15) == 1) { 166610037SARM gem5 Developers return new Unknown64(machInst); 166710037SARM gem5 Developers } else { 166810037SARM gem5 Developers if (bits(machInst, 29)) 166910037SARM gem5 Developers return new Unknown64(machInst); 167010037SARM gem5 Developers uint8_t rmode = bits(machInst, 20, 19); 167110037SARM gem5 Developers uint8_t switchVal1 = bits(machInst, 18, 16); 167210037SARM gem5 Developers uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 167310037SARM gem5 Developers // 30:24=0011110, 21=1, 15:10=000000 167410037SARM gem5 Developers switch (switchVal1) { 167510037SARM gem5 Developers case 0x0: 167610037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 167710037SARM gem5 Developers case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 167810037SARM gem5 Developers return new FcvtFpSIntWSN(machInst, rd, rn); 167910037SARM gem5 Developers case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 168010037SARM gem5 Developers return new FcvtFpSIntWSP(machInst, rd, rn); 168110037SARM gem5 Developers case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 168210037SARM gem5 Developers return new FcvtFpSIntWSM(machInst, rd, rn); 168310037SARM gem5 Developers case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 168410037SARM gem5 Developers return new FcvtFpSIntWSZ(machInst, rd, rn); 168510037SARM gem5 Developers case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 168610037SARM gem5 Developers return new FcvtFpSIntXSN(machInst, rd, rn); 168710037SARM gem5 Developers case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 168810037SARM gem5 Developers return new FcvtFpSIntXSP(machInst, rd, rn); 168910037SARM gem5 Developers case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 169010037SARM gem5 Developers return new FcvtFpSIntXSM(machInst, rd, rn); 169110037SARM gem5 Developers case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 169210037SARM gem5 Developers return new FcvtFpSIntXSZ(machInst, rd, rn); 169310037SARM gem5 Developers case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 169410037SARM gem5 Developers return new FcvtFpSIntWDN(machInst, rd, rn); 169510037SARM gem5 Developers case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 169610037SARM gem5 Developers return new FcvtFpSIntWDP(machInst, rd, rn); 169710037SARM gem5 Developers case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 169810037SARM gem5 Developers return new FcvtFpSIntWDM(machInst, rd, rn); 169910037SARM gem5 Developers case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 170010037SARM gem5 Developers return new FcvtFpSIntWDZ(machInst, rd, rn); 170110037SARM gem5 Developers case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 170210037SARM gem5 Developers return new FcvtFpSIntXDN(machInst, rd, rn); 170310037SARM gem5 Developers case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 170410037SARM gem5 Developers return new FcvtFpSIntXDP(machInst, rd, rn); 170510037SARM gem5 Developers case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 170610037SARM gem5 Developers return new FcvtFpSIntXDM(machInst, rd, rn); 170710037SARM gem5 Developers case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 170810037SARM gem5 Developers return new FcvtFpSIntXDZ(machInst, rd, rn); 170910037SARM gem5 Developers default: 171010037SARM gem5 Developers return new Unknown64(machInst); 171110037SARM gem5 Developers } 171210037SARM gem5 Developers case 0x1: 171310037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 171410037SARM gem5 Developers case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 171510037SARM gem5 Developers return new FcvtFpUIntWSN(machInst, rd, rn); 171610037SARM gem5 Developers case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 171710037SARM gem5 Developers return new FcvtFpUIntWSP(machInst, rd, rn); 171810037SARM gem5 Developers case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 171910037SARM gem5 Developers return new FcvtFpUIntWSM(machInst, rd, rn); 172010037SARM gem5 Developers case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 172110037SARM gem5 Developers return new FcvtFpUIntWSZ(machInst, rd, rn); 172210037SARM gem5 Developers case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 172310037SARM gem5 Developers return new FcvtFpUIntXSN(machInst, rd, rn); 172410037SARM gem5 Developers case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 172510037SARM gem5 Developers return new FcvtFpUIntXSP(machInst, rd, rn); 172610037SARM gem5 Developers case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 172710037SARM gem5 Developers return new FcvtFpUIntXSM(machInst, rd, rn); 172810037SARM gem5 Developers case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 172910037SARM gem5 Developers return new FcvtFpUIntXSZ(machInst, rd, rn); 173010037SARM gem5 Developers case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 173110037SARM gem5 Developers return new FcvtFpUIntWDN(machInst, rd, rn); 173210037SARM gem5 Developers case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 173310037SARM gem5 Developers return new FcvtFpUIntWDP(machInst, rd, rn); 173410037SARM gem5 Developers case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 173510037SARM gem5 Developers return new FcvtFpUIntWDM(machInst, rd, rn); 173610037SARM gem5 Developers case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 173710037SARM gem5 Developers return new FcvtFpUIntWDZ(machInst, rd, rn); 173810037SARM gem5 Developers case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 173910037SARM gem5 Developers return new FcvtFpUIntXDN(machInst, rd, rn); 174010037SARM gem5 Developers case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 174110037SARM gem5 Developers return new FcvtFpUIntXDP(machInst, rd, rn); 174210037SARM gem5 Developers case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 174310037SARM gem5 Developers return new FcvtFpUIntXDM(machInst, rd, rn); 174410037SARM gem5 Developers case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 174510037SARM gem5 Developers return new FcvtFpUIntXDZ(machInst, rd, rn); 174610037SARM gem5 Developers default: 174710037SARM gem5 Developers return new Unknown64(machInst); 174810037SARM gem5 Developers } 174910037SARM gem5 Developers case 0x2: 175010037SARM gem5 Developers if (rmode != 0) 175110037SARM gem5 Developers return new Unknown64(machInst); 175210037SARM gem5 Developers switch (switchVal2) { 175310037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn) 175410037SARM gem5 Developers return new FcvtWSIntFpS(machInst, rd, rn); 175510037SARM gem5 Developers case 1: // SCVTF Sd = convertFromInt(Xn) 175610037SARM gem5 Developers return new FcvtXSIntFpS(machInst, rd, rn); 175710037SARM gem5 Developers case 2: // SCVTF Dd = convertFromInt(Wn) 175810037SARM gem5 Developers return new FcvtWSIntFpD(machInst, rd, rn); 175910037SARM gem5 Developers case 3: // SCVTF Dd = convertFromInt(Xn) 176010037SARM gem5 Developers return new FcvtXSIntFpD(machInst, rd, rn); 176110037SARM gem5 Developers default: 176210037SARM gem5 Developers return new Unknown64(machInst); 176310037SARM gem5 Developers } 176410037SARM gem5 Developers case 0x3: 176510037SARM gem5 Developers switch (switchVal2) { 176610037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn) 176710037SARM gem5 Developers return new FcvtWUIntFpS(machInst, rd, rn); 176810037SARM gem5 Developers case 1: // UCVTF Sd = convertFromInt(Xn) 176910037SARM gem5 Developers return new FcvtXUIntFpS(machInst, rd, rn); 177010037SARM gem5 Developers case 2: // UCVTF Dd = convertFromInt(Wn) 177110037SARM gem5 Developers return new FcvtWUIntFpD(machInst, rd, rn); 177210037SARM gem5 Developers case 3: // UCVTF Dd = convertFromInt(Xn) 177310037SARM gem5 Developers return new FcvtXUIntFpD(machInst, rd, rn); 177410037SARM gem5 Developers default: 177510037SARM gem5 Developers return new Unknown64(machInst); 177610037SARM gem5 Developers } 177710037SARM gem5 Developers case 0x4: 177810037SARM gem5 Developers if (rmode != 0) 177910037SARM gem5 Developers return new Unknown64(machInst); 178010037SARM gem5 Developers switch (switchVal2) { 178110037SARM gem5 Developers case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 178210037SARM gem5 Developers return new FcvtFpSIntWSA(machInst, rd, rn); 178310037SARM gem5 Developers case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 178410037SARM gem5 Developers return new FcvtFpSIntXSA(machInst, rd, rn); 178510037SARM gem5 Developers case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 178610037SARM gem5 Developers return new FcvtFpSIntWDA(machInst, rd, rn); 178710037SARM gem5 Developers case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 178810037SARM gem5 Developers return new FcvtFpSIntXDA(machInst, rd, rn); 178910037SARM gem5 Developers default: 179010037SARM gem5 Developers return new Unknown64(machInst); 179110037SARM gem5 Developers } 179210037SARM gem5 Developers case 0x5: 179310037SARM gem5 Developers switch (switchVal2) { 179410037SARM gem5 Developers case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 179510037SARM gem5 Developers return new FcvtFpUIntWSA(machInst, rd, rn); 179610037SARM gem5 Developers case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 179710037SARM gem5 Developers return new FcvtFpUIntXSA(machInst, rd, rn); 179810037SARM gem5 Developers case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 179910037SARM gem5 Developers return new FcvtFpUIntWDA(machInst, rd, rn); 180010037SARM gem5 Developers case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 180110037SARM gem5 Developers return new FcvtFpUIntXDA(machInst, rd, rn); 180210037SARM gem5 Developers default: 180310037SARM gem5 Developers return new Unknown64(machInst); 180410037SARM gem5 Developers } 180510037SARM gem5 Developers case 0x06: 180610037SARM gem5 Developers switch (switchVal2) { 180710037SARM gem5 Developers case 0: // FMOV Wd = Sn 180810037SARM gem5 Developers if (rmode != 0) 180910037SARM gem5 Developers return new Unknown64(machInst); 181010037SARM gem5 Developers return new FmovRegCoreW(machInst, rd, rn); 181110037SARM gem5 Developers case 3: // FMOV Xd = Dn 181210037SARM gem5 Developers if (rmode != 0) 181310037SARM gem5 Developers return new Unknown64(machInst); 181410037SARM gem5 Developers return new FmovRegCoreX(machInst, rd, rn); 181510037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 181610037SARM gem5 Developers if (rmode != 1) 181710037SARM gem5 Developers return new Unknown64(machInst); 181810037SARM gem5 Developers return new FmovURegCoreX(machInst, rd, rn); 181910037SARM gem5 Developers default: 182010037SARM gem5 Developers return new Unknown64(machInst); 182110037SARM gem5 Developers } 182210037SARM gem5 Developers break; 182310037SARM gem5 Developers case 0x07: 182410037SARM gem5 Developers switch (switchVal2) { 182510037SARM gem5 Developers case 0: // FMOV Sd = Wn 182610037SARM gem5 Developers if (rmode != 0) 182710037SARM gem5 Developers return new Unknown64(machInst); 182810037SARM gem5 Developers return new FmovCoreRegW(machInst, rd, rn); 182910037SARM gem5 Developers case 3: // FMOV Xd = Dn 183010037SARM gem5 Developers if (rmode != 0) 183110037SARM gem5 Developers return new Unknown64(machInst); 183210037SARM gem5 Developers return new FmovCoreRegX(machInst, rd, rn); 183310037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 183410037SARM gem5 Developers if (rmode != 1) 183510037SARM gem5 Developers return new Unknown64(machInst); 183610037SARM gem5 Developers return new FmovUCoreRegX(machInst, rd, rn); 183710037SARM gem5 Developers default: 183810037SARM gem5 Developers return new Unknown64(machInst); 183910037SARM gem5 Developers } 184010037SARM gem5 Developers break; 184110037SARM gem5 Developers default: // Warning! missing cases in switch statement above, that still need to be added 184210037SARM gem5 Developers return new Unknown64(machInst); 184310037SARM gem5 Developers } 184410037SARM gem5 Developers } 184510037SARM gem5 Developers case 0x1: 184610037SARM gem5 Developers { 184710037SARM gem5 Developers if (bits(machInst, 31) || 184810037SARM gem5 Developers bits(machInst, 29) || 184910037SARM gem5 Developers bits(machInst, 23)) { 185010037SARM gem5 Developers return new Unknown64(machInst); 185110037SARM gem5 Developers } 185210037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 185310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 185410037SARM gem5 Developers uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 185510037SARM gem5 Developers ConditionCode cond = 185610037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 185710037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4) << 0) | 185810037SARM gem5 Developers (bits(machInst, 22) << 1); 185910037SARM gem5 Developers // 31:23=000111100, 21=1, 11:10=01 186010037SARM gem5 Developers switch (switchVal) { 186110037SARM gem5 Developers case 0x0: 186210037SARM gem5 Developers // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 186310037SARM gem5 Developers return new FCCmpRegS(machInst, rn, rm, cond, imm); 186410037SARM gem5 Developers case 0x1: 186510037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Sn,Sm) 186610037SARM gem5 Developers // else #nzcv 186710037SARM gem5 Developers return new FCCmpERegS(machInst, rn, rm, cond, imm); 186810037SARM gem5 Developers case 0x2: 186910037SARM gem5 Developers // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 187010037SARM gem5 Developers return new FCCmpRegD(machInst, rn, rm, cond, imm); 187110037SARM gem5 Developers case 0x3: 187210037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Dn,Dm) 187310037SARM gem5 Developers // else #nzcv 187410037SARM gem5 Developers return new FCCmpERegD(machInst, rn, rm, cond, imm); 187510037SARM gem5 Developers default: 187610037SARM gem5 Developers return new Unknown64(machInst); 187710037SARM gem5 Developers } 187810037SARM gem5 Developers } 187910037SARM gem5 Developers case 0x2: 188010037SARM gem5 Developers { 188110037SARM gem5 Developers if (bits(machInst, 31) || 188210037SARM gem5 Developers bits(machInst, 29) || 188310037SARM gem5 Developers bits(machInst, 23)) { 188410037SARM gem5 Developers return new Unknown64(machInst); 188510037SARM gem5 Developers } 188610037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 188710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 188810037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 188910037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 189010037SARM gem5 Developers (bits(machInst, 22) << 4); 189110037SARM gem5 Developers switch (switchVal) { 189210037SARM gem5 Developers case 0x00: // FMUL Sd = Sn * Sm 189310037SARM gem5 Developers return new FMulS(machInst, rd, rn, rm); 189410037SARM gem5 Developers case 0x10: // FMUL Dd = Dn * Dm 189510037SARM gem5 Developers return new FMulD(machInst, rd, rn, rm); 189610037SARM gem5 Developers case 0x01: // FDIV Sd = Sn / Sm 189710037SARM gem5 Developers return new FDivS(machInst, rd, rn, rm); 189810037SARM gem5 Developers case 0x11: // FDIV Dd = Dn / Dm 189910037SARM gem5 Developers return new FDivD(machInst, rd, rn, rm); 190010037SARM gem5 Developers case 0x02: // FADD Sd = Sn + Sm 190110037SARM gem5 Developers return new FAddS(machInst, rd, rn, rm); 190210037SARM gem5 Developers case 0x12: // FADD Dd = Dn + Dm 190310037SARM gem5 Developers return new FAddD(machInst, rd, rn, rm); 190410037SARM gem5 Developers case 0x03: // FSUB Sd = Sn - Sm 190510037SARM gem5 Developers return new FSubS(machInst, rd, rn, rm); 190610037SARM gem5 Developers case 0x13: // FSUB Dd = Dn - Dm 190710037SARM gem5 Developers return new FSubD(machInst, rd, rn, rm); 190810037SARM gem5 Developers case 0x04: // FMAX Sd = max(Sn, Sm) 190910037SARM gem5 Developers return new FMaxS(machInst, rd, rn, rm); 191010037SARM gem5 Developers case 0x14: // FMAX Dd = max(Dn, Dm) 191110037SARM gem5 Developers return new FMaxD(machInst, rd, rn, rm); 191210037SARM gem5 Developers case 0x05: // FMIN Sd = min(Sn, Sm) 191310037SARM gem5 Developers return new FMinS(machInst, rd, rn, rm); 191410037SARM gem5 Developers case 0x15: // FMIN Dd = min(Dn, Dm) 191510037SARM gem5 Developers return new FMinD(machInst, rd, rn, rm); 191610037SARM gem5 Developers case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 191710037SARM gem5 Developers return new FMaxNMS(machInst, rd, rn, rm); 191810037SARM gem5 Developers case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 191910037SARM gem5 Developers return new FMaxNMD(machInst, rd, rn, rm); 192010037SARM gem5 Developers case 0x07: // FMINNM Sd = minNum(Sn, Sm) 192110037SARM gem5 Developers return new FMinNMS(machInst, rd, rn, rm); 192210037SARM gem5 Developers case 0x17: // FMINNM Dd = minNum(Dn, Dm) 192310037SARM gem5 Developers return new FMinNMD(machInst, rd, rn, rm); 192410037SARM gem5 Developers case 0x08: // FNMUL Sd = -(Sn * Sm) 192510037SARM gem5 Developers return new FNMulS(machInst, rd, rn, rm); 192610037SARM gem5 Developers case 0x18: // FNMUL Dd = -(Dn * Dm) 192710037SARM gem5 Developers return new FNMulD(machInst, rd, rn, rm); 192810037SARM gem5 Developers default: 192910037SARM gem5 Developers return new Unknown64(machInst); 193010037SARM gem5 Developers } 193110037SARM gem5 Developers } 193210037SARM gem5 Developers case 0x3: 193310037SARM gem5 Developers { 193410037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 193510037SARM gem5 Developers return new Unknown64(machInst); 193610037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 193710037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 193810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 193910037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 194010037SARM gem5 Developers ConditionCode cond = 194110037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 194210037SARM gem5 Developers if (type == 0) // FCSEL Sd = if cond then Sn else Sm 194310037SARM gem5 Developers return new FCSelS(machInst, rd, rn, rm, cond); 194410037SARM gem5 Developers else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 194510037SARM gem5 Developers return new FCSelD(machInst, rd, rn, rm, cond); 194610037SARM gem5 Developers else 194710037SARM gem5 Developers return new Unknown64(machInst); 194810037SARM gem5 Developers } 194910037SARM gem5 Developers } 195010037SARM gem5 Developers } 195110037SARM gem5 Developers return new FailUnimplemented("Unhandled Case4", machInst); 195210037SARM gem5 Developers } 195310037SARM gem5 Developers} 195410037SARM gem5 Developers}}; 195510037SARM gem5 Developers 195610037SARM gem5 Developersoutput decoder {{ 195710037SARM gem5 Developersnamespace Aarch64 195810037SARM gem5 Developers{ 195910037SARM gem5 Developers StaticInstPtr 196010037SARM gem5 Developers decodeAdvSIMDScalar(ExtMachInst machInst) 196110037SARM gem5 Developers { 196210037SARM gem5 Developers if (bits(machInst, 24) == 1) { 196310037SARM gem5 Developers if (bits(machInst, 10) == 0) { 196410037SARM gem5 Developers return decodeNeonScIndexedElem(machInst); 196510037SARM gem5 Developers } else if (bits(machInst, 23) == 0) { 196610037SARM gem5 Developers return decodeNeonScShiftByImm(machInst); 196710037SARM gem5 Developers } 196810037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 196910037SARM gem5 Developers if (bits(machInst, 10) == 1) { 197010037SARM gem5 Developers return decodeNeonSc3Same(machInst); 197110037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 197210037SARM gem5 Developers return decodeNeonSc3Diff(machInst); 197310037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 197410037SARM gem5 Developers return decodeNeonSc2RegMisc(machInst); 197510037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 197610037SARM gem5 Developers return decodeNeonScPwise(machInst); 197710037SARM gem5 Developers } else { 197810037SARM gem5 Developers return new Unknown64(machInst); 197910037SARM gem5 Developers } 198010037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0 && 198110037SARM gem5 Developers bits(machInst, 15) == 0 && 198210037SARM gem5 Developers bits(machInst, 10) == 1) { 198310037SARM gem5 Developers return decodeNeonScCopy(machInst); 198410037SARM gem5 Developers } else { 198510037SARM gem5 Developers return new Unknown64(machInst); 198610037SARM gem5 Developers } 198710037SARM gem5 Developers return new FailUnimplemented("Unhandled Case6", machInst); 198810037SARM gem5 Developers } 198910037SARM gem5 Developers} 199010037SARM gem5 Developers}}; 199110037SARM gem5 Developers 199210037SARM gem5 Developersoutput decoder {{ 199310037SARM gem5 Developersnamespace Aarch64 199410037SARM gem5 Developers{ 199511165SRekai.GonzalezAlberquilla@arm.com template <typename DecoderFeatures> 199610037SARM gem5 Developers StaticInstPtr 199710037SARM gem5 Developers decodeFpAdvSIMD(ExtMachInst machInst) 199810037SARM gem5 Developers { 199910037SARM gem5 Developers 200010037SARM gem5 Developers if (bits(machInst, 28) == 0) { 200110037SARM gem5 Developers if (bits(machInst, 31) == 0) { 200211165SRekai.GonzalezAlberquilla@arm.com return decodeAdvSIMD<DecoderFeatures>(machInst); 200310037SARM gem5 Developers } else { 200410037SARM gem5 Developers return new Unknown64(machInst); 200510037SARM gem5 Developers } 200610037SARM gem5 Developers } else if (bits(machInst, 30) == 0) { 200710037SARM gem5 Developers return decodeFp(machInst); 200810037SARM gem5 Developers } else if (bits(machInst, 31) == 0) { 200910037SARM gem5 Developers return decodeAdvSIMDScalar(machInst); 201010037SARM gem5 Developers } else { 201110037SARM gem5 Developers return new Unknown64(machInst); 201210037SARM gem5 Developers } 201310037SARM gem5 Developers } 201410037SARM gem5 Developers} 201510037SARM gem5 Developers}}; 201610037SARM gem5 Developers 201711165SRekai.GonzalezAlberquilla@arm.comlet {{ 201811165SRekai.GonzalezAlberquilla@arm.com decoder_output =''' 201911165SRekai.GonzalezAlberquilla@arm.comnamespace Aarch64 202011165SRekai.GonzalezAlberquilla@arm.com{''' 202111165SRekai.GonzalezAlberquilla@arm.com for decoderFlavour, type_dict in decoders.iteritems(): 202211165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 202311165SRekai.GonzalezAlberquilla@arm.comtemplate StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); 202411165SRekai.GonzalezAlberquilla@arm.com''' % { "df" : decoderFlavour } 202511165SRekai.GonzalezAlberquilla@arm.com decoder_output +=''' 202611165SRekai.GonzalezAlberquilla@arm.com}''' 202711165SRekai.GonzalezAlberquilla@arm.com}}; 202811165SRekai.GonzalezAlberquilla@arm.com 202910037SARM gem5 Developersoutput decoder {{ 203010037SARM gem5 Developersnamespace Aarch64 203110037SARM gem5 Developers{ 203210037SARM gem5 Developers StaticInstPtr 203310037SARM gem5 Developers decodeGem5Ops(ExtMachInst machInst) 203410037SARM gem5 Developers { 203510037SARM gem5 Developers const uint32_t m5func = bits(machInst, 23, 16); 203610037SARM gem5 Developers switch (m5func) { 203712159Sandreas.sandberg@arm.com case M5OP_ARM: return new Arm(machInst); 203812159Sandreas.sandberg@arm.com case M5OP_QUIESCE: return new Quiesce(machInst); 203912159Sandreas.sandberg@arm.com case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst); 204012159Sandreas.sandberg@arm.com case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst); 204112159Sandreas.sandberg@arm.com case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst); 204212159Sandreas.sandberg@arm.com case M5OP_RPNS: return new Rpns64(machInst); 204312159Sandreas.sandberg@arm.com case M5OP_WAKE_CPU: return new WakeCPU64(machInst); 204412159Sandreas.sandberg@arm.com case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); 204512159Sandreas.sandberg@arm.com case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); 204612159Sandreas.sandberg@arm.com case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); 204712159Sandreas.sandberg@arm.com case M5OP_EXIT: return new M5exit64(machInst); 204812159Sandreas.sandberg@arm.com case M5OP_FAIL: return new M5fail64(machInst); 204912159Sandreas.sandberg@arm.com case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); 205012159Sandreas.sandberg@arm.com case M5OP_INIT_PARAM: return new Initparam64(machInst); 205112159Sandreas.sandberg@arm.com case M5OP_RESET_STATS: return new Resetstats64(machInst); 205212159Sandreas.sandberg@arm.com case M5OP_DUMP_STATS: return new Dumpstats64(machInst); 205312159Sandreas.sandberg@arm.com case M5OP_DUMP_RESET_STATS: return new Dumpresetstats64(machInst); 205412159Sandreas.sandberg@arm.com case M5OP_CHECKPOINT: return new M5checkpoint64(machInst); 205512159Sandreas.sandberg@arm.com case M5OP_WRITE_FILE: return new M5writefile64(machInst); 205612159Sandreas.sandberg@arm.com case M5OP_READ_FILE: return new M5readfile64(machInst); 205712159Sandreas.sandberg@arm.com case M5OP_DEBUG_BREAK: return new M5break(machInst); 205812159Sandreas.sandberg@arm.com case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); 205912159Sandreas.sandberg@arm.com case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst); 206012159Sandreas.sandberg@arm.com case M5OP_PANIC: return new M5panic(machInst); 206112159Sandreas.sandberg@arm.com case M5OP_WORK_BEGIN: return new M5workbegin64(machInst); 206212159Sandreas.sandberg@arm.com case M5OP_WORK_END: return new M5workend64(machInst); 206310037SARM gem5 Developers default: return new Unknown64(machInst); 206410037SARM gem5 Developers } 206510037SARM gem5 Developers } 206610037SARM gem5 Developers} 206710037SARM gem5 Developers}}; 206810037SARM gem5 Developers 206910037SARM gem5 Developersdef format Aarch64() {{ 207010037SARM gem5 Developers decode_block = ''' 207110037SARM gem5 Developers { 207210037SARM gem5 Developers using namespace Aarch64; 207310037SARM gem5 Developers if (bits(machInst, 27) == 0x0) { 207410037SARM gem5 Developers if (bits(machInst, 28) == 0x0) 207510037SARM gem5 Developers return new Unknown64(machInst); 207610037SARM gem5 Developers else if (bits(machInst, 26) == 0) 207710037SARM gem5 Developers // bit 28:26=100 207810037SARM gem5 Developers return decodeDataProcImm(machInst); 207910037SARM gem5 Developers else 208010037SARM gem5 Developers // bit 28:26=101 208110037SARM gem5 Developers return decodeBranchExcSys(machInst); 208210037SARM gem5 Developers } else if (bits(machInst, 25) == 0) { 208310037SARM gem5 Developers // bit 27=1, 25=0 208410037SARM gem5 Developers return decodeLoadsStores(machInst); 208510037SARM gem5 Developers } else if (bits(machInst, 26) == 0) { 208610037SARM gem5 Developers // bit 27:25=101 208710037SARM gem5 Developers return decodeDataProcReg(machInst); 208810037SARM gem5 Developers } else if (bits(machInst, 24) == 1 && 208910037SARM gem5 Developers bits(machInst, 31, 28) == 0xF) { 209010037SARM gem5 Developers return decodeGem5Ops(machInst); 209110037SARM gem5 Developers } else { 209210037SARM gem5 Developers // bit 27:25=111 209311165SRekai.GonzalezAlberquilla@arm.com switch(decoderFlavour){ 209411165SRekai.GonzalezAlberquilla@arm.com default: 209511165SRekai.GonzalezAlberquilla@arm.com return decodeFpAdvSIMD<GenericDecoder>(machInst); 209611165SRekai.GonzalezAlberquilla@arm.com } 209710037SARM gem5 Developers } 209810037SARM gem5 Developers } 209910037SARM gem5 Developers ''' 210010037SARM gem5 Developers}}; 2101