aarch64.isa revision 10506
110337SAndrew.Bardsley@arm.com// Copyright (c) 2011-2014 ARM Limited 210037SARM gem5 Developers// All rights reserved 310037SARM gem5 Developers// 410037SARM gem5 Developers// The license below extends only to copyright in the software and shall 510037SARM gem5 Developers// not be construed as granting a license to any other intellectual 610037SARM gem5 Developers// property including but not limited to intellectual property relating 710037SARM gem5 Developers// to a hardware implementation of the functionality of the software 810037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers// 1310037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1410037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1510037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1610037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1710037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 1910037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2010037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2110037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2210037SARM gem5 Developers// this software without specific prior written permission. 2310037SARM gem5 Developers// 2410037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510037SARM gem5 Developers// 3610037SARM gem5 Developers// Authors: Gabe Black 3710037SARM gem5 Developers// Thomas Grocutt 3810037SARM gem5 Developers// Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developersoutput header {{ 4210037SARM gem5 Developersnamespace Aarch64 4310037SARM gem5 Developers{ 4410037SARM gem5 Developers StaticInstPtr decodeDataProcImm(ExtMachInst machInst); 4510037SARM gem5 Developers StaticInstPtr decodeBranchExcSys(ExtMachInst machInst); 4610037SARM gem5 Developers StaticInstPtr decodeLoadsStores(ExtMachInst machInst); 4710037SARM gem5 Developers StaticInstPtr decodeDataProcReg(ExtMachInst machInst); 4810037SARM gem5 Developers 4910037SARM gem5 Developers StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); 5010037SARM gem5 Developers StaticInstPtr decodeFp(ExtMachInst machInst); 5110037SARM gem5 Developers StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); 5210037SARM gem5 Developers StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); 5310037SARM gem5 Developers 5410037SARM gem5 Developers StaticInstPtr decodeGem5Ops(ExtMachInst machInst); 5510037SARM gem5 Developers} 5610037SARM gem5 Developers}}; 5710037SARM gem5 Developers 5810037SARM gem5 Developersoutput decoder {{ 5910037SARM gem5 Developersnamespace Aarch64 6010037SARM gem5 Developers{ 6110037SARM gem5 Developers StaticInstPtr 6210037SARM gem5 Developers decodeDataProcImm(ExtMachInst machInst) 6310037SARM gem5 Developers { 6410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 6510037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 6610337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 6710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 6810037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 6910037SARM gem5 Developers 7010037SARM gem5 Developers uint8_t opc = bits(machInst, 30, 29); 7110037SARM gem5 Developers bool sf = bits(machInst, 31); 7210037SARM gem5 Developers bool n = bits(machInst, 22); 7310037SARM gem5 Developers uint8_t immr = bits(machInst, 21, 16); 7410037SARM gem5 Developers uint8_t imms = bits(machInst, 15, 10); 7510037SARM gem5 Developers switch (bits(machInst, 25, 23)) { 7610037SARM gem5 Developers case 0x0: 7710037SARM gem5 Developers case 0x1: 7810037SARM gem5 Developers { 7910037SARM gem5 Developers uint64_t immlo = bits(machInst, 30, 29); 8010037SARM gem5 Developers uint64_t immhi = bits(machInst, 23, 5); 8110037SARM gem5 Developers uint64_t imm = (immlo << 0) | (immhi << 2); 8210037SARM gem5 Developers if (bits(machInst, 31) == 0) 8310337SAndrew.Bardsley@arm.com return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm)); 8410037SARM gem5 Developers else 8510337SAndrew.Bardsley@arm.com return new AdrpXImm(machInst, rdzr, INTREG_ZERO, 8610037SARM gem5 Developers sext<33>(imm << 12)); 8710037SARM gem5 Developers } 8810037SARM gem5 Developers case 0x2: 8910037SARM gem5 Developers case 0x3: 9010037SARM gem5 Developers { 9110037SARM gem5 Developers uint32_t imm12 = bits(machInst, 21, 10); 9210037SARM gem5 Developers uint8_t shift = bits(machInst, 23, 22); 9310037SARM gem5 Developers uint32_t imm; 9410037SARM gem5 Developers if (shift == 0x0) 9510037SARM gem5 Developers imm = imm12 << 0; 9610037SARM gem5 Developers else if (shift == 0x1) 9710037SARM gem5 Developers imm = imm12 << 12; 9810037SARM gem5 Developers else 9910037SARM gem5 Developers return new Unknown64(machInst); 10010037SARM gem5 Developers switch (opc) { 10110037SARM gem5 Developers case 0x0: 10210037SARM gem5 Developers return new AddXImm(machInst, rdsp, rnsp, imm); 10310037SARM gem5 Developers case 0x1: 10410337SAndrew.Bardsley@arm.com return new AddXImmCc(machInst, rdzr, rnsp, imm); 10510037SARM gem5 Developers case 0x2: 10610037SARM gem5 Developers return new SubXImm(machInst, rdsp, rnsp, imm); 10710037SARM gem5 Developers case 0x3: 10810337SAndrew.Bardsley@arm.com return new SubXImmCc(machInst, rdzr, rnsp, imm); 10910037SARM gem5 Developers } 11010037SARM gem5 Developers } 11110037SARM gem5 Developers case 0x4: 11210037SARM gem5 Developers { 11310037SARM gem5 Developers if (!sf && n) 11410037SARM gem5 Developers return new Unknown64(machInst); 11510037SARM gem5 Developers // len = MSB(n:NOT(imms)), len < 1 is undefined. 11610037SARM gem5 Developers uint8_t len = 0; 11710037SARM gem5 Developers if (n) { 11810037SARM gem5 Developers len = 6; 11910037SARM gem5 Developers } else if (imms == 0x3f || imms == 0x3e) { 12010037SARM gem5 Developers return new Unknown64(machInst); 12110037SARM gem5 Developers } else { 12210037SARM gem5 Developers len = findMsbSet(imms ^ 0x3f); 12310037SARM gem5 Developers } 12410037SARM gem5 Developers // Generate r, s, and size. 12510037SARM gem5 Developers uint64_t r = bits(immr, len - 1, 0); 12610037SARM gem5 Developers uint64_t s = bits(imms, len - 1, 0); 12710037SARM gem5 Developers uint8_t size = 1 << len; 12810037SARM gem5 Developers if (s == size - 1) 12910037SARM gem5 Developers return new Unknown64(machInst); 13010037SARM gem5 Developers // Generate the pattern with s 1s, rotated by r, with size bits. 13110037SARM gem5 Developers uint64_t pattern = mask(s + 1); 13210037SARM gem5 Developers if (r) { 13310037SARM gem5 Developers pattern = (pattern >> r) | (pattern << (size - r)); 13410037SARM gem5 Developers pattern &= mask(size); 13510037SARM gem5 Developers } 13610037SARM gem5 Developers uint8_t width = sf ? 64 : 32; 13710037SARM gem5 Developers // Replicate that to fill up the immediate. 13810037SARM gem5 Developers for (unsigned i = 1; i < (width / size); i *= 2) 13910037SARM gem5 Developers pattern |= (pattern << (i * size)); 14010037SARM gem5 Developers uint64_t imm = pattern; 14110037SARM gem5 Developers 14210037SARM gem5 Developers switch (opc) { 14310037SARM gem5 Developers case 0x0: 14410037SARM gem5 Developers return new AndXImm(machInst, rdsp, rn, imm); 14510037SARM gem5 Developers case 0x1: 14610037SARM gem5 Developers return new OrrXImm(machInst, rdsp, rn, imm); 14710037SARM gem5 Developers case 0x2: 14810037SARM gem5 Developers return new EorXImm(machInst, rdsp, rn, imm); 14910037SARM gem5 Developers case 0x3: 15010337SAndrew.Bardsley@arm.com return new AndXImmCc(machInst, rdzr, rn, imm); 15110037SARM gem5 Developers } 15210037SARM gem5 Developers } 15310037SARM gem5 Developers case 0x5: 15410037SARM gem5 Developers { 15510037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 15610337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 15710037SARM gem5 Developers uint32_t imm16 = bits(machInst, 20, 5); 15810037SARM gem5 Developers uint32_t hw = bits(machInst, 22, 21); 15910037SARM gem5 Developers switch (opc) { 16010037SARM gem5 Developers case 0x0: 16110337SAndrew.Bardsley@arm.com return new Movn(machInst, rdzr, imm16, hw * 16); 16210037SARM gem5 Developers case 0x1: 16310037SARM gem5 Developers return new Unknown64(machInst); 16410037SARM gem5 Developers case 0x2: 16510337SAndrew.Bardsley@arm.com return new Movz(machInst, rdzr, imm16, hw * 16); 16610037SARM gem5 Developers case 0x3: 16710337SAndrew.Bardsley@arm.com return new Movk(machInst, rdzr, imm16, hw * 16); 16810037SARM gem5 Developers } 16910037SARM gem5 Developers } 17010037SARM gem5 Developers case 0x6: 17110037SARM gem5 Developers if ((sf != n) || (!sf && (bits(immr, 5) || bits(imms, 5)))) 17210037SARM gem5 Developers return new Unknown64(machInst); 17310037SARM gem5 Developers switch (opc) { 17410037SARM gem5 Developers case 0x0: 17510337SAndrew.Bardsley@arm.com return new Sbfm64(machInst, rdzr, rn, immr, imms); 17610037SARM gem5 Developers case 0x1: 17710337SAndrew.Bardsley@arm.com return new Bfm64(machInst, rdzr, rn, immr, imms); 17810037SARM gem5 Developers case 0x2: 17910337SAndrew.Bardsley@arm.com return new Ubfm64(machInst, rdzr, rn, immr, imms); 18010037SARM gem5 Developers case 0x3: 18110037SARM gem5 Developers return new Unknown64(machInst); 18210037SARM gem5 Developers } 18310037SARM gem5 Developers case 0x7: 18410037SARM gem5 Developers { 18510037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 18610037SARM gem5 Developers if (opc || bits(machInst, 21)) 18710037SARM gem5 Developers return new Unknown64(machInst); 18810037SARM gem5 Developers else 18910337SAndrew.Bardsley@arm.com return new Extr64(machInst, rdzr, rn, rm, imms); 19010037SARM gem5 Developers } 19110037SARM gem5 Developers } 19210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case8", machInst); 19310037SARM gem5 Developers } 19410037SARM gem5 Developers} 19510037SARM gem5 Developers}}; 19610037SARM gem5 Developers 19710037SARM gem5 Developersoutput decoder {{ 19810037SARM gem5 Developersnamespace Aarch64 19910037SARM gem5 Developers{ 20010037SARM gem5 Developers StaticInstPtr 20110037SARM gem5 Developers decodeBranchExcSys(ExtMachInst machInst) 20210037SARM gem5 Developers { 20310037SARM gem5 Developers switch (bits(machInst, 30, 29)) { 20410037SARM gem5 Developers case 0x0: 20510037SARM gem5 Developers { 20610037SARM gem5 Developers int64_t imm = sext<26>(bits(machInst, 25, 0)) << 2; 20710037SARM gem5 Developers if (bits(machInst, 31) == 0) 20810037SARM gem5 Developers return new B64(machInst, imm); 20910037SARM gem5 Developers else 21010037SARM gem5 Developers return new Bl64(machInst, imm); 21110037SARM gem5 Developers } 21210037SARM gem5 Developers case 0x1: 21310037SARM gem5 Developers { 21410037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 21510037SARM gem5 Developers if (bits(machInst, 25) == 0) { 21610037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 21710037SARM gem5 Developers if (bits(machInst, 24) == 0) 21810037SARM gem5 Developers return new Cbz64(machInst, imm, rt); 21910037SARM gem5 Developers else 22010037SARM gem5 Developers return new Cbnz64(machInst, imm, rt); 22110037SARM gem5 Developers } else { 22210037SARM gem5 Developers uint64_t bitmask = 0x1; 22310037SARM gem5 Developers bitmask <<= bits(machInst, 23, 19); 22410037SARM gem5 Developers int64_t imm = sext<14>(bits(machInst, 18, 5)) << 2; 22510037SARM gem5 Developers if (bits(machInst, 31)) 22610037SARM gem5 Developers bitmask <<= 32; 22710037SARM gem5 Developers if (bits(machInst, 24) == 0) 22810037SARM gem5 Developers return new Tbz64(machInst, bitmask, imm, rt); 22910037SARM gem5 Developers else 23010037SARM gem5 Developers return new Tbnz64(machInst, bitmask, imm, rt); 23110037SARM gem5 Developers } 23210037SARM gem5 Developers } 23310037SARM gem5 Developers case 0x2: 23410037SARM gem5 Developers // bit 30:26=10101 23510037SARM gem5 Developers if (bits(machInst, 31) == 0) { 23610037SARM gem5 Developers if (bits(machInst, 25, 24) || bits(machInst, 4)) 23710037SARM gem5 Developers return new Unknown64(machInst); 23810037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 23910037SARM gem5 Developers ConditionCode condCode = 24010037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 3, 0)); 24110037SARM gem5 Developers return new BCond64(machInst, imm, condCode); 24210037SARM gem5 Developers } else if (bits(machInst, 25, 24) == 0x0) { 24310037SARM gem5 Developers if (bits(machInst, 4, 2)) 24410037SARM gem5 Developers return new Unknown64(machInst); 24510037SARM gem5 Developers uint8_t decVal = (bits(machInst, 1, 0) << 0) | 24610037SARM gem5 Developers (bits(machInst, 23, 21) << 2); 24710037SARM gem5 Developers switch (decVal) { 24810037SARM gem5 Developers case 0x01: 24910037SARM gem5 Developers return new Svc64(machInst); 25010037SARM gem5 Developers case 0x02: 25110037SARM gem5 Developers return new FailUnimplemented("hvc", machInst); 25210037SARM gem5 Developers case 0x03: 25310037SARM gem5 Developers return new Smc64(machInst); 25410037SARM gem5 Developers case 0x04: 25510037SARM gem5 Developers return new FailUnimplemented("brk", machInst); 25610037SARM gem5 Developers case 0x08: 25710037SARM gem5 Developers return new FailUnimplemented("hlt", machInst); 25810037SARM gem5 Developers case 0x15: 25910037SARM gem5 Developers return new FailUnimplemented("dcps1", machInst); 26010037SARM gem5 Developers case 0x16: 26110037SARM gem5 Developers return new FailUnimplemented("dcps2", machInst); 26210037SARM gem5 Developers case 0x17: 26310037SARM gem5 Developers return new FailUnimplemented("dcps3", machInst); 26410037SARM gem5 Developers default: 26510037SARM gem5 Developers return new Unknown64(machInst); 26610037SARM gem5 Developers } 26710037SARM gem5 Developers } else if (bits(machInst, 25, 22) == 0x4) { 26810037SARM gem5 Developers // bit 31:22=1101010100 26910037SARM gem5 Developers bool l = bits(machInst, 21); 27010037SARM gem5 Developers uint8_t op0 = bits(machInst, 20, 19); 27110037SARM gem5 Developers uint8_t op1 = bits(machInst, 18, 16); 27210037SARM gem5 Developers uint8_t crn = bits(machInst, 15, 12); 27310037SARM gem5 Developers uint8_t crm = bits(machInst, 11, 8); 27410037SARM gem5 Developers uint8_t op2 = bits(machInst, 7, 5); 27510037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 27610037SARM gem5 Developers switch (op0) { 27710037SARM gem5 Developers case 0x0: 27810037SARM gem5 Developers if (rt != 0x1f || l) 27910037SARM gem5 Developers return new Unknown64(machInst); 28010037SARM gem5 Developers if (crn == 0x2 && op1 == 0x3) { 28110037SARM gem5 Developers switch (op2) { 28210037SARM gem5 Developers case 0x0: 28310037SARM gem5 Developers return new NopInst(machInst); 28410037SARM gem5 Developers case 0x1: 28510037SARM gem5 Developers return new YieldInst(machInst); 28610037SARM gem5 Developers case 0x2: 28710037SARM gem5 Developers return new WfeInst(machInst); 28810037SARM gem5 Developers case 0x3: 28910037SARM gem5 Developers return new WfiInst(machInst); 29010037SARM gem5 Developers case 0x4: 29110037SARM gem5 Developers return new SevInst(machInst); 29210037SARM gem5 Developers case 0x5: 29310037SARM gem5 Developers return new SevlInst(machInst); 29410037SARM gem5 Developers default: 29510037SARM gem5 Developers return new Unknown64(machInst); 29610037SARM gem5 Developers } 29710037SARM gem5 Developers } else if (crn == 0x3 && op1 == 0x3) { 29810037SARM gem5 Developers switch (op2) { 29910037SARM gem5 Developers case 0x2: 30010037SARM gem5 Developers return new Clrex64(machInst); 30110037SARM gem5 Developers case 0x4: 30210037SARM gem5 Developers return new Dsb64(machInst); 30310037SARM gem5 Developers case 0x5: 30410037SARM gem5 Developers return new Dmb64(machInst); 30510037SARM gem5 Developers case 0x6: 30610037SARM gem5 Developers return new Isb64(machInst); 30710037SARM gem5 Developers default: 30810037SARM gem5 Developers return new Unknown64(machInst); 30910037SARM gem5 Developers } 31010037SARM gem5 Developers } else if (crn == 0x4) { 31110037SARM gem5 Developers // MSR immediate 31210037SARM gem5 Developers switch (op1 << 3 | op2) { 31310037SARM gem5 Developers case 0x5: 31410037SARM gem5 Developers // SP 31510037SARM gem5 Developers return new MsrSP64(machInst, 31610037SARM gem5 Developers (IntRegIndex) MISCREG_SPSEL, 31710037SARM gem5 Developers INTREG_ZERO, 31810037SARM gem5 Developers crm & 0x1); 31910037SARM gem5 Developers case 0x1e: 32010037SARM gem5 Developers // DAIFSet 32110037SARM gem5 Developers return new MsrDAIFSet64( 32210037SARM gem5 Developers machInst, 32310037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 32410037SARM gem5 Developers INTREG_ZERO, 32510037SARM gem5 Developers crm); 32610037SARM gem5 Developers case 0x1f: 32710037SARM gem5 Developers // DAIFClr 32810037SARM gem5 Developers return new MsrDAIFClr64( 32910037SARM gem5 Developers machInst, 33010037SARM gem5 Developers (IntRegIndex) MISCREG_DAIF, 33110037SARM gem5 Developers INTREG_ZERO, 33210037SARM gem5 Developers crm); 33310037SARM gem5 Developers default: 33410037SARM gem5 Developers return new Unknown64(machInst); 33510037SARM gem5 Developers } 33610037SARM gem5 Developers } else { 33710037SARM gem5 Developers return new Unknown64(machInst); 33810037SARM gem5 Developers } 33910037SARM gem5 Developers break; 34010037SARM gem5 Developers case 0x1: 34110037SARM gem5 Developers case 0x2: 34210037SARM gem5 Developers case 0x3: 34310037SARM gem5 Developers { 34410037SARM gem5 Developers // bit 31:22=1101010100, 20:19=11 34510037SARM gem5 Developers bool read = l; 34610037SARM gem5 Developers MiscRegIndex miscReg = 34710037SARM gem5 Developers decodeAArch64SysReg(op0, op1, crn, crm, op2); 34810037SARM gem5 Developers if (read) { 34910037SARM gem5 Developers if ((miscReg == MISCREG_DC_CIVAC_Xt) || 35010037SARM gem5 Developers (miscReg == MISCREG_DC_CVAC_Xt) || 35110037SARM gem5 Developers (miscReg == MISCREG_DC_ZVA_Xt)) { 35210037SARM gem5 Developers return new Unknown64(machInst); 35310037SARM gem5 Developers } 35410037SARM gem5 Developers } 35510037SARM gem5 Developers // Check for invalid registers 35610037SARM gem5 Developers if (miscReg == MISCREG_UNKNOWN) { 35710037SARM gem5 Developers return new Unknown64(machInst); 35810037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { 35910037SARM gem5 Developers if (miscReg == MISCREG_NZCV) { 36010037SARM gem5 Developers if (read) 36110037SARM gem5 Developers return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg); 36210037SARM gem5 Developers else 36310037SARM gem5 Developers return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt); 36410037SARM gem5 Developers } 36510037SARM gem5 Developers uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt); 36610037SARM gem5 Developers if (miscReg == MISCREG_DC_ZVA_Xt && !read) 36710037SARM gem5 Developers return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); 36810037SARM gem5 Developers 36910506SAli.Saidi@ARM.com if (read) { 37010506SAli.Saidi@ARM.com StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); 37110506SAli.Saidi@ARM.com if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) 37210506SAli.Saidi@ARM.com si->setFlag(StaticInst::IsUnverifiable); 37310506SAli.Saidi@ARM.com return si; 37410506SAli.Saidi@ARM.com } else 37510037SARM gem5 Developers return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); 37610037SARM gem5 Developers } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { 37710037SARM gem5 Developers std::string full_mnem = csprintf("%s %s", 37810037SARM gem5 Developers read ? "mrs" : "msr", miscRegName[miscReg]); 37910037SARM gem5 Developers return new WarnUnimplemented(read ? "mrs" : "msr", 38010037SARM gem5 Developers machInst, full_mnem); 38110037SARM gem5 Developers } else { 38210173SMitchell.Hayenga@ARM.com return new FailUnimplemented(read ? "mrs" : "msr", 38310173SMitchell.Hayenga@ARM.com machInst, 38410173SMitchell.Hayenga@ARM.com csprintf("%s %s", 38510173SMitchell.Hayenga@ARM.com read ? "mrs" : "msr", 38610173SMitchell.Hayenga@ARM.com miscRegName[miscReg])); 38710037SARM gem5 Developers } 38810037SARM gem5 Developers } 38910037SARM gem5 Developers break; 39010037SARM gem5 Developers } 39110037SARM gem5 Developers } else if (bits(machInst, 25) == 0x1) { 39210037SARM gem5 Developers uint8_t opc = bits(machInst, 24, 21); 39310037SARM gem5 Developers uint8_t op2 = bits(machInst, 20, 16); 39410037SARM gem5 Developers uint8_t op3 = bits(machInst, 15, 10); 39510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 39610037SARM gem5 Developers uint8_t op4 = bits(machInst, 4, 0); 39710037SARM gem5 Developers if (op2 != 0x1f || op3 != 0x0 || op4 != 0x0) 39810037SARM gem5 Developers return new Unknown64(machInst); 39910037SARM gem5 Developers switch (opc) { 40010037SARM gem5 Developers case 0x0: 40110037SARM gem5 Developers return new Br64(machInst, rn); 40210037SARM gem5 Developers case 0x1: 40310037SARM gem5 Developers return new Blr64(machInst, rn); 40410037SARM gem5 Developers case 0x2: 40510037SARM gem5 Developers return new Ret64(machInst, rn); 40610037SARM gem5 Developers case 0x4: 40710037SARM gem5 Developers if (rn != 0x1f) 40810037SARM gem5 Developers return new Unknown64(machInst); 40910037SARM gem5 Developers return new Eret64(machInst); 41010037SARM gem5 Developers case 0x5: 41110037SARM gem5 Developers if (rn != 0x1f) 41210037SARM gem5 Developers return new Unknown64(machInst); 41310037SARM gem5 Developers return new FailUnimplemented("dret", machInst); 41410037SARM gem5 Developers } 41510037SARM gem5 Developers } 41610037SARM gem5 Developers default: 41710037SARM gem5 Developers return new Unknown64(machInst); 41810037SARM gem5 Developers } 41910037SARM gem5 Developers return new FailUnimplemented("Unhandled Case7", machInst); 42010037SARM gem5 Developers } 42110037SARM gem5 Developers} 42210037SARM gem5 Developers}}; 42310037SARM gem5 Developers 42410037SARM gem5 Developersoutput decoder {{ 42510037SARM gem5 Developersnamespace Aarch64 42610037SARM gem5 Developers{ 42710037SARM gem5 Developers StaticInstPtr 42810037SARM gem5 Developers decodeLoadsStores(ExtMachInst machInst) 42910037SARM gem5 Developers { 43010037SARM gem5 Developers // bit 27,25=10 43110037SARM gem5 Developers switch (bits(machInst, 29, 28)) { 43210037SARM gem5 Developers case 0x0: 43310037SARM gem5 Developers if (bits(machInst, 26) == 0) { 43410037SARM gem5 Developers if (bits(machInst, 24) != 0) 43510037SARM gem5 Developers return new Unknown64(machInst); 43610037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 43710037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 43810037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 43910037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 44010037SARM gem5 Developers IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 44110037SARM gem5 Developers uint8_t opc = (bits(machInst, 15) << 0) | 44210037SARM gem5 Developers (bits(machInst, 23, 21) << 1); 44310037SARM gem5 Developers uint8_t size = bits(machInst, 31, 30); 44410037SARM gem5 Developers switch (opc) { 44510037SARM gem5 Developers case 0x0: 44610037SARM gem5 Developers switch (size) { 44710037SARM gem5 Developers case 0x0: 44810037SARM gem5 Developers return new STXRB64(machInst, rt, rnsp, rs); 44910037SARM gem5 Developers case 0x1: 45010037SARM gem5 Developers return new STXRH64(machInst, rt, rnsp, rs); 45110037SARM gem5 Developers case 0x2: 45210037SARM gem5 Developers return new STXRW64(machInst, rt, rnsp, rs); 45310037SARM gem5 Developers case 0x3: 45410037SARM gem5 Developers return new STXRX64(machInst, rt, rnsp, rs); 45510037SARM gem5 Developers } 45610037SARM gem5 Developers case 0x1: 45710037SARM gem5 Developers switch (size) { 45810037SARM gem5 Developers case 0x0: 45910037SARM gem5 Developers return new STLXRB64(machInst, rt, rnsp, rs); 46010037SARM gem5 Developers case 0x1: 46110037SARM gem5 Developers return new STLXRH64(machInst, rt, rnsp, rs); 46210037SARM gem5 Developers case 0x2: 46310037SARM gem5 Developers return new STLXRW64(machInst, rt, rnsp, rs); 46410037SARM gem5 Developers case 0x3: 46510037SARM gem5 Developers return new STLXRX64(machInst, rt, rnsp, rs); 46610037SARM gem5 Developers } 46710037SARM gem5 Developers case 0x2: 46810037SARM gem5 Developers switch (size) { 46910037SARM gem5 Developers case 0x0: 47010037SARM gem5 Developers case 0x1: 47110037SARM gem5 Developers return new Unknown64(machInst); 47210037SARM gem5 Developers case 0x2: 47310037SARM gem5 Developers return new STXPW64(machInst, rs, rt, rt2, rnsp); 47410037SARM gem5 Developers case 0x3: 47510037SARM gem5 Developers return new STXPX64(machInst, rs, rt, rt2, rnsp); 47610037SARM gem5 Developers } 47710037SARM gem5 Developers 47810037SARM gem5 Developers case 0x3: 47910037SARM gem5 Developers switch (size) { 48010037SARM gem5 Developers case 0x0: 48110037SARM gem5 Developers case 0x1: 48210037SARM gem5 Developers return new Unknown64(machInst); 48310037SARM gem5 Developers case 0x2: 48410037SARM gem5 Developers return new STLXPW64(machInst, rs, rt, rt2, rnsp); 48510037SARM gem5 Developers case 0x3: 48610037SARM gem5 Developers return new STLXPX64(machInst, rs, rt, rt2, rnsp); 48710037SARM gem5 Developers } 48810037SARM gem5 Developers 48910037SARM gem5 Developers case 0x4: 49010037SARM gem5 Developers switch (size) { 49110037SARM gem5 Developers case 0x0: 49210037SARM gem5 Developers return new LDXRB64(machInst, rt, rnsp, rs); 49310037SARM gem5 Developers case 0x1: 49410037SARM gem5 Developers return new LDXRH64(machInst, rt, rnsp, rs); 49510037SARM gem5 Developers case 0x2: 49610037SARM gem5 Developers return new LDXRW64(machInst, rt, rnsp, rs); 49710037SARM gem5 Developers case 0x3: 49810037SARM gem5 Developers return new LDXRX64(machInst, rt, rnsp, rs); 49910037SARM gem5 Developers } 50010037SARM gem5 Developers case 0x5: 50110037SARM gem5 Developers switch (size) { 50210037SARM gem5 Developers case 0x0: 50310037SARM gem5 Developers return new LDAXRB64(machInst, rt, rnsp, rs); 50410037SARM gem5 Developers case 0x1: 50510037SARM gem5 Developers return new LDAXRH64(machInst, rt, rnsp, rs); 50610037SARM gem5 Developers case 0x2: 50710037SARM gem5 Developers return new LDAXRW64(machInst, rt, rnsp, rs); 50810037SARM gem5 Developers case 0x3: 50910037SARM gem5 Developers return new LDAXRX64(machInst, rt, rnsp, rs); 51010037SARM gem5 Developers } 51110037SARM gem5 Developers case 0x6: 51210037SARM gem5 Developers switch (size) { 51310037SARM gem5 Developers case 0x0: 51410037SARM gem5 Developers case 0x1: 51510037SARM gem5 Developers return new Unknown64(machInst); 51610037SARM gem5 Developers case 0x2: 51710037SARM gem5 Developers return new LDXPW64(machInst, rt, rt2, rnsp); 51810037SARM gem5 Developers case 0x3: 51910037SARM gem5 Developers return new LDXPX64(machInst, rt, rt2, rnsp); 52010037SARM gem5 Developers } 52110037SARM gem5 Developers 52210037SARM gem5 Developers case 0x7: 52310037SARM gem5 Developers switch (size) { 52410037SARM gem5 Developers case 0x0: 52510037SARM gem5 Developers case 0x1: 52610037SARM gem5 Developers return new Unknown64(machInst); 52710037SARM gem5 Developers case 0x2: 52810037SARM gem5 Developers return new LDAXPW64(machInst, rt, rt2, rnsp); 52910037SARM gem5 Developers case 0x3: 53010037SARM gem5 Developers return new LDAXPX64(machInst, rt, rt2, rnsp); 53110037SARM gem5 Developers } 53210037SARM gem5 Developers 53310037SARM gem5 Developers case 0x9: 53410037SARM gem5 Developers switch (size) { 53510037SARM gem5 Developers case 0x0: 53610037SARM gem5 Developers return new STLRB64(machInst, rt, rnsp); 53710037SARM gem5 Developers case 0x1: 53810037SARM gem5 Developers return new STLRH64(machInst, rt, rnsp); 53910037SARM gem5 Developers case 0x2: 54010037SARM gem5 Developers return new STLRW64(machInst, rt, rnsp); 54110037SARM gem5 Developers case 0x3: 54210037SARM gem5 Developers return new STLRX64(machInst, rt, rnsp); 54310037SARM gem5 Developers } 54410037SARM gem5 Developers case 0xd: 54510037SARM gem5 Developers switch (size) { 54610037SARM gem5 Developers case 0x0: 54710037SARM gem5 Developers return new LDARB64(machInst, rt, rnsp); 54810037SARM gem5 Developers case 0x1: 54910037SARM gem5 Developers return new LDARH64(machInst, rt, rnsp); 55010037SARM gem5 Developers case 0x2: 55110037SARM gem5 Developers return new LDARW64(machInst, rt, rnsp); 55210037SARM gem5 Developers case 0x3: 55310037SARM gem5 Developers return new LDARX64(machInst, rt, rnsp); 55410037SARM gem5 Developers } 55510037SARM gem5 Developers default: 55610037SARM gem5 Developers return new Unknown64(machInst); 55710037SARM gem5 Developers } 55810037SARM gem5 Developers } else if (bits(machInst, 31)) { 55910037SARM gem5 Developers return new Unknown64(machInst); 56010037SARM gem5 Developers } else { 56110037SARM gem5 Developers return decodeNeonMem(machInst); 56210037SARM gem5 Developers } 56310037SARM gem5 Developers case 0x1: 56410037SARM gem5 Developers { 56510037SARM gem5 Developers if (bits(machInst, 24) != 0) 56610037SARM gem5 Developers return new Unknown64(machInst); 56710037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 26) << 0) | 56810037SARM gem5 Developers (bits(machInst, 31, 30) << 1); 56910037SARM gem5 Developers int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2; 57010037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 57110037SARM gem5 Developers switch (switchVal) { 57210037SARM gem5 Developers case 0x0: 57310037SARM gem5 Developers return new LDRWL64_LIT(machInst, rt, imm); 57410037SARM gem5 Developers case 0x1: 57510037SARM gem5 Developers return new LDRSFP64_LIT(machInst, rt, imm); 57610037SARM gem5 Developers case 0x2: 57710037SARM gem5 Developers return new LDRXL64_LIT(machInst, rt, imm); 57810037SARM gem5 Developers case 0x3: 57910037SARM gem5 Developers return new LDRDFP64_LIT(machInst, rt, imm); 58010037SARM gem5 Developers case 0x4: 58110037SARM gem5 Developers return new LDRSWL64_LIT(machInst, rt, imm); 58210037SARM gem5 Developers case 0x5: 58310037SARM gem5 Developers return new BigFpMemLit("ldr", machInst, rt, imm); 58410037SARM gem5 Developers case 0x6: 58510037SARM gem5 Developers return new PRFM64_LIT(machInst, rt, imm); 58610037SARM gem5 Developers default: 58710037SARM gem5 Developers return new Unknown64(machInst); 58810037SARM gem5 Developers } 58910037SARM gem5 Developers } 59010037SARM gem5 Developers case 0x2: 59110037SARM gem5 Developers { 59210037SARM gem5 Developers uint8_t opc = bits(machInst, 31, 30); 59310037SARM gem5 Developers if (opc >= 3) 59410037SARM gem5 Developers return new Unknown64(machInst); 59510037SARM gem5 Developers uint32_t size = 0; 59610037SARM gem5 Developers bool fp = bits(machInst, 26); 59710037SARM gem5 Developers bool load = bits(machInst, 22); 59810037SARM gem5 Developers if (fp) { 59910037SARM gem5 Developers size = 4 << opc; 60010037SARM gem5 Developers } else { 60110037SARM gem5 Developers if ((opc == 1) && !load) 60210037SARM gem5 Developers return new Unknown64(machInst); 60310037SARM gem5 Developers size = (opc == 0 || opc == 1) ? 4 : 8; 60410037SARM gem5 Developers } 60510037SARM gem5 Developers uint8_t type = bits(machInst, 24, 23); 60610037SARM gem5 Developers int64_t imm = sext<7>(bits(machInst, 21, 15)) * size; 60710037SARM gem5 Developers 60810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 60910037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 61010037SARM gem5 Developers IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 61110037SARM gem5 Developers 61210037SARM gem5 Developers bool noAlloc = (type == 0); 61310037SARM gem5 Developers bool signExt = !noAlloc && !fp && opc == 1; 61410037SARM gem5 Developers PairMemOp::AddrMode mode; 61510037SARM gem5 Developers const char *mnemonic = NULL; 61610037SARM gem5 Developers switch (type) { 61710037SARM gem5 Developers case 0x0: 61810037SARM gem5 Developers case 0x2: 61910037SARM gem5 Developers mode = PairMemOp::AddrMd_Offset; 62010037SARM gem5 Developers break; 62110037SARM gem5 Developers case 0x1: 62210037SARM gem5 Developers mode = PairMemOp::AddrMd_PostIndex; 62310037SARM gem5 Developers break; 62410037SARM gem5 Developers case 0x3: 62510037SARM gem5 Developers mode = PairMemOp::AddrMd_PreIndex; 62610037SARM gem5 Developers break; 62710037SARM gem5 Developers default: 62810037SARM gem5 Developers return new Unknown64(machInst); 62910037SARM gem5 Developers } 63010037SARM gem5 Developers if (load) { 63110037SARM gem5 Developers if (noAlloc) 63210037SARM gem5 Developers mnemonic = "ldnp"; 63310037SARM gem5 Developers else if (signExt) 63410037SARM gem5 Developers mnemonic = "ldpsw"; 63510037SARM gem5 Developers else 63610037SARM gem5 Developers mnemonic = "ldp"; 63710037SARM gem5 Developers } else { 63810037SARM gem5 Developers if (noAlloc) 63910037SARM gem5 Developers mnemonic = "stnp"; 64010037SARM gem5 Developers else 64110037SARM gem5 Developers mnemonic = "stp"; 64210037SARM gem5 Developers } 64310037SARM gem5 Developers 64410037SARM gem5 Developers return new LdpStp(mnemonic, machInst, size, fp, load, noAlloc, 64510037SARM gem5 Developers signExt, false, false, imm, mode, rn, rt, rt2); 64610037SARM gem5 Developers } 64710037SARM gem5 Developers // bit 29:27=111, 25=0 64810037SARM gem5 Developers case 0x3: 64910037SARM gem5 Developers { 65010037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 22) << 0) | 65110037SARM gem5 Developers (bits(machInst, 26) << 2) | 65210037SARM gem5 Developers (bits(machInst, 31, 30) << 3); 65310037SARM gem5 Developers if (bits(machInst, 24) == 1) { 65410037SARM gem5 Developers uint64_t imm12 = bits(machInst, 21, 10); 65510037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 65610037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 65710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 65810037SARM gem5 Developers switch (switchVal) { 65910037SARM gem5 Developers case 0x00: 66010037SARM gem5 Developers return new STRB64_IMM(machInst, rt, rnsp, imm12); 66110037SARM gem5 Developers case 0x01: 66210037SARM gem5 Developers return new LDRB64_IMM(machInst, rt, rnsp, imm12); 66310037SARM gem5 Developers case 0x02: 66410037SARM gem5 Developers return new LDRSBX64_IMM(machInst, rt, rnsp, imm12); 66510037SARM gem5 Developers case 0x03: 66610037SARM gem5 Developers return new LDRSBW64_IMM(machInst, rt, rnsp, imm12); 66710037SARM gem5 Developers case 0x04: 66810037SARM gem5 Developers return new STRBFP64_IMM(machInst, rt, rnsp, imm12); 66910037SARM gem5 Developers case 0x05: 67010037SARM gem5 Developers return new LDRBFP64_IMM(machInst, rt, rnsp, imm12); 67110037SARM gem5 Developers case 0x06: 67210037SARM gem5 Developers return new BigFpMemImm("str", machInst, false, 67310037SARM gem5 Developers rt, rnsp, imm12 << 4); 67410037SARM gem5 Developers case 0x07: 67510037SARM gem5 Developers return new BigFpMemImm("ldr", machInst, true, 67610037SARM gem5 Developers rt, rnsp, imm12 << 4); 67710037SARM gem5 Developers case 0x08: 67810037SARM gem5 Developers return new STRH64_IMM(machInst, rt, rnsp, imm12 << 1); 67910037SARM gem5 Developers case 0x09: 68010037SARM gem5 Developers return new LDRH64_IMM(machInst, rt, rnsp, imm12 << 1); 68110037SARM gem5 Developers case 0x0a: 68210037SARM gem5 Developers return new LDRSHX64_IMM(machInst, rt, rnsp, imm12 << 1); 68310037SARM gem5 Developers case 0x0b: 68410037SARM gem5 Developers return new LDRSHW64_IMM(machInst, rt, rnsp, imm12 << 1); 68510037SARM gem5 Developers case 0x0c: 68610037SARM gem5 Developers return new STRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 68710037SARM gem5 Developers case 0x0d: 68810037SARM gem5 Developers return new LDRHFP64_IMM(machInst, rt, rnsp, imm12 << 1); 68910037SARM gem5 Developers case 0x10: 69010037SARM gem5 Developers return new STRW64_IMM(machInst, rt, rnsp, imm12 << 2); 69110037SARM gem5 Developers case 0x11: 69210037SARM gem5 Developers return new LDRW64_IMM(machInst, rt, rnsp, imm12 << 2); 69310037SARM gem5 Developers case 0x12: 69410037SARM gem5 Developers return new LDRSW64_IMM(machInst, rt, rnsp, imm12 << 2); 69510037SARM gem5 Developers case 0x14: 69610037SARM gem5 Developers return new STRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 69710037SARM gem5 Developers case 0x15: 69810037SARM gem5 Developers return new LDRSFP64_IMM(machInst, rt, rnsp, imm12 << 2); 69910037SARM gem5 Developers case 0x18: 70010037SARM gem5 Developers return new STRX64_IMM(machInst, rt, rnsp, imm12 << 3); 70110037SARM gem5 Developers case 0x19: 70210037SARM gem5 Developers return new LDRX64_IMM(machInst, rt, rnsp, imm12 << 3); 70310037SARM gem5 Developers case 0x1a: 70410037SARM gem5 Developers return new PRFM64_IMM(machInst, rt, rnsp, imm12 << 3); 70510037SARM gem5 Developers case 0x1c: 70610037SARM gem5 Developers return new STRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 70710037SARM gem5 Developers case 0x1d: 70810037SARM gem5 Developers return new LDRDFP64_IMM(machInst, rt, rnsp, imm12 << 3); 70910037SARM gem5 Developers default: 71010037SARM gem5 Developers return new Unknown64(machInst); 71110037SARM gem5 Developers } 71210037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 71310037SARM gem5 Developers if (bits(machInst, 11, 10) != 0x2) 71410037SARM gem5 Developers return new Unknown64(machInst); 71510037SARM gem5 Developers if (!bits(machInst, 14)) 71610037SARM gem5 Developers return new Unknown64(machInst); 71710037SARM gem5 Developers IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 71810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 71910037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 72010037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 72110037SARM gem5 Developers ArmExtendType type = 72210037SARM gem5 Developers (ArmExtendType)(uint32_t)bits(machInst, 15, 13); 72310037SARM gem5 Developers uint8_t s = bits(machInst, 12); 72410037SARM gem5 Developers switch (switchVal) { 72510037SARM gem5 Developers case 0x00: 72610037SARM gem5 Developers return new STRB64_REG(machInst, rt, rnsp, rm, type, 0); 72710037SARM gem5 Developers case 0x01: 72810037SARM gem5 Developers return new LDRB64_REG(machInst, rt, rnsp, rm, type, 0); 72910037SARM gem5 Developers case 0x02: 73010037SARM gem5 Developers return new LDRSBX64_REG(machInst, rt, rnsp, rm, type, 0); 73110037SARM gem5 Developers case 0x03: 73210037SARM gem5 Developers return new LDRSBW64_REG(machInst, rt, rnsp, rm, type, 0); 73310037SARM gem5 Developers case 0x04: 73410037SARM gem5 Developers return new STRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 73510037SARM gem5 Developers case 0x05: 73610037SARM gem5 Developers return new LDRBFP64_REG(machInst, rt, rnsp, rm, type, 0); 73710037SARM gem5 Developers case 0x6: 73810037SARM gem5 Developers return new BigFpMemReg("str", machInst, false, 73910037SARM gem5 Developers rt, rnsp, rm, type, s * 4); 74010037SARM gem5 Developers case 0x7: 74110037SARM gem5 Developers return new BigFpMemReg("ldr", machInst, true, 74210037SARM gem5 Developers rt, rnsp, rm, type, s * 4); 74310037SARM gem5 Developers case 0x08: 74410037SARM gem5 Developers return new STRH64_REG(machInst, rt, rnsp, rm, type, s); 74510037SARM gem5 Developers case 0x09: 74610037SARM gem5 Developers return new LDRH64_REG(machInst, rt, rnsp, rm, type, s); 74710037SARM gem5 Developers case 0x0a: 74810037SARM gem5 Developers return new LDRSHX64_REG(machInst, rt, rnsp, rm, type, s); 74910037SARM gem5 Developers case 0x0b: 75010037SARM gem5 Developers return new LDRSHW64_REG(machInst, rt, rnsp, rm, type, s); 75110037SARM gem5 Developers case 0x0c: 75210037SARM gem5 Developers return new STRHFP64_REG(machInst, rt, rnsp, rm, type, s); 75310037SARM gem5 Developers case 0x0d: 75410037SARM gem5 Developers return new LDRHFP64_REG(machInst, rt, rnsp, rm, type, s); 75510037SARM gem5 Developers case 0x10: 75610037SARM gem5 Developers return new STRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 75710037SARM gem5 Developers case 0x11: 75810037SARM gem5 Developers return new LDRW64_REG(machInst, rt, rnsp, rm, type, s * 2); 75910037SARM gem5 Developers case 0x12: 76010037SARM gem5 Developers return new LDRSW64_REG(machInst, rt, rnsp, rm, type, s * 2); 76110037SARM gem5 Developers case 0x14: 76210037SARM gem5 Developers return new STRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 76310037SARM gem5 Developers case 0x15: 76410037SARM gem5 Developers return new LDRSFP64_REG(machInst, rt, rnsp, rm, type, s * 2); 76510037SARM gem5 Developers case 0x18: 76610037SARM gem5 Developers return new STRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 76710037SARM gem5 Developers case 0x19: 76810037SARM gem5 Developers return new LDRX64_REG(machInst, rt, rnsp, rm, type, s * 3); 76910037SARM gem5 Developers case 0x1a: 77010037SARM gem5 Developers return new PRFM64_REG(machInst, rt, rnsp, rm, type, s * 3); 77110037SARM gem5 Developers case 0x1c: 77210037SARM gem5 Developers return new STRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 77310037SARM gem5 Developers case 0x1d: 77410037SARM gem5 Developers return new LDRDFP64_REG(machInst, rt, rnsp, rm, type, s * 3); 77510037SARM gem5 Developers default: 77610037SARM gem5 Developers return new Unknown64(machInst); 77710037SARM gem5 Developers } 77810037SARM gem5 Developers } else { 77910037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0 78010037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 78110037SARM gem5 Developers case 0x0: 78210037SARM gem5 Developers { 78310037SARM gem5 Developers IntRegIndex rt = 78410037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 78510037SARM gem5 Developers IntRegIndex rn = 78610037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 78710037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 78810037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 78910037SARM gem5 Developers switch (switchVal) { 79010037SARM gem5 Developers case 0x00: 79110037SARM gem5 Developers return new STURB64_IMM(machInst, rt, rnsp, imm); 79210037SARM gem5 Developers case 0x01: 79310037SARM gem5 Developers return new LDURB64_IMM(machInst, rt, rnsp, imm); 79410037SARM gem5 Developers case 0x02: 79510037SARM gem5 Developers return new LDURSBX64_IMM(machInst, rt, rnsp, imm); 79610037SARM gem5 Developers case 0x03: 79710037SARM gem5 Developers return new LDURSBW64_IMM(machInst, rt, rnsp, imm); 79810037SARM gem5 Developers case 0x04: 79910037SARM gem5 Developers return new STURBFP64_IMM(machInst, rt, rnsp, imm); 80010037SARM gem5 Developers case 0x05: 80110037SARM gem5 Developers return new LDURBFP64_IMM(machInst, rt, rnsp, imm); 80210037SARM gem5 Developers case 0x06: 80310037SARM gem5 Developers return new BigFpMemImm("stur", machInst, false, 80410037SARM gem5 Developers rt, rnsp, imm); 80510037SARM gem5 Developers case 0x07: 80610037SARM gem5 Developers return new BigFpMemImm("ldur", machInst, true, 80710037SARM gem5 Developers rt, rnsp, imm); 80810037SARM gem5 Developers case 0x08: 80910037SARM gem5 Developers return new STURH64_IMM(machInst, rt, rnsp, imm); 81010037SARM gem5 Developers case 0x09: 81110037SARM gem5 Developers return new LDURH64_IMM(machInst, rt, rnsp, imm); 81210037SARM gem5 Developers case 0x0a: 81310037SARM gem5 Developers return new LDURSHX64_IMM(machInst, rt, rnsp, imm); 81410037SARM gem5 Developers case 0x0b: 81510037SARM gem5 Developers return new LDURSHW64_IMM(machInst, rt, rnsp, imm); 81610037SARM gem5 Developers case 0x0c: 81710037SARM gem5 Developers return new STURHFP64_IMM(machInst, rt, rnsp, imm); 81810037SARM gem5 Developers case 0x0d: 81910037SARM gem5 Developers return new LDURHFP64_IMM(machInst, rt, rnsp, imm); 82010037SARM gem5 Developers case 0x10: 82110037SARM gem5 Developers return new STURW64_IMM(machInst, rt, rnsp, imm); 82210037SARM gem5 Developers case 0x11: 82310037SARM gem5 Developers return new LDURW64_IMM(machInst, rt, rnsp, imm); 82410037SARM gem5 Developers case 0x12: 82510037SARM gem5 Developers return new LDURSW64_IMM(machInst, rt, rnsp, imm); 82610037SARM gem5 Developers case 0x14: 82710037SARM gem5 Developers return new STURSFP64_IMM(machInst, rt, rnsp, imm); 82810037SARM gem5 Developers case 0x15: 82910037SARM gem5 Developers return new LDURSFP64_IMM(machInst, rt, rnsp, imm); 83010037SARM gem5 Developers case 0x18: 83110037SARM gem5 Developers return new STURX64_IMM(machInst, rt, rnsp, imm); 83210037SARM gem5 Developers case 0x19: 83310037SARM gem5 Developers return new LDURX64_IMM(machInst, rt, rnsp, imm); 83410037SARM gem5 Developers case 0x1a: 83510037SARM gem5 Developers return new PRFUM64_IMM(machInst, rt, rnsp, imm); 83610037SARM gem5 Developers case 0x1c: 83710037SARM gem5 Developers return new STURDFP64_IMM(machInst, rt, rnsp, imm); 83810037SARM gem5 Developers case 0x1d: 83910037SARM gem5 Developers return new LDURDFP64_IMM(machInst, rt, rnsp, imm); 84010037SARM gem5 Developers default: 84110037SARM gem5 Developers return new Unknown64(machInst); 84210037SARM gem5 Developers } 84310037SARM gem5 Developers } 84410037SARM gem5 Developers // bit 29:27=111, 25:24=00, 21=0, 11:10=01 84510037SARM gem5 Developers case 0x1: 84610037SARM gem5 Developers { 84710037SARM gem5 Developers IntRegIndex rt = 84810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 84910037SARM gem5 Developers IntRegIndex rn = 85010037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 85110037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 85210037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 85310037SARM gem5 Developers switch (switchVal) { 85410037SARM gem5 Developers case 0x00: 85510037SARM gem5 Developers return new STRB64_POST(machInst, rt, rnsp, imm); 85610037SARM gem5 Developers case 0x01: 85710037SARM gem5 Developers return new LDRB64_POST(machInst, rt, rnsp, imm); 85810037SARM gem5 Developers case 0x02: 85910037SARM gem5 Developers return new LDRSBX64_POST(machInst, rt, rnsp, imm); 86010037SARM gem5 Developers case 0x03: 86110037SARM gem5 Developers return new LDRSBW64_POST(machInst, rt, rnsp, imm); 86210037SARM gem5 Developers case 0x04: 86310037SARM gem5 Developers return new STRBFP64_POST(machInst, rt, rnsp, imm); 86410037SARM gem5 Developers case 0x05: 86510037SARM gem5 Developers return new LDRBFP64_POST(machInst, rt, rnsp, imm); 86610037SARM gem5 Developers case 0x06: 86710037SARM gem5 Developers return new BigFpMemPost("str", machInst, false, 86810037SARM gem5 Developers rt, rnsp, imm); 86910037SARM gem5 Developers case 0x07: 87010037SARM gem5 Developers return new BigFpMemPost("ldr", machInst, true, 87110037SARM gem5 Developers rt, rnsp, imm); 87210037SARM gem5 Developers case 0x08: 87310037SARM gem5 Developers return new STRH64_POST(machInst, rt, rnsp, imm); 87410037SARM gem5 Developers case 0x09: 87510037SARM gem5 Developers return new LDRH64_POST(machInst, rt, rnsp, imm); 87610037SARM gem5 Developers case 0x0a: 87710037SARM gem5 Developers return new LDRSHX64_POST(machInst, rt, rnsp, imm); 87810037SARM gem5 Developers case 0x0b: 87910037SARM gem5 Developers return new LDRSHW64_POST(machInst, rt, rnsp, imm); 88010037SARM gem5 Developers case 0x0c: 88110037SARM gem5 Developers return new STRHFP64_POST(machInst, rt, rnsp, imm); 88210037SARM gem5 Developers case 0x0d: 88310037SARM gem5 Developers return new LDRHFP64_POST(machInst, rt, rnsp, imm); 88410037SARM gem5 Developers case 0x10: 88510037SARM gem5 Developers return new STRW64_POST(machInst, rt, rnsp, imm); 88610037SARM gem5 Developers case 0x11: 88710037SARM gem5 Developers return new LDRW64_POST(machInst, rt, rnsp, imm); 88810037SARM gem5 Developers case 0x12: 88910037SARM gem5 Developers return new LDRSW64_POST(machInst, rt, rnsp, imm); 89010037SARM gem5 Developers case 0x14: 89110037SARM gem5 Developers return new STRSFP64_POST(machInst, rt, rnsp, imm); 89210037SARM gem5 Developers case 0x15: 89310037SARM gem5 Developers return new LDRSFP64_POST(machInst, rt, rnsp, imm); 89410037SARM gem5 Developers case 0x18: 89510037SARM gem5 Developers return new STRX64_POST(machInst, rt, rnsp, imm); 89610037SARM gem5 Developers case 0x19: 89710037SARM gem5 Developers return new LDRX64_POST(machInst, rt, rnsp, imm); 89810037SARM gem5 Developers case 0x1c: 89910037SARM gem5 Developers return new STRDFP64_POST(machInst, rt, rnsp, imm); 90010037SARM gem5 Developers case 0x1d: 90110037SARM gem5 Developers return new LDRDFP64_POST(machInst, rt, rnsp, imm); 90210037SARM gem5 Developers default: 90310037SARM gem5 Developers return new Unknown64(machInst); 90410037SARM gem5 Developers } 90510037SARM gem5 Developers } 90610037SARM gem5 Developers case 0x2: 90710037SARM gem5 Developers { 90810037SARM gem5 Developers IntRegIndex rt = 90910037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 91010037SARM gem5 Developers IntRegIndex rn = 91110037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 91210037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 91310037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 91410037SARM gem5 Developers switch (switchVal) { 91510037SARM gem5 Developers case 0x00: 91610037SARM gem5 Developers return new STTRB64_IMM(machInst, rt, rnsp, imm); 91710037SARM gem5 Developers case 0x01: 91810037SARM gem5 Developers return new LDTRB64_IMM(machInst, rt, rnsp, imm); 91910037SARM gem5 Developers case 0x02: 92010037SARM gem5 Developers return new LDTRSBX64_IMM(machInst, rt, rnsp, imm); 92110037SARM gem5 Developers case 0x03: 92210037SARM gem5 Developers return new LDTRSBW64_IMM(machInst, rt, rnsp, imm); 92310037SARM gem5 Developers case 0x08: 92410037SARM gem5 Developers return new STTRH64_IMM(machInst, rt, rnsp, imm); 92510037SARM gem5 Developers case 0x09: 92610037SARM gem5 Developers return new LDTRH64_IMM(machInst, rt, rnsp, imm); 92710037SARM gem5 Developers case 0x0a: 92810037SARM gem5 Developers return new LDTRSHX64_IMM(machInst, rt, rnsp, imm); 92910037SARM gem5 Developers case 0x0b: 93010037SARM gem5 Developers return new LDTRSHW64_IMM(machInst, rt, rnsp, imm); 93110037SARM gem5 Developers case 0x10: 93210037SARM gem5 Developers return new STTRW64_IMM(machInst, rt, rnsp, imm); 93310037SARM gem5 Developers case 0x11: 93410037SARM gem5 Developers return new LDTRW64_IMM(machInst, rt, rnsp, imm); 93510037SARM gem5 Developers case 0x12: 93610037SARM gem5 Developers return new LDTRSW64_IMM(machInst, rt, rnsp, imm); 93710037SARM gem5 Developers case 0x18: 93810037SARM gem5 Developers return new STTRX64_IMM(machInst, rt, rnsp, imm); 93910037SARM gem5 Developers case 0x19: 94010037SARM gem5 Developers return new LDTRX64_IMM(machInst, rt, rnsp, imm); 94110037SARM gem5 Developers default: 94210037SARM gem5 Developers return new Unknown64(machInst); 94310037SARM gem5 Developers } 94410037SARM gem5 Developers } 94510037SARM gem5 Developers case 0x3: 94610037SARM gem5 Developers { 94710037SARM gem5 Developers IntRegIndex rt = 94810037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 94910037SARM gem5 Developers IntRegIndex rn = 95010037SARM gem5 Developers (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 95110037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 95210037SARM gem5 Developers uint64_t imm = sext<9>(bits(machInst, 20, 12)); 95310037SARM gem5 Developers switch (switchVal) { 95410037SARM gem5 Developers case 0x00: 95510037SARM gem5 Developers return new STRB64_PRE(machInst, rt, rnsp, imm); 95610037SARM gem5 Developers case 0x01: 95710037SARM gem5 Developers return new LDRB64_PRE(machInst, rt, rnsp, imm); 95810037SARM gem5 Developers case 0x02: 95910037SARM gem5 Developers return new LDRSBX64_PRE(machInst, rt, rnsp, imm); 96010037SARM gem5 Developers case 0x03: 96110037SARM gem5 Developers return new LDRSBW64_PRE(machInst, rt, rnsp, imm); 96210037SARM gem5 Developers case 0x04: 96310037SARM gem5 Developers return new STRBFP64_PRE(machInst, rt, rnsp, imm); 96410037SARM gem5 Developers case 0x05: 96510037SARM gem5 Developers return new LDRBFP64_PRE(machInst, rt, rnsp, imm); 96610037SARM gem5 Developers case 0x06: 96710037SARM gem5 Developers return new BigFpMemPre("str", machInst, false, 96810037SARM gem5 Developers rt, rnsp, imm); 96910037SARM gem5 Developers case 0x07: 97010037SARM gem5 Developers return new BigFpMemPre("ldr", machInst, true, 97110037SARM gem5 Developers rt, rnsp, imm); 97210037SARM gem5 Developers case 0x08: 97310037SARM gem5 Developers return new STRH64_PRE(machInst, rt, rnsp, imm); 97410037SARM gem5 Developers case 0x09: 97510037SARM gem5 Developers return new LDRH64_PRE(machInst, rt, rnsp, imm); 97610037SARM gem5 Developers case 0x0a: 97710037SARM gem5 Developers return new LDRSHX64_PRE(machInst, rt, rnsp, imm); 97810037SARM gem5 Developers case 0x0b: 97910037SARM gem5 Developers return new LDRSHW64_PRE(machInst, rt, rnsp, imm); 98010037SARM gem5 Developers case 0x0c: 98110037SARM gem5 Developers return new STRHFP64_PRE(machInst, rt, rnsp, imm); 98210037SARM gem5 Developers case 0x0d: 98310037SARM gem5 Developers return new LDRHFP64_PRE(machInst, rt, rnsp, imm); 98410037SARM gem5 Developers case 0x10: 98510037SARM gem5 Developers return new STRW64_PRE(machInst, rt, rnsp, imm); 98610037SARM gem5 Developers case 0x11: 98710037SARM gem5 Developers return new LDRW64_PRE(machInst, rt, rnsp, imm); 98810037SARM gem5 Developers case 0x12: 98910037SARM gem5 Developers return new LDRSW64_PRE(machInst, rt, rnsp, imm); 99010037SARM gem5 Developers case 0x14: 99110037SARM gem5 Developers return new STRSFP64_PRE(machInst, rt, rnsp, imm); 99210037SARM gem5 Developers case 0x15: 99310037SARM gem5 Developers return new LDRSFP64_PRE(machInst, rt, rnsp, imm); 99410037SARM gem5 Developers case 0x18: 99510037SARM gem5 Developers return new STRX64_PRE(machInst, rt, rnsp, imm); 99610037SARM gem5 Developers case 0x19: 99710037SARM gem5 Developers return new LDRX64_PRE(machInst, rt, rnsp, imm); 99810037SARM gem5 Developers case 0x1c: 99910037SARM gem5 Developers return new STRDFP64_PRE(machInst, rt, rnsp, imm); 100010037SARM gem5 Developers case 0x1d: 100110037SARM gem5 Developers return new LDRDFP64_PRE(machInst, rt, rnsp, imm); 100210037SARM gem5 Developers default: 100310037SARM gem5 Developers return new Unknown64(machInst); 100410037SARM gem5 Developers } 100510037SARM gem5 Developers } 100610037SARM gem5 Developers } 100710037SARM gem5 Developers } 100810037SARM gem5 Developers } 100910037SARM gem5 Developers } 101010037SARM gem5 Developers return new FailUnimplemented("Unhandled Case1", machInst); 101110037SARM gem5 Developers } 101210037SARM gem5 Developers} 101310037SARM gem5 Developers}}; 101410037SARM gem5 Developers 101510037SARM gem5 Developersoutput decoder {{ 101610037SARM gem5 Developersnamespace Aarch64 101710037SARM gem5 Developers{ 101810037SARM gem5 Developers StaticInstPtr 101910037SARM gem5 Developers decodeDataProcReg(ExtMachInst machInst) 102010037SARM gem5 Developers { 102110037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 28) << 1) | 102210037SARM gem5 Developers (bits(machInst, 24) << 0); 102310037SARM gem5 Developers switch (switchVal) { 102410037SARM gem5 Developers case 0x0: 102510037SARM gem5 Developers { 102610037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 21) << 0) | 102710037SARM gem5 Developers (bits(machInst, 30, 29) << 1); 102810037SARM gem5 Developers ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 102910037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 103010037SARM gem5 Developers bool sf = bits(machInst, 31); 103110037SARM gem5 Developers if (!sf && (imm6 & 0x20)) 103210037SARM gem5 Developers return new Unknown64(machInst); 103310037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 103410337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 103510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 103610037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 103710037SARM gem5 Developers 103810037SARM gem5 Developers switch (switchVal) { 103910037SARM gem5 Developers case 0x0: 104010337SAndrew.Bardsley@arm.com return new AndXSReg(machInst, rdzr, rn, rm, imm6, type); 104110037SARM gem5 Developers case 0x1: 104210337SAndrew.Bardsley@arm.com return new BicXSReg(machInst, rdzr, rn, rm, imm6, type); 104310037SARM gem5 Developers case 0x2: 104410337SAndrew.Bardsley@arm.com return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type); 104510037SARM gem5 Developers case 0x3: 104610337SAndrew.Bardsley@arm.com return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type); 104710037SARM gem5 Developers case 0x4: 104810337SAndrew.Bardsley@arm.com return new EorXSReg(machInst, rdzr, rn, rm, imm6, type); 104910037SARM gem5 Developers case 0x5: 105010337SAndrew.Bardsley@arm.com return new EonXSReg(machInst, rdzr, rn, rm, imm6, type); 105110037SARM gem5 Developers case 0x6: 105210337SAndrew.Bardsley@arm.com return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type); 105310037SARM gem5 Developers case 0x7: 105410337SAndrew.Bardsley@arm.com return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type); 105510037SARM gem5 Developers } 105610037SARM gem5 Developers } 105710037SARM gem5 Developers case 0x1: 105810037SARM gem5 Developers { 105910037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 106010037SARM gem5 Developers if (bits(machInst, 21) == 0) { 106110037SARM gem5 Developers ArmShiftType type = 106210037SARM gem5 Developers (ArmShiftType)(uint8_t)bits(machInst, 23, 22); 106310037SARM gem5 Developers if (type == ROR) 106410037SARM gem5 Developers return new Unknown64(machInst); 106510037SARM gem5 Developers uint8_t imm6 = bits(machInst, 15, 10); 106610037SARM gem5 Developers if (!bits(machInst, 31) && bits(imm6, 5)) 106710037SARM gem5 Developers return new Unknown64(machInst); 106810037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 106910337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 107010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 107110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 107210037SARM gem5 Developers switch (switchVal) { 107310037SARM gem5 Developers case 0x0: 107410337SAndrew.Bardsley@arm.com return new AddXSReg(machInst, rdzr, rn, rm, imm6, type); 107510037SARM gem5 Developers case 0x1: 107610337SAndrew.Bardsley@arm.com return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type); 107710037SARM gem5 Developers case 0x2: 107810337SAndrew.Bardsley@arm.com return new SubXSReg(machInst, rdzr, rn, rm, imm6, type); 107910037SARM gem5 Developers case 0x3: 108010337SAndrew.Bardsley@arm.com return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type); 108110037SARM gem5 Developers } 108210037SARM gem5 Developers } else { 108310037SARM gem5 Developers if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) > 0x4) 108410037SARM gem5 Developers return new Unknown64(machInst); 108510037SARM gem5 Developers ArmExtendType type = 108610037SARM gem5 Developers (ArmExtendType)(uint8_t)bits(machInst, 15, 13); 108710037SARM gem5 Developers uint8_t imm3 = bits(machInst, 12, 10); 108810037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 108910037SARM gem5 Developers IntRegIndex rdsp = makeSP(rd); 109010337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 109110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 109210037SARM gem5 Developers IntRegIndex rnsp = makeSP(rn); 109310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 109410037SARM gem5 Developers 109510037SARM gem5 Developers switch (switchVal) { 109610037SARM gem5 Developers case 0x0: 109710037SARM gem5 Developers return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3); 109810037SARM gem5 Developers case 0x1: 109910337SAndrew.Bardsley@arm.com return new AddXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 110010037SARM gem5 Developers case 0x2: 110110037SARM gem5 Developers return new SubXEReg(machInst, rdsp, rnsp, rm, type, imm3); 110210037SARM gem5 Developers case 0x3: 110310337SAndrew.Bardsley@arm.com return new SubXERegCc(machInst, rdzr, rnsp, rm, type, imm3); 110410037SARM gem5 Developers } 110510037SARM gem5 Developers } 110610037SARM gem5 Developers } 110710037SARM gem5 Developers case 0x2: 110810037SARM gem5 Developers { 110910037SARM gem5 Developers if (bits(machInst, 21) == 1) 111010037SARM gem5 Developers return new Unknown64(machInst); 111110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 111210337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 111310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 111410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 111510037SARM gem5 Developers switch (bits(machInst, 23, 22)) { 111610037SARM gem5 Developers case 0x0: 111710037SARM gem5 Developers { 111810037SARM gem5 Developers if (bits(machInst, 15, 10)) 111910037SARM gem5 Developers return new Unknown64(machInst); 112010037SARM gem5 Developers uint8_t switchVal = bits(machInst, 30, 29); 112110037SARM gem5 Developers switch (switchVal) { 112210037SARM gem5 Developers case 0x0: 112310337SAndrew.Bardsley@arm.com return new AdcXSReg(machInst, rdzr, rn, rm, 0, LSL); 112410037SARM gem5 Developers case 0x1: 112510337SAndrew.Bardsley@arm.com return new AdcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 112610037SARM gem5 Developers case 0x2: 112710337SAndrew.Bardsley@arm.com return new SbcXSReg(machInst, rdzr, rn, rm, 0, LSL); 112810037SARM gem5 Developers case 0x3: 112910337SAndrew.Bardsley@arm.com return new SbcXSRegCc(machInst, rdzr, rn, rm, 0, LSL); 113010037SARM gem5 Developers } 113110037SARM gem5 Developers } 113210037SARM gem5 Developers case 0x1: 113310037SARM gem5 Developers { 113410037SARM gem5 Developers if ((bits(machInst, 4) == 1) || 113510037SARM gem5 Developers (bits(machInst, 10) == 1) || 113610037SARM gem5 Developers (bits(machInst, 29) == 0)) { 113710037SARM gem5 Developers return new Unknown64(machInst); 113810037SARM gem5 Developers } 113910037SARM gem5 Developers ConditionCode cond = 114010037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 114110037SARM gem5 Developers uint8_t flags = bits(machInst, 3, 0); 114210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 114310037SARM gem5 Developers if (bits(machInst, 11) == 0) { 114410037SARM gem5 Developers IntRegIndex rm = 114510037SARM gem5 Developers (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 114610037SARM gem5 Developers if (bits(machInst, 30) == 0) { 114710037SARM gem5 Developers return new CcmnReg64(machInst, rn, rm, cond, flags); 114810037SARM gem5 Developers } else { 114910037SARM gem5 Developers return new CcmpReg64(machInst, rn, rm, cond, flags); 115010037SARM gem5 Developers } 115110037SARM gem5 Developers } else { 115210037SARM gem5 Developers uint8_t imm5 = bits(machInst, 20, 16); 115310037SARM gem5 Developers if (bits(machInst, 30) == 0) { 115410037SARM gem5 Developers return new CcmnImm64(machInst, rn, imm5, cond, flags); 115510037SARM gem5 Developers } else { 115610037SARM gem5 Developers return new CcmpImm64(machInst, rn, imm5, cond, flags); 115710037SARM gem5 Developers } 115810037SARM gem5 Developers } 115910037SARM gem5 Developers } 116010037SARM gem5 Developers case 0x2: 116110037SARM gem5 Developers { 116210037SARM gem5 Developers if (bits(machInst, 29) == 1 || 116310037SARM gem5 Developers bits(machInst, 11) == 1) { 116410037SARM gem5 Developers return new Unknown64(machInst); 116510037SARM gem5 Developers } 116610037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 10) << 0) | 116710037SARM gem5 Developers (bits(machInst, 30) << 1); 116810037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 116910337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 117010037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 117110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 117210037SARM gem5 Developers ConditionCode cond = 117310037SARM gem5 Developers (ConditionCode)(uint8_t)bits(machInst, 15, 12); 117410037SARM gem5 Developers switch (switchVal) { 117510037SARM gem5 Developers case 0x0: 117610337SAndrew.Bardsley@arm.com return new Csel64(machInst, rdzr, rn, rm, cond); 117710037SARM gem5 Developers case 0x1: 117810337SAndrew.Bardsley@arm.com return new Csinc64(machInst, rdzr, rn, rm, cond); 117910037SARM gem5 Developers case 0x2: 118010337SAndrew.Bardsley@arm.com return new Csinv64(machInst, rdzr, rn, rm, cond); 118110037SARM gem5 Developers case 0x3: 118210337SAndrew.Bardsley@arm.com return new Csneg64(machInst, rdzr, rn, rm, cond); 118310037SARM gem5 Developers } 118410037SARM gem5 Developers } 118510037SARM gem5 Developers case 0x3: 118610037SARM gem5 Developers if (bits(machInst, 30) == 0) { 118710037SARM gem5 Developers if (bits(machInst, 29) != 0) 118810037SARM gem5 Developers return new Unknown64(machInst); 118910037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 119010037SARM gem5 Developers switch (switchVal) { 119110037SARM gem5 Developers case 0x2: 119210337SAndrew.Bardsley@arm.com return new Udiv64(machInst, rdzr, rn, rm); 119310037SARM gem5 Developers case 0x3: 119410337SAndrew.Bardsley@arm.com return new Sdiv64(machInst, rdzr, rn, rm); 119510037SARM gem5 Developers case 0x8: 119610337SAndrew.Bardsley@arm.com return new Lslv64(machInst, rdzr, rn, rm); 119710037SARM gem5 Developers case 0x9: 119810337SAndrew.Bardsley@arm.com return new Lsrv64(machInst, rdzr, rn, rm); 119910037SARM gem5 Developers case 0xa: 120010337SAndrew.Bardsley@arm.com return new Asrv64(machInst, rdzr, rn, rm); 120110037SARM gem5 Developers case 0xb: 120210337SAndrew.Bardsley@arm.com return new Rorv64(machInst, rdzr, rn, rm); 120310037SARM gem5 Developers default: 120410037SARM gem5 Developers return new Unknown64(machInst); 120510037SARM gem5 Developers } 120610037SARM gem5 Developers } else { 120710037SARM gem5 Developers if (bits(machInst, 20, 16) != 0 || 120810037SARM gem5 Developers bits(machInst, 29) != 0) { 120910037SARM gem5 Developers return new Unknown64(machInst); 121010037SARM gem5 Developers } 121110037SARM gem5 Developers uint8_t switchVal = bits(machInst, 15, 10); 121210037SARM gem5 Developers switch (switchVal) { 121310037SARM gem5 Developers case 0x0: 121410337SAndrew.Bardsley@arm.com return new Rbit64(machInst, rdzr, rn); 121510037SARM gem5 Developers case 0x1: 121610337SAndrew.Bardsley@arm.com return new Rev1664(machInst, rdzr, rn); 121710037SARM gem5 Developers case 0x2: 121810037SARM gem5 Developers if (bits(machInst, 31) == 0) 121910337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 122010037SARM gem5 Developers else 122110337SAndrew.Bardsley@arm.com return new Rev3264(machInst, rdzr, rn); 122210037SARM gem5 Developers case 0x3: 122310037SARM gem5 Developers if (bits(machInst, 31) != 1) 122410037SARM gem5 Developers return new Unknown64(machInst); 122510337SAndrew.Bardsley@arm.com return new Rev64(machInst, rdzr, rn); 122610037SARM gem5 Developers case 0x4: 122710337SAndrew.Bardsley@arm.com return new Clz64(machInst, rdzr, rn); 122810037SARM gem5 Developers case 0x5: 122910337SAndrew.Bardsley@arm.com return new Cls64(machInst, rdzr, rn); 123010037SARM gem5 Developers } 123110037SARM gem5 Developers } 123210037SARM gem5 Developers } 123310037SARM gem5 Developers } 123410037SARM gem5 Developers case 0x3: 123510037SARM gem5 Developers { 123610037SARM gem5 Developers if (bits(machInst, 30, 29) != 0x0 || 123710037SARM gem5 Developers (bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0)) 123810037SARM gem5 Developers return new Unknown64(machInst); 123910037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0); 124010337SAndrew.Bardsley@arm.com IntRegIndex rdzr = makeZero(rd); 124110037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5); 124210037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10); 124310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16); 124410037SARM gem5 Developers switch (bits(machInst, 23, 21)) { 124510037SARM gem5 Developers case 0x0: 124610037SARM gem5 Developers if (bits(machInst, 15) == 0) 124710337SAndrew.Bardsley@arm.com return new Madd64(machInst, rdzr, ra, rn, rm); 124810037SARM gem5 Developers else 124910337SAndrew.Bardsley@arm.com return new Msub64(machInst, rdzr, ra, rn, rm); 125010037SARM gem5 Developers case 0x1: 125110037SARM gem5 Developers if (bits(machInst, 15) == 0) 125210337SAndrew.Bardsley@arm.com return new Smaddl64(machInst, rdzr, ra, rn, rm); 125310037SARM gem5 Developers else 125410337SAndrew.Bardsley@arm.com return new Smsubl64(machInst, rdzr, ra, rn, rm); 125510037SARM gem5 Developers case 0x2: 125610037SARM gem5 Developers if (bits(machInst, 15) != 0) 125710037SARM gem5 Developers return new Unknown64(machInst); 125810337SAndrew.Bardsley@arm.com return new Smulh64(machInst, rdzr, rn, rm); 125910037SARM gem5 Developers case 0x5: 126010037SARM gem5 Developers if (bits(machInst, 15) == 0) 126110337SAndrew.Bardsley@arm.com return new Umaddl64(machInst, rdzr, ra, rn, rm); 126210037SARM gem5 Developers else 126310337SAndrew.Bardsley@arm.com return new Umsubl64(machInst, rdzr, ra, rn, rm); 126410037SARM gem5 Developers case 0x6: 126510037SARM gem5 Developers if (bits(machInst, 15) != 0) 126610037SARM gem5 Developers return new Unknown64(machInst); 126710337SAndrew.Bardsley@arm.com return new Umulh64(machInst, rdzr, rn, rm); 126810037SARM gem5 Developers default: 126910037SARM gem5 Developers return new Unknown64(machInst); 127010037SARM gem5 Developers } 127110037SARM gem5 Developers } 127210037SARM gem5 Developers } 127310037SARM gem5 Developers return new FailUnimplemented("Unhandled Case2", machInst); 127410037SARM gem5 Developers } 127510037SARM gem5 Developers} 127610037SARM gem5 Developers}}; 127710037SARM gem5 Developers 127810037SARM gem5 Developersoutput decoder {{ 127910037SARM gem5 Developersnamespace Aarch64 128010037SARM gem5 Developers{ 128110037SARM gem5 Developers StaticInstPtr 128210037SARM gem5 Developers decodeAdvSIMD(ExtMachInst machInst) 128310037SARM gem5 Developers { 128410037SARM gem5 Developers if (bits(machInst, 24) == 1) { 128510037SARM gem5 Developers if (bits(machInst, 10) == 0) { 128610037SARM gem5 Developers return decodeNeonIndexedElem(machInst); 128710037SARM gem5 Developers } else if (bits(machInst, 23) == 1) { 128810037SARM gem5 Developers return new Unknown64(machInst); 128910037SARM gem5 Developers } else { 129010037SARM gem5 Developers if (bits(machInst, 22, 19)) { 129110037SARM gem5 Developers return decodeNeonShiftByImm(machInst); 129210037SARM gem5 Developers } else { 129310037SARM gem5 Developers return decodeNeonModImm(machInst); 129410037SARM gem5 Developers } 129510037SARM gem5 Developers } 129610037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 129710037SARM gem5 Developers if (bits(machInst, 10) == 1) { 129810037SARM gem5 Developers return decodeNeon3Same(machInst); 129910037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 130010037SARM gem5 Developers return decodeNeon3Diff(machInst); 130110037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 130210037SARM gem5 Developers return decodeNeon2RegMisc(machInst); 130310037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 130410037SARM gem5 Developers return decodeNeonAcrossLanes(machInst); 130510037SARM gem5 Developers } else { 130610037SARM gem5 Developers return new Unknown64(machInst); 130710037SARM gem5 Developers } 130810037SARM gem5 Developers } else if (bits(machInst, 24) || 130910037SARM gem5 Developers bits(machInst, 21) || 131010037SARM gem5 Developers bits(machInst, 15)) { 131110037SARM gem5 Developers return new Unknown64(machInst); 131210037SARM gem5 Developers } else if (bits(machInst, 10) == 1) { 131310037SARM gem5 Developers if (bits(machInst, 23, 22)) 131410037SARM gem5 Developers return new Unknown64(machInst); 131510037SARM gem5 Developers return decodeNeonCopy(machInst); 131610037SARM gem5 Developers } else if (bits(machInst, 29) == 1) { 131710037SARM gem5 Developers return decodeNeonExt(machInst); 131810037SARM gem5 Developers } else if (bits(machInst, 11) == 1) { 131910037SARM gem5 Developers return decodeNeonZipUzpTrn(machInst); 132010037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0x0) { 132110037SARM gem5 Developers return decodeNeonTblTbx(machInst); 132210037SARM gem5 Developers } else { 132310037SARM gem5 Developers return new Unknown64(machInst); 132410037SARM gem5 Developers } 132510037SARM gem5 Developers return new FailUnimplemented("Unhandled Case3", machInst); 132610037SARM gem5 Developers } 132710037SARM gem5 Developers} 132810037SARM gem5 Developers}}; 132910037SARM gem5 Developers 133010037SARM gem5 Developers 133110037SARM gem5 Developersoutput decoder {{ 133210037SARM gem5 Developersnamespace Aarch64 133310037SARM gem5 Developers{ 133410037SARM gem5 Developers StaticInstPtr 133510037SARM gem5 Developers // bit 30=0, 28:25=1111 133610037SARM gem5 Developers decodeFp(ExtMachInst machInst) 133710037SARM gem5 Developers { 133810037SARM gem5 Developers if (bits(machInst, 24) == 1) { 133910037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 134010037SARM gem5 Developers return new Unknown64(machInst); 134110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 134210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 134310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 134410037SARM gem5 Developers IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10); 134510037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 23, 21) << 1) | 134610037SARM gem5 Developers (bits(machInst, 15) << 0); 134710037SARM gem5 Developers switch (switchVal) { 134810037SARM gem5 Developers case 0x0: // FMADD Sd = Sa + Sn*Sm 134910037SARM gem5 Developers return new FMAddS(machInst, rd, rn, rm, ra); 135010037SARM gem5 Developers case 0x1: // FMSUB Sd = Sa + (-Sn)*Sm 135110037SARM gem5 Developers return new FMSubS(machInst, rd, rn, rm, ra); 135210037SARM gem5 Developers case 0x2: // FNMADD Sd = (-Sa) + (-Sn)*Sm 135310037SARM gem5 Developers return new FNMAddS(machInst, rd, rn, rm, ra); 135410037SARM gem5 Developers case 0x3: // FNMSUB Sd = (-Sa) + Sn*Sm 135510037SARM gem5 Developers return new FNMSubS(machInst, rd, rn, rm, ra); 135610037SARM gem5 Developers case 0x4: // FMADD Dd = Da + Dn*Dm 135710037SARM gem5 Developers return new FMAddD(machInst, rd, rn, rm, ra); 135810037SARM gem5 Developers case 0x5: // FMSUB Dd = Da + (-Dn)*Dm 135910037SARM gem5 Developers return new FMSubD(machInst, rd, rn, rm, ra); 136010037SARM gem5 Developers case 0x6: // FNMADD Dd = (-Da) + (-Dn)*Dm 136110037SARM gem5 Developers return new FNMAddD(machInst, rd, rn, rm, ra); 136210037SARM gem5 Developers case 0x7: // FNMSUB Dd = (-Da) + Dn*Dm 136310037SARM gem5 Developers return new FNMSubD(machInst, rd, rn, rm, ra); 136410037SARM gem5 Developers default: 136510037SARM gem5 Developers return new Unknown64(machInst); 136610037SARM gem5 Developers } 136710037SARM gem5 Developers } else if (bits(machInst, 21) == 0) { 136810037SARM gem5 Developers bool s = bits(machInst, 29); 136910037SARM gem5 Developers if (s) 137010037SARM gem5 Developers return new Unknown64(machInst); 137110037SARM gem5 Developers uint8_t switchVal = bits(machInst, 20, 16); 137210037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 137310037SARM gem5 Developers uint8_t scale = bits(machInst, 15, 10); 137410037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 137510037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 137610037SARM gem5 Developers if (bits(machInst, 18, 17) == 3 && scale != 0) 137710037SARM gem5 Developers return new Unknown64(machInst); 137810037SARM gem5 Developers // 30:24=0011110, 21=0 137910037SARM gem5 Developers switch (switchVal) { 138010037SARM gem5 Developers case 0x00: 138110037SARM gem5 Developers return new FailUnimplemented("fcvtns", machInst); 138210037SARM gem5 Developers case 0x01: 138310037SARM gem5 Developers return new FailUnimplemented("fcvtnu", machInst); 138410037SARM gem5 Developers case 0x02: 138510037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 138610037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn/(2^fbits)) 138710037SARM gem5 Developers return new FcvtSFixedFpSW(machInst, rd, rn, scale); 138810037SARM gem5 Developers case 1: // SCVTF Dd = convertFromInt(Wn/(2^fbits)) 138910037SARM gem5 Developers return new FcvtSFixedFpDW(machInst, rd, rn, scale); 139010037SARM gem5 Developers case 4: // SCVTF Sd = convertFromInt(Xn/(2^fbits)) 139110037SARM gem5 Developers return new FcvtSFixedFpSX(machInst, rd, rn, scale); 139210037SARM gem5 Developers case 5: // SCVTF Dd = convertFromInt(Xn/(2^fbits)) 139310037SARM gem5 Developers return new FcvtSFixedFpDX(machInst, rd, rn, scale); 139410037SARM gem5 Developers default: 139510037SARM gem5 Developers return new Unknown64(machInst); 139610037SARM gem5 Developers } 139710037SARM gem5 Developers case 0x03: 139810037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 139910037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn/(2^fbits)) 140010037SARM gem5 Developers return new FcvtUFixedFpSW(machInst, rd, rn, scale); 140110037SARM gem5 Developers case 1: // UCVTF Dd = convertFromInt(Wn/(2^fbits)) 140210037SARM gem5 Developers return new FcvtUFixedFpDW(machInst, rd, rn, scale); 140310037SARM gem5 Developers case 4: // UCVTF Sd = convertFromInt(Xn/(2^fbits)) 140410037SARM gem5 Developers return new FcvtUFixedFpSX(machInst, rd, rn, scale); 140510037SARM gem5 Developers case 5: // UCVTF Dd = convertFromInt(Xn/(2^fbits)) 140610037SARM gem5 Developers return new FcvtUFixedFpDX(machInst, rd, rn, scale); 140710037SARM gem5 Developers default: 140810037SARM gem5 Developers return new Unknown64(machInst); 140910037SARM gem5 Developers } 141010037SARM gem5 Developers case 0x04: 141110037SARM gem5 Developers return new FailUnimplemented("fcvtas", machInst); 141210037SARM gem5 Developers case 0x05: 141310037SARM gem5 Developers return new FailUnimplemented("fcvtau", machInst); 141410037SARM gem5 Developers case 0x08: 141510037SARM gem5 Developers return new FailUnimplemented("fcvtps", machInst); 141610037SARM gem5 Developers case 0x09: 141710037SARM gem5 Developers return new FailUnimplemented("fcvtpu", machInst); 141810037SARM gem5 Developers case 0x0e: 141910037SARM gem5 Developers return new FailUnimplemented("fmov elem. to 64", machInst); 142010037SARM gem5 Developers case 0x0f: 142110037SARM gem5 Developers return new FailUnimplemented("fmov 64 bit", machInst); 142210037SARM gem5 Developers case 0x10: 142310037SARM gem5 Developers return new FailUnimplemented("fcvtms", machInst); 142410037SARM gem5 Developers case 0x11: 142510037SARM gem5 Developers return new FailUnimplemented("fcvtmu", machInst); 142610037SARM gem5 Developers case 0x18: 142710037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 142810037SARM gem5 Developers case 0: // FCVTZS Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 142910037SARM gem5 Developers return new FcvtFpSFixedSW(machInst, rd, rn, scale); 143010037SARM gem5 Developers case 1: // FCVTZS Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 143110037SARM gem5 Developers return new FcvtFpSFixedDW(machInst, rd, rn, scale); 143210037SARM gem5 Developers case 4: // FCVTZS Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 143310037SARM gem5 Developers return new FcvtFpSFixedSX(machInst, rd, rn, scale); 143410037SARM gem5 Developers case 5: // FCVTZS Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 143510037SARM gem5 Developers return new FcvtFpSFixedDX(machInst, rd, rn, scale); 143610037SARM gem5 Developers default: 143710037SARM gem5 Developers return new Unknown64(machInst); 143810037SARM gem5 Developers } 143910037SARM gem5 Developers case 0x19: 144010037SARM gem5 Developers switch ( (bits(machInst, 31) << 2) | type ) { 144110037SARM gem5 Developers case 0: // FCVTZU Wd = convertToIntExactTowardZero(Sn*(2^fbits)) 144210037SARM gem5 Developers return new FcvtFpUFixedSW(machInst, rd, rn, scale); 144310037SARM gem5 Developers case 1: // FCVTZU Wd = convertToIntExactTowardZero(Dn*(2^fbits)) 144410037SARM gem5 Developers return new FcvtFpUFixedDW(machInst, rd, rn, scale); 144510037SARM gem5 Developers case 4: // FCVTZU Xd = convertToIntExactTowardZero(Sn*(2^fbits)) 144610037SARM gem5 Developers return new FcvtFpUFixedSX(machInst, rd, rn, scale); 144710037SARM gem5 Developers case 5: // FCVTZU Xd = convertToIntExactTowardZero(Dn*(2^fbits)) 144810037SARM gem5 Developers return new FcvtFpUFixedDX(machInst, rd, rn, scale); 144910037SARM gem5 Developers default: 145010037SARM gem5 Developers return new Unknown64(machInst); 145110037SARM gem5 Developers } 145210037SARM gem5 Developers } 145310037SARM gem5 Developers } else { 145410037SARM gem5 Developers // 30=0, 28:24=11110, 21=1 145510037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 145610037SARM gem5 Developers uint8_t imm8 = bits(machInst, 20, 13); 145710037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 145810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 145910037SARM gem5 Developers switch (bits(machInst, 11, 10)) { 146010037SARM gem5 Developers case 0x0: 146110037SARM gem5 Developers if (bits(machInst, 12) == 1) { 146210037SARM gem5 Developers if (bits(machInst, 31) || 146310037SARM gem5 Developers bits(machInst, 29) || 146410037SARM gem5 Developers bits(machInst, 9, 5)) { 146510037SARM gem5 Developers return new Unknown64(machInst); 146610037SARM gem5 Developers } 146710037SARM gem5 Developers // 31:29=000, 28:24=11110, 21=1, 12:10=100 146810037SARM gem5 Developers if (type == 0) { 146910037SARM gem5 Developers // FMOV S[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5) 147010037SARM gem5 Developers // :imm8<5:0>:Zeros(19) 147110037SARM gem5 Developers uint32_t imm = vfp_modified_imm(imm8, false); 147210037SARM gem5 Developers return new FmovImmS(machInst, rd, imm); 147310037SARM gem5 Developers } else if (type == 1) { 147410037SARM gem5 Developers // FMOV D[d] = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,8) 147510037SARM gem5 Developers // :imm8<5:0>:Zeros(48) 147610037SARM gem5 Developers uint64_t imm = vfp_modified_imm(imm8, true); 147710037SARM gem5 Developers return new FmovImmD(machInst, rd, imm); 147810037SARM gem5 Developers } else { 147910037SARM gem5 Developers return new Unknown64(machInst); 148010037SARM gem5 Developers } 148110037SARM gem5 Developers } else if (bits(machInst, 13) == 1) { 148210037SARM gem5 Developers if (bits(machInst, 31) || 148310037SARM gem5 Developers bits(machInst, 29) || 148410037SARM gem5 Developers bits(machInst, 15, 14) || 148510037SARM gem5 Developers bits(machInst, 23) || 148610037SARM gem5 Developers bits(machInst, 2, 0)) { 148710037SARM gem5 Developers return new Unknown64(machInst); 148810037SARM gem5 Developers } 148910037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4, 3) << 0) | 149010037SARM gem5 Developers (bits(machInst, 22) << 2); 149110037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) 149210037SARM gem5 Developers bits(machInst, 20, 16); 149310037SARM gem5 Developers // 28:23=000111100, 21=1, 15:10=001000, 2:0=000 149410037SARM gem5 Developers switch (switchVal) { 149510037SARM gem5 Developers case 0x0: 149610037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,Sm) 149710037SARM gem5 Developers return new FCmpRegS(machInst, rn, rm); 149810037SARM gem5 Developers case 0x1: 149910037SARM gem5 Developers // FCMP flags = compareQuiet(Sn,0.0) 150010037SARM gem5 Developers return new FCmpImmS(machInst, rn, 0); 150110037SARM gem5 Developers case 0x2: 150210037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,Sm) 150310037SARM gem5 Developers return new FCmpERegS(machInst, rn, rm); 150410037SARM gem5 Developers case 0x3: 150510037SARM gem5 Developers // FCMPE flags = compareSignaling(Sn,0.0) 150610037SARM gem5 Developers return new FCmpEImmS(machInst, rn, 0); 150710037SARM gem5 Developers case 0x4: 150810037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,Dm) 150910037SARM gem5 Developers return new FCmpRegD(machInst, rn, rm); 151010037SARM gem5 Developers case 0x5: 151110037SARM gem5 Developers // FCMP flags = compareQuiet(Dn,0.0) 151210037SARM gem5 Developers return new FCmpImmD(machInst, rn, 0); 151310037SARM gem5 Developers case 0x6: 151410037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,Dm) 151510037SARM gem5 Developers return new FCmpERegD(machInst, rn, rm); 151610037SARM gem5 Developers case 0x7: 151710037SARM gem5 Developers // FCMPE flags = compareSignaling(Dn,0.0) 151810037SARM gem5 Developers return new FCmpEImmD(machInst, rn, 0); 151910037SARM gem5 Developers default: 152010037SARM gem5 Developers return new Unknown64(machInst); 152110037SARM gem5 Developers } 152210037SARM gem5 Developers } else if (bits(machInst, 14) == 1) { 152310037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 152410037SARM gem5 Developers return new Unknown64(machInst); 152510037SARM gem5 Developers uint8_t opcode = bits(machInst, 20, 15); 152610037SARM gem5 Developers // Bits 31:24=00011110, 21=1, 14:10=10000 152710037SARM gem5 Developers switch (opcode) { 152810037SARM gem5 Developers case 0x0: 152910037SARM gem5 Developers if (type == 0) 153010037SARM gem5 Developers // FMOV Sd = Sn 153110037SARM gem5 Developers return new FmovRegS(machInst, rd, rn); 153210037SARM gem5 Developers else if (type == 1) 153310037SARM gem5 Developers // FMOV Dd = Dn 153410037SARM gem5 Developers return new FmovRegD(machInst, rd, rn); 153510037SARM gem5 Developers break; 153610037SARM gem5 Developers case 0x1: 153710037SARM gem5 Developers if (type == 0) 153810037SARM gem5 Developers // FABS Sd = abs(Sn) 153910037SARM gem5 Developers return new FAbsS(machInst, rd, rn); 154010037SARM gem5 Developers else if (type == 1) 154110037SARM gem5 Developers // FABS Dd = abs(Dn) 154210037SARM gem5 Developers return new FAbsD(machInst, rd, rn); 154310037SARM gem5 Developers break; 154410037SARM gem5 Developers case 0x2: 154510037SARM gem5 Developers if (type == 0) 154610037SARM gem5 Developers // FNEG Sd = -Sn 154710037SARM gem5 Developers return new FNegS(machInst, rd, rn); 154810037SARM gem5 Developers else if (type == 1) 154910037SARM gem5 Developers // FNEG Dd = -Dn 155010037SARM gem5 Developers return new FNegD(machInst, rd, rn); 155110037SARM gem5 Developers break; 155210037SARM gem5 Developers case 0x3: 155310037SARM gem5 Developers if (type == 0) 155410037SARM gem5 Developers // FSQRT Sd = sqrt(Sn) 155510037SARM gem5 Developers return new FSqrtS(machInst, rd, rn); 155610037SARM gem5 Developers else if (type == 1) 155710037SARM gem5 Developers // FSQRT Dd = sqrt(Dn) 155810037SARM gem5 Developers return new FSqrtD(machInst, rd, rn); 155910037SARM gem5 Developers break; 156010037SARM gem5 Developers case 0x4: 156110037SARM gem5 Developers if (type == 1) 156210037SARM gem5 Developers // FCVT Sd = convertFormat(Dn) 156310037SARM gem5 Developers return new FcvtFpDFpS(machInst, rd, rn); 156410037SARM gem5 Developers else if (type == 3) 156510037SARM gem5 Developers // FCVT Sd = convertFormat(Hn) 156610037SARM gem5 Developers return new FcvtFpHFpS(machInst, rd, rn); 156710037SARM gem5 Developers break; 156810037SARM gem5 Developers case 0x5: 156910037SARM gem5 Developers if (type == 0) 157010037SARM gem5 Developers // FCVT Dd = convertFormat(Sn) 157110037SARM gem5 Developers return new FCvtFpSFpD(machInst, rd, rn); 157210037SARM gem5 Developers else if (type == 3) 157310037SARM gem5 Developers // FCVT Dd = convertFormat(Hn) 157410037SARM gem5 Developers return new FcvtFpHFpD(machInst, rd, rn); 157510037SARM gem5 Developers break; 157610037SARM gem5 Developers case 0x7: 157710037SARM gem5 Developers if (type == 0) 157810037SARM gem5 Developers // FCVT Hd = convertFormat(Sn) 157910037SARM gem5 Developers return new FcvtFpSFpH(machInst, rd, rn); 158010037SARM gem5 Developers else if (type == 1) 158110037SARM gem5 Developers // FCVT Hd = convertFormat(Dn) 158210037SARM gem5 Developers return new FcvtFpDFpH(machInst, rd, rn); 158310037SARM gem5 Developers break; 158410037SARM gem5 Developers case 0x8: 158510037SARM gem5 Developers if (type == 0) // FRINTN Sd = roundToIntegralTiesToEven(Sn) 158610037SARM gem5 Developers return new FRIntNS(machInst, rd, rn); 158710037SARM gem5 Developers else if (type == 1) // FRINTN Dd = roundToIntegralTiesToEven(Dn) 158810037SARM gem5 Developers return new FRIntND(machInst, rd, rn); 158910037SARM gem5 Developers break; 159010037SARM gem5 Developers case 0x9: 159110037SARM gem5 Developers if (type == 0) // FRINTP Sd = roundToIntegralTowardPlusInf(Sn) 159210037SARM gem5 Developers return new FRIntPS(machInst, rd, rn); 159310037SARM gem5 Developers else if (type == 1) // FRINTP Dd = roundToIntegralTowardPlusInf(Dn) 159410037SARM gem5 Developers return new FRIntPD(machInst, rd, rn); 159510037SARM gem5 Developers break; 159610037SARM gem5 Developers case 0xa: 159710037SARM gem5 Developers if (type == 0) // FRINTM Sd = roundToIntegralTowardMinusInf(Sn) 159810037SARM gem5 Developers return new FRIntMS(machInst, rd, rn); 159910037SARM gem5 Developers else if (type == 1) // FRINTM Dd = roundToIntegralTowardMinusInf(Dn) 160010037SARM gem5 Developers return new FRIntMD(machInst, rd, rn); 160110037SARM gem5 Developers break; 160210037SARM gem5 Developers case 0xb: 160310037SARM gem5 Developers if (type == 0) // FRINTZ Sd = roundToIntegralTowardZero(Sn) 160410037SARM gem5 Developers return new FRIntZS(machInst, rd, rn); 160510037SARM gem5 Developers else if (type == 1) // FRINTZ Dd = roundToIntegralTowardZero(Dn) 160610037SARM gem5 Developers return new FRIntZD(machInst, rd, rn); 160710037SARM gem5 Developers break; 160810037SARM gem5 Developers case 0xc: 160910037SARM gem5 Developers if (type == 0) // FRINTA Sd = roundToIntegralTiesToAway(Sn) 161010037SARM gem5 Developers return new FRIntAS(machInst, rd, rn); 161110037SARM gem5 Developers else if (type == 1) // FRINTA Dd = roundToIntegralTiesToAway(Dn) 161210037SARM gem5 Developers return new FRIntAD(machInst, rd, rn); 161310037SARM gem5 Developers break; 161410037SARM gem5 Developers case 0xe: 161510037SARM gem5 Developers if (type == 0) // FRINTX Sd = roundToIntegralExact(Sn) 161610037SARM gem5 Developers return new FRIntXS(machInst, rd, rn); 161710037SARM gem5 Developers else if (type == 1) // FRINTX Dd = roundToIntegralExact(Dn) 161810037SARM gem5 Developers return new FRIntXD(machInst, rd, rn); 161910037SARM gem5 Developers break; 162010037SARM gem5 Developers case 0xf: 162110037SARM gem5 Developers if (type == 0) // FRINTI Sd = roundToIntegral(Sn) 162210037SARM gem5 Developers return new FRIntIS(machInst, rd, rn); 162310037SARM gem5 Developers else if (type == 1) // FRINTI Dd = roundToIntegral(Dn) 162410037SARM gem5 Developers return new FRIntID(machInst, rd, rn); 162510037SARM gem5 Developers break; 162610037SARM gem5 Developers default: 162710037SARM gem5 Developers return new Unknown64(machInst); 162810037SARM gem5 Developers } 162910037SARM gem5 Developers return new Unknown64(machInst); 163010037SARM gem5 Developers } else if (bits(machInst, 15) == 1) { 163110037SARM gem5 Developers return new Unknown64(machInst); 163210037SARM gem5 Developers } else { 163310037SARM gem5 Developers if (bits(machInst, 29)) 163410037SARM gem5 Developers return new Unknown64(machInst); 163510037SARM gem5 Developers uint8_t rmode = bits(machInst, 20, 19); 163610037SARM gem5 Developers uint8_t switchVal1 = bits(machInst, 18, 16); 163710037SARM gem5 Developers uint8_t switchVal2 = (type << 1) | bits(machInst, 31); 163810037SARM gem5 Developers // 30:24=0011110, 21=1, 15:10=000000 163910037SARM gem5 Developers switch (switchVal1) { 164010037SARM gem5 Developers case 0x0: 164110037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 164210037SARM gem5 Developers case 0x0: //FCVTNS Wd = convertToIntExactTiesToEven(Sn) 164310037SARM gem5 Developers return new FcvtFpSIntWSN(machInst, rd, rn); 164410037SARM gem5 Developers case 0x1: //FCVTPS Wd = convertToIntExactTowardPlusInf(Sn) 164510037SARM gem5 Developers return new FcvtFpSIntWSP(machInst, rd, rn); 164610037SARM gem5 Developers case 0x2: //FCVTMS Wd = convertToIntExactTowardMinusInf(Sn) 164710037SARM gem5 Developers return new FcvtFpSIntWSM(machInst, rd, rn); 164810037SARM gem5 Developers case 0x3: //FCVTZS Wd = convertToIntExactTowardZero(Sn) 164910037SARM gem5 Developers return new FcvtFpSIntWSZ(machInst, rd, rn); 165010037SARM gem5 Developers case 0x4: //FCVTNS Xd = convertToIntExactTiesToEven(Sn) 165110037SARM gem5 Developers return new FcvtFpSIntXSN(machInst, rd, rn); 165210037SARM gem5 Developers case 0x5: //FCVTPS Xd = convertToIntExactTowardPlusInf(Sn) 165310037SARM gem5 Developers return new FcvtFpSIntXSP(machInst, rd, rn); 165410037SARM gem5 Developers case 0x6: //FCVTMS Xd = convertToIntExactTowardMinusInf(Sn) 165510037SARM gem5 Developers return new FcvtFpSIntXSM(machInst, rd, rn); 165610037SARM gem5 Developers case 0x7: //FCVTZS Xd = convertToIntExactTowardZero(Sn) 165710037SARM gem5 Developers return new FcvtFpSIntXSZ(machInst, rd, rn); 165810037SARM gem5 Developers case 0x8: //FCVTNS Wd = convertToIntExactTiesToEven(Dn) 165910037SARM gem5 Developers return new FcvtFpSIntWDN(machInst, rd, rn); 166010037SARM gem5 Developers case 0x9: //FCVTPS Wd = convertToIntExactTowardPlusInf(Dn) 166110037SARM gem5 Developers return new FcvtFpSIntWDP(machInst, rd, rn); 166210037SARM gem5 Developers case 0xA: //FCVTMS Wd = convertToIntExactTowardMinusInf(Dn) 166310037SARM gem5 Developers return new FcvtFpSIntWDM(machInst, rd, rn); 166410037SARM gem5 Developers case 0xB: //FCVTZS Wd = convertToIntExactTowardZero(Dn) 166510037SARM gem5 Developers return new FcvtFpSIntWDZ(machInst, rd, rn); 166610037SARM gem5 Developers case 0xC: //FCVTNS Xd = convertToIntExactTiesToEven(Dn) 166710037SARM gem5 Developers return new FcvtFpSIntXDN(machInst, rd, rn); 166810037SARM gem5 Developers case 0xD: //FCVTPS Xd = convertToIntExactTowardPlusInf(Dn) 166910037SARM gem5 Developers return new FcvtFpSIntXDP(machInst, rd, rn); 167010037SARM gem5 Developers case 0xE: //FCVTMS Xd = convertToIntExactTowardMinusInf(Dn) 167110037SARM gem5 Developers return new FcvtFpSIntXDM(machInst, rd, rn); 167210037SARM gem5 Developers case 0xF: //FCVTZS Xd = convertToIntExactTowardZero(Dn) 167310037SARM gem5 Developers return new FcvtFpSIntXDZ(machInst, rd, rn); 167410037SARM gem5 Developers default: 167510037SARM gem5 Developers return new Unknown64(machInst); 167610037SARM gem5 Developers } 167710037SARM gem5 Developers case 0x1: 167810037SARM gem5 Developers switch ((switchVal2 << 2) | rmode) { 167910037SARM gem5 Developers case 0x0: //FCVTNU Wd = convertToIntExactTiesToEven(Sn) 168010037SARM gem5 Developers return new FcvtFpUIntWSN(machInst, rd, rn); 168110037SARM gem5 Developers case 0x1: //FCVTPU Wd = convertToIntExactTowardPlusInf(Sn) 168210037SARM gem5 Developers return new FcvtFpUIntWSP(machInst, rd, rn); 168310037SARM gem5 Developers case 0x2: //FCVTMU Wd = convertToIntExactTowardMinusInf(Sn) 168410037SARM gem5 Developers return new FcvtFpUIntWSM(machInst, rd, rn); 168510037SARM gem5 Developers case 0x3: //FCVTZU Wd = convertToIntExactTowardZero(Sn) 168610037SARM gem5 Developers return new FcvtFpUIntWSZ(machInst, rd, rn); 168710037SARM gem5 Developers case 0x4: //FCVTNU Xd = convertToIntExactTiesToEven(Sn) 168810037SARM gem5 Developers return new FcvtFpUIntXSN(machInst, rd, rn); 168910037SARM gem5 Developers case 0x5: //FCVTPU Xd = convertToIntExactTowardPlusInf(Sn) 169010037SARM gem5 Developers return new FcvtFpUIntXSP(machInst, rd, rn); 169110037SARM gem5 Developers case 0x6: //FCVTMU Xd = convertToIntExactTowardMinusInf(Sn) 169210037SARM gem5 Developers return new FcvtFpUIntXSM(machInst, rd, rn); 169310037SARM gem5 Developers case 0x7: //FCVTZU Xd = convertToIntExactTowardZero(Sn) 169410037SARM gem5 Developers return new FcvtFpUIntXSZ(machInst, rd, rn); 169510037SARM gem5 Developers case 0x8: //FCVTNU Wd = convertToIntExactTiesToEven(Dn) 169610037SARM gem5 Developers return new FcvtFpUIntWDN(machInst, rd, rn); 169710037SARM gem5 Developers case 0x9: //FCVTPU Wd = convertToIntExactTowardPlusInf(Dn) 169810037SARM gem5 Developers return new FcvtFpUIntWDP(machInst, rd, rn); 169910037SARM gem5 Developers case 0xA: //FCVTMU Wd = convertToIntExactTowardMinusInf(Dn) 170010037SARM gem5 Developers return new FcvtFpUIntWDM(machInst, rd, rn); 170110037SARM gem5 Developers case 0xB: //FCVTZU Wd = convertToIntExactTowardZero(Dn) 170210037SARM gem5 Developers return new FcvtFpUIntWDZ(machInst, rd, rn); 170310037SARM gem5 Developers case 0xC: //FCVTNU Xd = convertToIntExactTiesToEven(Dn) 170410037SARM gem5 Developers return new FcvtFpUIntXDN(machInst, rd, rn); 170510037SARM gem5 Developers case 0xD: //FCVTPU Xd = convertToIntExactTowardPlusInf(Dn) 170610037SARM gem5 Developers return new FcvtFpUIntXDP(machInst, rd, rn); 170710037SARM gem5 Developers case 0xE: //FCVTMU Xd = convertToIntExactTowardMinusInf(Dn) 170810037SARM gem5 Developers return new FcvtFpUIntXDM(machInst, rd, rn); 170910037SARM gem5 Developers case 0xF: //FCVTZU Xd = convertToIntExactTowardZero(Dn) 171010037SARM gem5 Developers return new FcvtFpUIntXDZ(machInst, rd, rn); 171110037SARM gem5 Developers default: 171210037SARM gem5 Developers return new Unknown64(machInst); 171310037SARM gem5 Developers } 171410037SARM gem5 Developers case 0x2: 171510037SARM gem5 Developers if (rmode != 0) 171610037SARM gem5 Developers return new Unknown64(machInst); 171710037SARM gem5 Developers switch (switchVal2) { 171810037SARM gem5 Developers case 0: // SCVTF Sd = convertFromInt(Wn) 171910037SARM gem5 Developers return new FcvtWSIntFpS(machInst, rd, rn); 172010037SARM gem5 Developers case 1: // SCVTF Sd = convertFromInt(Xn) 172110037SARM gem5 Developers return new FcvtXSIntFpS(machInst, rd, rn); 172210037SARM gem5 Developers case 2: // SCVTF Dd = convertFromInt(Wn) 172310037SARM gem5 Developers return new FcvtWSIntFpD(machInst, rd, rn); 172410037SARM gem5 Developers case 3: // SCVTF Dd = convertFromInt(Xn) 172510037SARM gem5 Developers return new FcvtXSIntFpD(machInst, rd, rn); 172610037SARM gem5 Developers default: 172710037SARM gem5 Developers return new Unknown64(machInst); 172810037SARM gem5 Developers } 172910037SARM gem5 Developers case 0x3: 173010037SARM gem5 Developers switch (switchVal2) { 173110037SARM gem5 Developers case 0: // UCVTF Sd = convertFromInt(Wn) 173210037SARM gem5 Developers return new FcvtWUIntFpS(machInst, rd, rn); 173310037SARM gem5 Developers case 1: // UCVTF Sd = convertFromInt(Xn) 173410037SARM gem5 Developers return new FcvtXUIntFpS(machInst, rd, rn); 173510037SARM gem5 Developers case 2: // UCVTF Dd = convertFromInt(Wn) 173610037SARM gem5 Developers return new FcvtWUIntFpD(machInst, rd, rn); 173710037SARM gem5 Developers case 3: // UCVTF Dd = convertFromInt(Xn) 173810037SARM gem5 Developers return new FcvtXUIntFpD(machInst, rd, rn); 173910037SARM gem5 Developers default: 174010037SARM gem5 Developers return new Unknown64(machInst); 174110037SARM gem5 Developers } 174210037SARM gem5 Developers case 0x4: 174310037SARM gem5 Developers if (rmode != 0) 174410037SARM gem5 Developers return new Unknown64(machInst); 174510037SARM gem5 Developers switch (switchVal2) { 174610037SARM gem5 Developers case 0: // FCVTAS Wd = convertToIntExactTiesToAway(Sn) 174710037SARM gem5 Developers return new FcvtFpSIntWSA(machInst, rd, rn); 174810037SARM gem5 Developers case 1: // FCVTAS Xd = convertToIntExactTiesToAway(Sn) 174910037SARM gem5 Developers return new FcvtFpSIntXSA(machInst, rd, rn); 175010037SARM gem5 Developers case 2: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 175110037SARM gem5 Developers return new FcvtFpSIntWDA(machInst, rd, rn); 175210037SARM gem5 Developers case 3: // FCVTAS Wd = convertToIntExactTiesToAway(Dn) 175310037SARM gem5 Developers return new FcvtFpSIntXDA(machInst, rd, rn); 175410037SARM gem5 Developers default: 175510037SARM gem5 Developers return new Unknown64(machInst); 175610037SARM gem5 Developers } 175710037SARM gem5 Developers case 0x5: 175810037SARM gem5 Developers switch (switchVal2) { 175910037SARM gem5 Developers case 0: // FCVTAU Wd = convertToIntExactTiesToAway(Sn) 176010037SARM gem5 Developers return new FcvtFpUIntWSA(machInst, rd, rn); 176110037SARM gem5 Developers case 1: // FCVTAU Xd = convertToIntExactTiesToAway(Sn) 176210037SARM gem5 Developers return new FcvtFpUIntXSA(machInst, rd, rn); 176310037SARM gem5 Developers case 2: // FCVTAU Wd = convertToIntExactTiesToAway(Dn) 176410037SARM gem5 Developers return new FcvtFpUIntWDA(machInst, rd, rn); 176510037SARM gem5 Developers case 3: // FCVTAU Xd = convertToIntExactTiesToAway(Dn) 176610037SARM gem5 Developers return new FcvtFpUIntXDA(machInst, rd, rn); 176710037SARM gem5 Developers default: 176810037SARM gem5 Developers return new Unknown64(machInst); 176910037SARM gem5 Developers } 177010037SARM gem5 Developers case 0x06: 177110037SARM gem5 Developers switch (switchVal2) { 177210037SARM gem5 Developers case 0: // FMOV Wd = Sn 177310037SARM gem5 Developers if (rmode != 0) 177410037SARM gem5 Developers return new Unknown64(machInst); 177510037SARM gem5 Developers return new FmovRegCoreW(machInst, rd, rn); 177610037SARM gem5 Developers case 3: // FMOV Xd = Dn 177710037SARM gem5 Developers if (rmode != 0) 177810037SARM gem5 Developers return new Unknown64(machInst); 177910037SARM gem5 Developers return new FmovRegCoreX(machInst, rd, rn); 178010037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 178110037SARM gem5 Developers if (rmode != 1) 178210037SARM gem5 Developers return new Unknown64(machInst); 178310037SARM gem5 Developers return new FmovURegCoreX(machInst, rd, rn); 178410037SARM gem5 Developers default: 178510037SARM gem5 Developers return new Unknown64(machInst); 178610037SARM gem5 Developers } 178710037SARM gem5 Developers break; 178810037SARM gem5 Developers case 0x07: 178910037SARM gem5 Developers switch (switchVal2) { 179010037SARM gem5 Developers case 0: // FMOV Sd = Wn 179110037SARM gem5 Developers if (rmode != 0) 179210037SARM gem5 Developers return new Unknown64(machInst); 179310037SARM gem5 Developers return new FmovCoreRegW(machInst, rd, rn); 179410037SARM gem5 Developers case 3: // FMOV Xd = Dn 179510037SARM gem5 Developers if (rmode != 0) 179610037SARM gem5 Developers return new Unknown64(machInst); 179710037SARM gem5 Developers return new FmovCoreRegX(machInst, rd, rn); 179810037SARM gem5 Developers case 5: // FMOV Xd = Vn<127:64> 179910037SARM gem5 Developers if (rmode != 1) 180010037SARM gem5 Developers return new Unknown64(machInst); 180110037SARM gem5 Developers return new FmovUCoreRegX(machInst, rd, rn); 180210037SARM gem5 Developers default: 180310037SARM gem5 Developers return new Unknown64(machInst); 180410037SARM gem5 Developers } 180510037SARM gem5 Developers break; 180610037SARM gem5 Developers default: // Warning! missing cases in switch statement above, that still need to be added 180710037SARM gem5 Developers return new Unknown64(machInst); 180810037SARM gem5 Developers } 180910037SARM gem5 Developers } 181010037SARM gem5 Developers case 0x1: 181110037SARM gem5 Developers { 181210037SARM gem5 Developers if (bits(machInst, 31) || 181310037SARM gem5 Developers bits(machInst, 29) || 181410037SARM gem5 Developers bits(machInst, 23)) { 181510037SARM gem5 Developers return new Unknown64(machInst); 181610037SARM gem5 Developers } 181710037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16); 181810037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5); 181910037SARM gem5 Developers uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0); 182010037SARM gem5 Developers ConditionCode cond = 182110037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 182210037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 4) << 0) | 182310037SARM gem5 Developers (bits(machInst, 22) << 1); 182410037SARM gem5 Developers // 31:23=000111100, 21=1, 11:10=01 182510037SARM gem5 Developers switch (switchVal) { 182610037SARM gem5 Developers case 0x0: 182710037SARM gem5 Developers // FCCMP flags = if cond the compareQuiet(Sn,Sm) else #nzcv 182810037SARM gem5 Developers return new FCCmpRegS(machInst, rn, rm, cond, imm); 182910037SARM gem5 Developers case 0x1: 183010037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Sn,Sm) 183110037SARM gem5 Developers // else #nzcv 183210037SARM gem5 Developers return new FCCmpERegS(machInst, rn, rm, cond, imm); 183310037SARM gem5 Developers case 0x2: 183410037SARM gem5 Developers // FCCMP flags = if cond then compareQuiet(Dn,Dm) else #nzcv 183510037SARM gem5 Developers return new FCCmpRegD(machInst, rn, rm, cond, imm); 183610037SARM gem5 Developers case 0x3: 183710037SARM gem5 Developers // FCCMP flags = if cond then compareSignaling(Dn,Dm) 183810037SARM gem5 Developers // else #nzcv 183910037SARM gem5 Developers return new FCCmpERegD(machInst, rn, rm, cond, imm); 184010037SARM gem5 Developers default: 184110037SARM gem5 Developers return new Unknown64(machInst); 184210037SARM gem5 Developers } 184310037SARM gem5 Developers } 184410037SARM gem5 Developers case 0x2: 184510037SARM gem5 Developers { 184610037SARM gem5 Developers if (bits(machInst, 31) || 184710037SARM gem5 Developers bits(machInst, 29) || 184810037SARM gem5 Developers bits(machInst, 23)) { 184910037SARM gem5 Developers return new Unknown64(machInst); 185010037SARM gem5 Developers } 185110037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 185210037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 185310037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 185410037SARM gem5 Developers uint8_t switchVal = (bits(machInst, 15, 12) << 0) | 185510037SARM gem5 Developers (bits(machInst, 22) << 4); 185610037SARM gem5 Developers switch (switchVal) { 185710037SARM gem5 Developers case 0x00: // FMUL Sd = Sn * Sm 185810037SARM gem5 Developers return new FMulS(machInst, rd, rn, rm); 185910037SARM gem5 Developers case 0x10: // FMUL Dd = Dn * Dm 186010037SARM gem5 Developers return new FMulD(machInst, rd, rn, rm); 186110037SARM gem5 Developers case 0x01: // FDIV Sd = Sn / Sm 186210037SARM gem5 Developers return new FDivS(machInst, rd, rn, rm); 186310037SARM gem5 Developers case 0x11: // FDIV Dd = Dn / Dm 186410037SARM gem5 Developers return new FDivD(machInst, rd, rn, rm); 186510037SARM gem5 Developers case 0x02: // FADD Sd = Sn + Sm 186610037SARM gem5 Developers return new FAddS(machInst, rd, rn, rm); 186710037SARM gem5 Developers case 0x12: // FADD Dd = Dn + Dm 186810037SARM gem5 Developers return new FAddD(machInst, rd, rn, rm); 186910037SARM gem5 Developers case 0x03: // FSUB Sd = Sn - Sm 187010037SARM gem5 Developers return new FSubS(machInst, rd, rn, rm); 187110037SARM gem5 Developers case 0x13: // FSUB Dd = Dn - Dm 187210037SARM gem5 Developers return new FSubD(machInst, rd, rn, rm); 187310037SARM gem5 Developers case 0x04: // FMAX Sd = max(Sn, Sm) 187410037SARM gem5 Developers return new FMaxS(machInst, rd, rn, rm); 187510037SARM gem5 Developers case 0x14: // FMAX Dd = max(Dn, Dm) 187610037SARM gem5 Developers return new FMaxD(machInst, rd, rn, rm); 187710037SARM gem5 Developers case 0x05: // FMIN Sd = min(Sn, Sm) 187810037SARM gem5 Developers return new FMinS(machInst, rd, rn, rm); 187910037SARM gem5 Developers case 0x15: // FMIN Dd = min(Dn, Dm) 188010037SARM gem5 Developers return new FMinD(machInst, rd, rn, rm); 188110037SARM gem5 Developers case 0x06: // FMAXNM Sd = maxNum(Sn, Sm) 188210037SARM gem5 Developers return new FMaxNMS(machInst, rd, rn, rm); 188310037SARM gem5 Developers case 0x16: // FMAXNM Dd = maxNum(Dn, Dm) 188410037SARM gem5 Developers return new FMaxNMD(machInst, rd, rn, rm); 188510037SARM gem5 Developers case 0x07: // FMINNM Sd = minNum(Sn, Sm) 188610037SARM gem5 Developers return new FMinNMS(machInst, rd, rn, rm); 188710037SARM gem5 Developers case 0x17: // FMINNM Dd = minNum(Dn, Dm) 188810037SARM gem5 Developers return new FMinNMD(machInst, rd, rn, rm); 188910037SARM gem5 Developers case 0x08: // FNMUL Sd = -(Sn * Sm) 189010037SARM gem5 Developers return new FNMulS(machInst, rd, rn, rm); 189110037SARM gem5 Developers case 0x18: // FNMUL Dd = -(Dn * Dm) 189210037SARM gem5 Developers return new FNMulD(machInst, rd, rn, rm); 189310037SARM gem5 Developers default: 189410037SARM gem5 Developers return new Unknown64(machInst); 189510037SARM gem5 Developers } 189610037SARM gem5 Developers } 189710037SARM gem5 Developers case 0x3: 189810037SARM gem5 Developers { 189910037SARM gem5 Developers if (bits(machInst, 31) || bits(machInst, 29)) 190010037SARM gem5 Developers return new Unknown64(machInst); 190110037SARM gem5 Developers uint8_t type = bits(machInst, 23, 22); 190210037SARM gem5 Developers IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0); 190310037SARM gem5 Developers IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5); 190410037SARM gem5 Developers IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16); 190510037SARM gem5 Developers ConditionCode cond = 190610037SARM gem5 Developers (ConditionCode)(uint8_t)(bits(machInst, 15, 12)); 190710037SARM gem5 Developers if (type == 0) // FCSEL Sd = if cond then Sn else Sm 190810037SARM gem5 Developers return new FCSelS(machInst, rd, rn, rm, cond); 190910037SARM gem5 Developers else if (type == 1) // FCSEL Dd = if cond then Dn else Dm 191010037SARM gem5 Developers return new FCSelD(machInst, rd, rn, rm, cond); 191110037SARM gem5 Developers else 191210037SARM gem5 Developers return new Unknown64(machInst); 191310037SARM gem5 Developers } 191410037SARM gem5 Developers } 191510037SARM gem5 Developers } 191610037SARM gem5 Developers return new FailUnimplemented("Unhandled Case4", machInst); 191710037SARM gem5 Developers } 191810037SARM gem5 Developers} 191910037SARM gem5 Developers}}; 192010037SARM gem5 Developers 192110037SARM gem5 Developersoutput decoder {{ 192210037SARM gem5 Developersnamespace Aarch64 192310037SARM gem5 Developers{ 192410037SARM gem5 Developers StaticInstPtr 192510037SARM gem5 Developers decodeAdvSIMDScalar(ExtMachInst machInst) 192610037SARM gem5 Developers { 192710037SARM gem5 Developers if (bits(machInst, 24) == 1) { 192810037SARM gem5 Developers if (bits(machInst, 10) == 0) { 192910037SARM gem5 Developers return decodeNeonScIndexedElem(machInst); 193010037SARM gem5 Developers } else if (bits(machInst, 23) == 0) { 193110037SARM gem5 Developers return decodeNeonScShiftByImm(machInst); 193210037SARM gem5 Developers } 193310037SARM gem5 Developers } else if (bits(machInst, 21) == 1) { 193410037SARM gem5 Developers if (bits(machInst, 10) == 1) { 193510037SARM gem5 Developers return decodeNeonSc3Same(machInst); 193610037SARM gem5 Developers } else if (bits(machInst, 11) == 0) { 193710037SARM gem5 Developers return decodeNeonSc3Diff(machInst); 193810037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x0) { 193910037SARM gem5 Developers return decodeNeonSc2RegMisc(machInst); 194010037SARM gem5 Developers } else if (bits(machInst, 20, 17) == 0x8) { 194110037SARM gem5 Developers return decodeNeonScPwise(machInst); 194210037SARM gem5 Developers } else { 194310037SARM gem5 Developers return new Unknown64(machInst); 194410037SARM gem5 Developers } 194510037SARM gem5 Developers } else if (bits(machInst, 23, 22) == 0 && 194610037SARM gem5 Developers bits(machInst, 15) == 0 && 194710037SARM gem5 Developers bits(machInst, 10) == 1) { 194810037SARM gem5 Developers return decodeNeonScCopy(machInst); 194910037SARM gem5 Developers } else { 195010037SARM gem5 Developers return new Unknown64(machInst); 195110037SARM gem5 Developers } 195210037SARM gem5 Developers return new FailUnimplemented("Unhandled Case6", machInst); 195310037SARM gem5 Developers } 195410037SARM gem5 Developers} 195510037SARM gem5 Developers}}; 195610037SARM gem5 Developers 195710037SARM gem5 Developersoutput decoder {{ 195810037SARM gem5 Developersnamespace Aarch64 195910037SARM gem5 Developers{ 196010037SARM gem5 Developers StaticInstPtr 196110037SARM gem5 Developers decodeFpAdvSIMD(ExtMachInst machInst) 196210037SARM gem5 Developers { 196310037SARM gem5 Developers 196410037SARM gem5 Developers if (bits(machInst, 28) == 0) { 196510037SARM gem5 Developers if (bits(machInst, 31) == 0) { 196610037SARM gem5 Developers return decodeAdvSIMD(machInst); 196710037SARM gem5 Developers } else { 196810037SARM gem5 Developers return new Unknown64(machInst); 196910037SARM gem5 Developers } 197010037SARM gem5 Developers } else if (bits(machInst, 30) == 0) { 197110037SARM gem5 Developers return decodeFp(machInst); 197210037SARM gem5 Developers } else if (bits(machInst, 31) == 0) { 197310037SARM gem5 Developers return decodeAdvSIMDScalar(machInst); 197410037SARM gem5 Developers } else { 197510037SARM gem5 Developers return new Unknown64(machInst); 197610037SARM gem5 Developers } 197710037SARM gem5 Developers } 197810037SARM gem5 Developers} 197910037SARM gem5 Developers}}; 198010037SARM gem5 Developers 198110037SARM gem5 Developersoutput decoder {{ 198210037SARM gem5 Developersnamespace Aarch64 198310037SARM gem5 Developers{ 198410037SARM gem5 Developers StaticInstPtr 198510037SARM gem5 Developers decodeGem5Ops(ExtMachInst machInst) 198610037SARM gem5 Developers { 198710037SARM gem5 Developers const uint32_t m5func = bits(machInst, 23, 16); 198810037SARM gem5 Developers switch (m5func) { 198910037SARM gem5 Developers case 0x00: return new Arm(machInst); 199010037SARM gem5 Developers case 0x01: return new Quiesce(machInst); 199110037SARM gem5 Developers case 0x02: return new QuiesceNs64(machInst); 199210037SARM gem5 Developers case 0x03: return new QuiesceCycles64(machInst); 199310037SARM gem5 Developers case 0x04: return new QuiesceTime64(machInst); 199410037SARM gem5 Developers case 0x07: return new Rpns64(machInst); 199510037SARM gem5 Developers case 0x09: return new WakeCPU64(machInst); 199610037SARM gem5 Developers case 0x10: return new Deprecated_ivlb(machInst); 199710037SARM gem5 Developers case 0x11: return new Deprecated_ivle(machInst); 199810037SARM gem5 Developers case 0x20: return new Deprecated_exit (machInst); 199910037SARM gem5 Developers case 0x21: return new M5exit64(machInst); 200010037SARM gem5 Developers case 0x31: return new Loadsymbol(machInst); 200110037SARM gem5 Developers case 0x30: return new Initparam64(machInst); 200210037SARM gem5 Developers case 0x40: return new Resetstats64(machInst); 200310037SARM gem5 Developers case 0x41: return new Dumpstats64(machInst); 200410037SARM gem5 Developers case 0x42: return new Dumpresetstats64(machInst); 200510037SARM gem5 Developers case 0x43: return new M5checkpoint64(machInst); 200610037SARM gem5 Developers case 0x4F: return new M5writefile64(machInst); 200710037SARM gem5 Developers case 0x50: return new M5readfile64(machInst); 200810037SARM gem5 Developers case 0x51: return new M5break(machInst); 200910037SARM gem5 Developers case 0x52: return new M5switchcpu(machInst); 201010037SARM gem5 Developers case 0x53: return new M5addsymbol64(machInst); 201110037SARM gem5 Developers case 0x54: return new M5panic(machInst); 201210037SARM gem5 Developers case 0x5a: return new M5workbegin64(machInst); 201310037SARM gem5 Developers case 0x5b: return new M5workend64(machInst); 201410037SARM gem5 Developers default: return new Unknown64(machInst); 201510037SARM gem5 Developers } 201610037SARM gem5 Developers } 201710037SARM gem5 Developers} 201810037SARM gem5 Developers}}; 201910037SARM gem5 Developers 202010037SARM gem5 Developersdef format Aarch64() {{ 202110037SARM gem5 Developers decode_block = ''' 202210037SARM gem5 Developers { 202310037SARM gem5 Developers using namespace Aarch64; 202410037SARM gem5 Developers if (bits(machInst, 27) == 0x0) { 202510037SARM gem5 Developers if (bits(machInst, 28) == 0x0) 202610037SARM gem5 Developers return new Unknown64(machInst); 202710037SARM gem5 Developers else if (bits(machInst, 26) == 0) 202810037SARM gem5 Developers // bit 28:26=100 202910037SARM gem5 Developers return decodeDataProcImm(machInst); 203010037SARM gem5 Developers else 203110037SARM gem5 Developers // bit 28:26=101 203210037SARM gem5 Developers return decodeBranchExcSys(machInst); 203310037SARM gem5 Developers } else if (bits(machInst, 25) == 0) { 203410037SARM gem5 Developers // bit 27=1, 25=0 203510037SARM gem5 Developers return decodeLoadsStores(machInst); 203610037SARM gem5 Developers } else if (bits(machInst, 26) == 0) { 203710037SARM gem5 Developers // bit 27:25=101 203810037SARM gem5 Developers return decodeDataProcReg(machInst); 203910037SARM gem5 Developers } else if (bits(machInst, 24) == 1 && 204010037SARM gem5 Developers bits(machInst, 31, 28) == 0xF) { 204110037SARM gem5 Developers return decodeGem5Ops(machInst); 204210037SARM gem5 Developers } else { 204310037SARM gem5 Developers // bit 27:25=111 204410037SARM gem5 Developers return decodeFpAdvSIMD(machInst); 204510037SARM gem5 Developers } 204610037SARM gem5 Developers } 204710037SARM gem5 Developers ''' 204810037SARM gem5 Developers}}; 2049