arm.isa revision 7401:9b873c0357b8
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode COND_CODE { 540xF: ArmUnconditional::armUnconditional(); 55default: decode ENCODING { 56format DataOp { 57 0x0: decode SEVEN_AND_FOUR { 58 1: decode MISC_OPCODE { 59 0x9: decode PREPOST { 60 0: ArmMultAndMultAcc::armMultAndMultAcc(); 61 1: ArmSyncMem::armSyncMem(); 62 } 63 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 64 } 65 0: decode IS_MISC { 66 0: ArmDataProcReg::armDataProcReg(); 67 1: decode OPCODE_7 { 68 0x0: decode MISC_OPCODE { 69 0x0: ArmMsrMrs::armMsrMrs(); 70 // bxj unimplemented, treated as bx 71 0x1,0x2: ArmBxClz::armBxClz(); 72 0x3: decode OPCODE { 73 0x9: ArmBlxReg::armBlxReg(); 74 } 75 0x5: ArmSatAddSub::armSatAddSub(); 76 0x7: Breakpoint::bkpt(); 77 } 78 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 79 } 80 } 81 } 82 0x1: decode IS_MISC { 83 0: ArmDataProcImm::armDataProcImm(); 84 1: decode OPCODE { 85 // The following two instructions aren't supposed to be defined 86 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 87 0x9: decode RN { 88 0: decode IMM { 89 0: PredImmOp::nop({{ ; }}); 90#if FULL_SYSTEM 91 1: PredImmOp::yield({{ ; }}); 92 2: PredImmOp::wfe({{ 93 if (SevMailbox) 94 SevMailbox = 0; 95 else 96 PseudoInst::quiesce(xc->tcBase()); 97 }}, IsNonSpeculative, IsQuiesce); 98 3: PredImmOp::wfi({{ 99 PseudoInst::quiesce(xc->tcBase()); 100 }}, IsNonSpeculative, IsQuiesce); 101 4: PredImmOp::sev({{ 102 // Need a way for O3 to not scoreboard these 103 // accesses as pipeflushs 104 System *sys = xc->tcBase()->getSystemPtr(); 105 for (int x = 0; x < sys->numContexts(); x++) { 106 ThreadContext *oc = sys->getThreadContext(x); 107 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 108 } 109 }}); 110#endif 111 } 112 default: PredImmOp::msr_i_cpsr({{ 113 SCTLR sctlr = Sctlr; 114 uint32_t newCpsr = 115 cpsrWriteByInstr(Cpsr | CondCodes, 116 rotated_imm, RN, false, sctlr.nmfi); 117 Cpsr = ~CondCodesMask & newCpsr; 118 CondCodes = CondCodesMask & newCpsr; 119 }}); 120 } 121 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 122 0xb: PredImmOp::msr_i_spsr({{ 123 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 124 }}); 125 } 126 } 127 0x2: AddrMode2::addrMode2(True); 128 0x3: decode OPCODE_4 { 129 0: AddrMode2::addrMode2(False); 130 1: decode OPCODE_24_23 { 131 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 132 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 133 0x2: ArmSignedMultiplies::armSignedMultiplies(); 134 0x3: ArmMiscMedia::armMiscMedia(); 135 } 136 } 137 0x4: ArmMacroMem::armMacroMem(); 138 0x5: decode OPCODE_24 { 139 0: ArmBBlxImm::armBBlxImm(); 140 1: ArmBlBlxImm::armBlBlxImm(); 141 } 142 0x6: decode CPNUM { 143 0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 144 } 145 0x7: decode OPCODE_24 { 146 0: decode OPCODE_4 { 147 0: decode CPNUM { 148 0xa, 0xb: VfpData::vfpData(); 149 } // CPNUM 150 1: decode CPNUM { // 27-24=1110,4 ==1 151 1: decode OPCODE_15_12 { 152 format FloatOp { 153 0xf: decode OPCODE_23_21 { 154 format FloatCmp { 155 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 156 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 157 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 158 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 159 } 160 } 161 default: decode OPCODE_23_20 { 162 0x0: decode OPCODE_7 { 163 0: flts({{ Fn.sf = (float) Rd.sw; }}); 164 1: fltd({{ Fn.df = (double) Rd.sw; }}); 165 } 166 0x1: decode OPCODE_7 { 167 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 168 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 169 } 170 0x2: wfs({{ Fpsr = Rd; }}); 171 0x3: rfs({{ Rd = Fpsr; }}); 172 0x4: FailUnimpl::wfc(); 173 0x5: FailUnimpl::rfc(); 174 } 175 } // format FloatOp 176 } 177 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 178 0xf: McrMrc15::mcrMrc15(); 179 } // CPNUM (OP4 == 1) 180 } //OPCODE_4 181 182 1: Svc::svc(); 183 } // OPCODE_24 184 185} 186} 187} 188 189