arm.isa revision 7321:d0fdf3452086
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode COND_CODE { 540xF: ArmUnconditional::armUnconditional(); 55default: decode ENCODING { 56format DataOp { 57 0x0: decode SEVEN_AND_FOUR { 58 1: decode MISC_OPCODE { 59 0x9: decode PREPOST { 60 0: ArmMultAndMultAcc::armMultAndMultAcc(); 61 1: ArmSyncMem::armSyncMem(); 62 } 63 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 64 } 65 0: decode IS_MISC { 66 0: ArmDataProcReg::armDataProcReg(); 67 1: decode OPCODE_7 { 68 0x0: decode MISC_OPCODE { 69 0x0: ArmMsrMrs::armMsrMrs(); 70 0x1: ArmBxClz::armBxClz(); 71 0x2: decode OPCODE { 72 0x9: WarnUnimpl::bxj(); 73 } 74 0x3: decode OPCODE { 75 0x9: ArmBlxReg::armBlxReg(); 76 } 77 0x5: ArmSatAddSub::armSatAddSub(); 78 } 79 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 80 } 81 } 82 } 83 0x1: decode IS_MISC { 84 0: ArmDataProcImm::armDataProcImm(); 85 1: decode OPCODE { 86 // The following two instructions aren't supposed to be defined 87 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 88 0x9: decode RN { 89 0: decode IMM { 90 0: PredImmOp::nop({{ ; }}); 91 1: WarnUnimpl::yield(); 92 2: WarnUnimpl::wfe(); 93 3: WarnUnimpl::wfi(); 94 4: WarnUnimpl::sev(); 95 } 96 default: PredImmOp::msr_i_cpsr({{ 97 uint32_t newCpsr = 98 cpsrWriteByInstr(Cpsr | CondCodes, 99 rotated_imm, RN, false); 100 Cpsr = ~CondCodesMask & newCpsr; 101 CondCodes = CondCodesMask & newCpsr; 102 }}); 103 } 104 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 105 0xb: PredImmOp::msr_i_spsr({{ 106 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 107 }}); 108 } 109 } 110 0x2: AddrMode2::addrMode2(True); 111 0x3: decode OPCODE_4 { 112 0: AddrMode2::addrMode2(False); 113 1: decode OPCODE_24_23 { 114 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 115 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 116 0x2: ArmSignedMultiplies::armSignedMultiplies(); 117 0x3: ArmMiscMedia::armMiscMedia(); 118 } 119 } 120 0x4: ArmMacroMem::armMacroMem(); 121 0x5: decode OPCODE_24 { 122 0: ArmBBlxImm::armBBlxImm(); 123 1: ArmBlBlxImm::armBlBlxImm(); 124 } 125 0x6: decode CPNUM { 126 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 127 } 128 0x7: decode OPCODE_24 { 129 0: decode OPCODE_4 { 130 0: decode CPNUM { 131 0xa, 0xb: decode OPCODE_23_20 { 132##include "vfp.isa" 133 } 134 } // CPNUM 135 1: decode CPNUM { // 27-24=1110,4 ==1 136 1: decode OPCODE_15_12 { 137 format FloatOp { 138 0xf: decode OPCODE_23_21 { 139 format FloatCmp { 140 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 141 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 142 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 143 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 144 } 145 } 146 default: decode OPCODE_23_20 { 147 0x0: decode OPCODE_7 { 148 0: flts({{ Fn.sf = (float) Rd.sw; }}); 149 1: fltd({{ Fn.df = (double) Rd.sw; }}); 150 } 151 0x1: decode OPCODE_7 { 152 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 153 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 154 } 155 0x2: wfs({{ Fpsr = Rd; }}); 156 0x3: rfs({{ Rd = Fpsr; }}); 157 0x4: FailUnimpl::wfc(); 158 0x5: FailUnimpl::rfc(); 159 } 160 } // format FloatOp 161 } 162 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); 163 0xf: McrMrc15::mcrMrc15(); 164 } // CPNUM (OP4 == 1) 165 } //OPCODE_4 166 167 1: Svc::svc(); 168 } // OPCODE_24 169 170} 171} 172} 173 174