arm.isa revision 7203:39753c33e7aa
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode COND_CODE { 540xF: ArmUnconditional::armUnconditional(); 55default: decode ENCODING { 56format DataOp { 57 0x0: decode SEVEN_AND_FOUR { 58 1: decode MISC_OPCODE { 59 0x9: decode PREPOST { 60 0: ArmMultAndMultAcc::armMultAndMultAcc(); 61 1: decode PUBWL { 62 0x10: WarnUnimpl::swp(); 63 0x14: WarnUnimpl::swpb(); 64 0x18: WarnUnimpl::strex(); 65 0x19: WarnUnimpl::ldrex(); 66 } 67 } 68 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 69 } 70 0: decode IS_MISC { 71 0: ArmDataProcReg::armDataProcReg(); 72 1: decode OPCODE_7 { 73 0x0: decode MISC_OPCODE { 74 0x0: ArmMsrMrs::armMsrMrs(); 75 0x1: decode OPCODE { 76 0x9: ArmBx::armBx(); 77 0xb: PredOp::clz({{ 78 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 79 }}); 80 } 81 0x2: decode OPCODE { 82 0x9: WarnUnimpl::bxj(); 83 } 84 0x3: decode OPCODE { 85 0x9: ArmBlxReg::armBlxReg(); 86 } 87 0x5: ArmSatAddSub::armSatAddSub(); 88 } 89 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 90 } 91 } 92 } 93 0x1: decode IS_MISC { 94 0: ArmDataProcImm::armDataProcImm(); 95 1: decode OPCODE { 96 // The following two instructions aren't supposed to be defined 97 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 98 0x9: decode RN { 99 0: decode IMM { 100 0: PredImmOp::nop({{ ; }}); 101 1: WarnUnimpl::yield(); 102 2: WarnUnimpl::wfe(); 103 3: WarnUnimpl::wfi(); 104 4: WarnUnimpl::sev(); 105 } 106 default: PredImmOp::msr_i_cpsr({{ 107 uint32_t newCpsr = 108 cpsrWriteByInstr(Cpsr | CondCodes, 109 rotated_imm, RN, false); 110 Cpsr = ~CondCodesMask & newCpsr; 111 CondCodes = CondCodesMask & newCpsr; 112 }}); 113 } 114 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 115 0xb: PredImmOp::msr_i_spsr({{ 116 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 117 }}); 118 } 119 } 120 0x2: AddrMode2::addrMode2(True); 121 0x3: decode OPCODE_4 { 122 0: AddrMode2::addrMode2(False); 123 1: decode OPCODE_24_23 { 124 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 125 0x1: decode MEDIA_OPCODE { 126 0x8: decode MISC_OPCODE { 127 0x1, 0x9: WarnUnimpl::pkhbt(); 128 0x7: WarnUnimpl::sxtab16(); 129 0xb: WarnUnimpl::sel(); 130 0x5, 0xd: WarnUnimpl::pkhtb(); 131 0x3: WarnUnimpl::sign_zero_extend_add(); 132 } 133 0xa, 0xb: decode SHIFT { 134 0x0, 0x2: WarnUnimpl::ssat(); 135 0x1: WarnUnimpl::ssat16(); 136 } 137 0xe, 0xf: decode SHIFT { 138 0x0, 0x2: WarnUnimpl::usat(); 139 0x1: WarnUnimpl::usat16(); 140 } 141 } 142 0x2: ArmSignedMultiplies::armSignedMultiplies(); 143 0x3: decode MEDIA_OPCODE { 144 0x18: decode RN { 145 0xf: WarnUnimpl::usada8(); 146 default: WarnUnimpl::usad8(); 147 } 148 } 149 } 150 } 151 0x4: ArmMacroMem::armMacroMem(); 152 0x5: decode OPCODE_24 { 153 0: ArmBBlxImm::armBBlxImm(); 154 1: ArmBlBlxImm::armBlBlxImm(); 155 } 156 0x6: decode CPNUM { 157 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 158 } 159 0x7: decode OPCODE_24 { 160 0: decode OPCODE_4 { 161 0: decode CPNUM { 162 0xa, 0xb: decode OPCODE_23_20 { 163##include "vfp.isa" 164 } 165 } // CPNUM 166 1: decode CPNUM { // 27-24=1110,4 ==1 167 1: decode OPCODE_15_12 { 168 format FloatOp { 169 0xf: decode OPCODE_23_21 { 170 format FloatCmp { 171 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 172 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 173 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 174 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 175 } 176 } 177 default: decode OPCODE_23_20 { 178 0x0: decode OPCODE_7 { 179 0: flts({{ Fn.sf = (float) Rd.sw; }}); 180 1: fltd({{ Fn.df = (double) Rd.sw; }}); 181 } 182 0x1: decode OPCODE_7 { 183 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 184 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 185 } 186 0x2: wfs({{ Fpsr = Rd; }}); 187 0x3: rfs({{ Rd = Fpsr; }}); 188 0x4: FailUnimpl::wfc(); 189 0x5: FailUnimpl::rfc(); 190 } 191 } // format FloatOp 192 } 193 0xa: decode MISC_OPCODE { 194 0x1: decode MEDIA_OPCODE { 195 0xf: decode RN { 196 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 197 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 198 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 199 } 200 0xe: decode RN { 201 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 202 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 203 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 204 } 205 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 206 } // MISC_OPCODE (CPNUM 0xA) 207 0xf: decode RN { 208 // Barrriers, Cache Maintence, NOPS 209 7: decode OPCODE_23_21 { 210 0: decode RM { 211 0: decode OPC2 { 212 4: decode OPCODE_20 { 213 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 214 } 215 } 216 1: WarnUnimpl::cp15_cache_maint(); 217 4: WarnUnimpl::cp15_par(); 218 5: decode OPC2 { 219 0,1: WarnUnimpl::cp15_cache_maint2(); 220 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 221 6,7: WarnUnimpl::cp15_bp_maint(); 222 } 223 6: WarnUnimpl::cp15_cache_maint3(); 224 8: WarnUnimpl::cp15_va_to_pa(); 225 10: decode OPC2 { 226 1,2: WarnUnimpl::cp15_cache_maint3(); 227 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 228 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 229 } 230 11: WarnUnimpl::cp15_cache_maint4(); 231 13: decode OPC2 { 232 1: decode OPCODE_20 { 233 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 234 } 235 } 236 14: WarnUnimpl::cp15_cache_maint5(); 237 } // RM 238 } // OPCODE_23_21 CR 239 240 // Thread ID and context ID registers 241 // Thread ID register needs cheaper access than miscreg 242 13: WarnUnimpl::mcr_mrc_cp15_c7(); 243 244 // All the rest 245 default: decode OPCODE_20 { 246 0: PredOp::mcr_cp15({{ 247 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 248 }}); 249 1: PredOp::mrc_cp15({{ 250 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 251 }}); 252 } 253 } // RN 254 } // CPNUM (OP4 == 1) 255 } //OPCODE_4 256 257 1: Svc::svc(); 258 } // OPCODE_24 259 260} 261} 262} 263 264