arm.isa revision 7195:ccd270981263
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode COND_CODE { 540xF: ArmUnconditional::armUnconditional(); 55default: decode ENCODING { 56format DataOp { 57 0x0: decode SEVEN_AND_FOUR { 58 1: decode MISC_OPCODE { 59 0x9: decode PREPOST { 60 0: ArmMultAndMultAcc::armMultAndMultAcc(); 61 1: decode PUBWL { 62 0x10: WarnUnimpl::swp(); 63 0x14: WarnUnimpl::swpb(); 64 0x18: WarnUnimpl::strex(); 65 0x19: WarnUnimpl::ldrex(); 66 } 67 } 68 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 69 } 70 0: decode IS_MISC { 71 0: ArmDataProcReg::armDataProcReg(); 72 1: decode OPCODE_7 { 73 0x0: decode MISC_OPCODE { 74 0x0: decode OPCODE { 75 0x8: PredOp::mrs_cpsr({{ 76 Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 77 }}); 78 0x9: decode USEIMM { 79 // The mask field is the same as the RN index. 80 0: PredOp::msr_cpsr_reg({{ 81 uint32_t newCpsr = 82 cpsrWriteByInstr(Cpsr | CondCodes, 83 Rm, RN, false); 84 Cpsr = ~CondCodesMask & newCpsr; 85 CondCodes = CondCodesMask & newCpsr; 86 }}); 87 1: PredImmOp::msr_cpsr_imm({{ 88 uint32_t newCpsr = 89 cpsrWriteByInstr(Cpsr | CondCodes, 90 rotated_imm, RN, false); 91 Cpsr = ~CondCodesMask & newCpsr; 92 CondCodes = CondCodesMask & newCpsr; 93 }}); 94 } 95 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 96 0xb: decode USEIMM { 97 // The mask field is the same as the RN index. 98 0: PredOp::msr_spsr_reg({{ 99 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 100 }}); 101 1: PredImmOp::msr_spsr_imm({{ 102 Spsr = spsrWriteByInstr(Spsr, rotated_imm, 103 RN, false); 104 }}); 105 } 106 } 107 0x1: decode OPCODE { 108 0x9: ArmBx::armBx(); 109 0xb: PredOp::clz({{ 110 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 111 }}); 112 } 113 0x2: decode OPCODE { 114 0x9: WarnUnimpl::bxj(); 115 } 116 0x3: decode OPCODE { 117 0x9: ArmBlxReg::armBlxReg(); 118 } 119 0x5: ArmSatAddSub::armSatAddSub(); 120 } 121 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 122 } 123 } 124 } 125 0x1: decode IS_MISC { 126 0: ArmDataProcImm::armDataProcImm(); 127 1: decode OPCODE { 128 // The following two instructions aren't supposed to be defined 129 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 130 0x9: decode RN { 131 0: decode IMM { 132 0: PredImmOp::nop({{ ; }}); 133 1: WarnUnimpl::yield(); 134 2: WarnUnimpl::wfe(); 135 3: WarnUnimpl::wfi(); 136 4: WarnUnimpl::sev(); 137 } 138 default: PredImmOp::msr_i_cpsr({{ 139 uint32_t newCpsr = 140 cpsrWriteByInstr(Cpsr | CondCodes, 141 rotated_imm, RN, false); 142 Cpsr = ~CondCodesMask & newCpsr; 143 CondCodes = CondCodesMask & newCpsr; 144 }}); 145 } 146 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 147 0xb: PredImmOp::msr_i_spsr({{ 148 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 149 }}); 150 } 151 } 152 0x2: AddrMode2::addrMode2(True); 153 0x3: decode OPCODE_4 { 154 0: AddrMode2::addrMode2(False); 155 1: decode OPCODE_24_23 { 156 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 157 0x1: decode MEDIA_OPCODE { 158 0x8: decode MISC_OPCODE { 159 0x1, 0x9: WarnUnimpl::pkhbt(); 160 0x7: WarnUnimpl::sxtab16(); 161 0xb: WarnUnimpl::sel(); 162 0x5, 0xd: WarnUnimpl::pkhtb(); 163 0x3: WarnUnimpl::sign_zero_extend_add(); 164 } 165 0xa, 0xb: decode SHIFT { 166 0x0, 0x2: WarnUnimpl::ssat(); 167 0x1: WarnUnimpl::ssat16(); 168 } 169 0xe, 0xf: decode SHIFT { 170 0x0, 0x2: WarnUnimpl::usat(); 171 0x1: WarnUnimpl::usat16(); 172 } 173 } 174 0x2: ArmSignedMultiplies::armSignedMultiplies(); 175 0x3: decode MEDIA_OPCODE { 176 0x18: decode RN { 177 0xf: WarnUnimpl::usada8(); 178 default: WarnUnimpl::usad8(); 179 } 180 } 181 } 182 } 183 0x4: ArmMacroMem::armMacroMem(); 184 0x5: decode OPCODE_24 { 185 0: ArmBBlxImm::armBBlxImm(); 186 1: ArmBlBlxImm::armBlBlxImm(); 187 } 188 0x6: decode CPNUM { 189 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 190 } 191 0x7: decode OPCODE_24 { 192 0: decode OPCODE_4 { 193 0: decode CPNUM { 194 0xa, 0xb: decode OPCODE_23_20 { 195##include "vfp.isa" 196 } 197 } // CPNUM 198 1: decode CPNUM { // 27-24=1110,4 ==1 199 1: decode OPCODE_15_12 { 200 format FloatOp { 201 0xf: decode OPCODE_23_21 { 202 format FloatCmp { 203 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 204 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 205 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 206 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 207 } 208 } 209 default: decode OPCODE_23_20 { 210 0x0: decode OPCODE_7 { 211 0: flts({{ Fn.sf = (float) Rd.sw; }}); 212 1: fltd({{ Fn.df = (double) Rd.sw; }}); 213 } 214 0x1: decode OPCODE_7 { 215 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 216 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 217 } 218 0x2: wfs({{ Fpsr = Rd; }}); 219 0x3: rfs({{ Rd = Fpsr; }}); 220 0x4: FailUnimpl::wfc(); 221 0x5: FailUnimpl::rfc(); 222 } 223 } // format FloatOp 224 } 225 0xa: decode MISC_OPCODE { 226 0x1: decode MEDIA_OPCODE { 227 0xf: decode RN { 228 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 229 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 230 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 231 } 232 0xe: decode RN { 233 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 234 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 235 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 236 } 237 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 238 } // MISC_OPCODE (CPNUM 0xA) 239 0xf: decode RN { 240 // Barrriers, Cache Maintence, NOPS 241 7: decode OPCODE_23_21 { 242 0: decode RM { 243 0: decode OPC2 { 244 4: decode OPCODE_20 { 245 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 246 } 247 } 248 1: WarnUnimpl::cp15_cache_maint(); 249 4: WarnUnimpl::cp15_par(); 250 5: decode OPC2 { 251 0,1: WarnUnimpl::cp15_cache_maint2(); 252 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 253 6,7: WarnUnimpl::cp15_bp_maint(); 254 } 255 6: WarnUnimpl::cp15_cache_maint3(); 256 8: WarnUnimpl::cp15_va_to_pa(); 257 10: decode OPC2 { 258 1,2: WarnUnimpl::cp15_cache_maint3(); 259 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 260 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 261 } 262 11: WarnUnimpl::cp15_cache_maint4(); 263 13: decode OPC2 { 264 1: decode OPCODE_20 { 265 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 266 } 267 } 268 14: WarnUnimpl::cp15_cache_maint5(); 269 } // RM 270 } // OPCODE_23_21 CR 271 272 // Thread ID and context ID registers 273 // Thread ID register needs cheaper access than miscreg 274 13: WarnUnimpl::mcr_mrc_cp15_c7(); 275 276 // All the rest 277 default: decode OPCODE_20 { 278 0: PredOp::mcr_cp15({{ 279 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 280 }}); 281 1: PredOp::mrc_cp15({{ 282 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 283 }}); 284 } 285 } // RN 286 } // CPNUM (OP4 == 1) 287 } //OPCODE_4 288 289#if FULL_SYSTEM 290 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 291#else 292 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 293 { 294 if (IMMED_23_0) 295 xc->syscall(IMMED_23_0); 296 else 297 xc->syscall(R7); 298 } 299 }}); 300#endif // FULL_SYSTEM 301 } // OPCODE_24 302 303} 304} 305} 306 307