arm.isa revision 7194:f72dc8789553
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode COND_CODE { 540xF: ArmUnconditional::armUnconditional(); 55default: decode ENCODING { 56format DataOp { 57 0x0: decode SEVEN_AND_FOUR { 58 1: decode MISC_OPCODE { 59 0x9: decode PREPOST { 60 0: ArmMultAndMultAcc::armMultAndMultAcc(); 61 1: decode PUBWL { 62 0x10: WarnUnimpl::swp(); 63 0x14: WarnUnimpl::swpb(); 64 0x18: WarnUnimpl::strex(); 65 0x19: WarnUnimpl::ldrex(); 66 } 67 } 68 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 69 } 70 0: decode IS_MISC { 71 0: ArmDataProcReg::armDataProcReg(); 72 1: decode OPCODE_7 { 73 0x0: decode MISC_OPCODE { 74 0x0: decode OPCODE { 75 0x8: PredOp::mrs_cpsr({{ 76 Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 77 }}); 78 0x9: decode USEIMM { 79 // The mask field is the same as the RN index. 80 0: PredOp::msr_cpsr_reg({{ 81 uint32_t newCpsr = 82 cpsrWriteByInstr(Cpsr | CondCodes, 83 Rm, RN, false); 84 Cpsr = ~CondCodesMask & newCpsr; 85 CondCodes = CondCodesMask & newCpsr; 86 }}); 87 1: PredImmOp::msr_cpsr_imm({{ 88 uint32_t newCpsr = 89 cpsrWriteByInstr(Cpsr | CondCodes, 90 rotated_imm, RN, false); 91 Cpsr = ~CondCodesMask & newCpsr; 92 CondCodes = CondCodesMask & newCpsr; 93 }}); 94 } 95 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 96 0xb: decode USEIMM { 97 // The mask field is the same as the RN index. 98 0: PredOp::msr_spsr_reg({{ 99 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 100 }}); 101 1: PredImmOp::msr_spsr_imm({{ 102 Spsr = spsrWriteByInstr(Spsr, rotated_imm, 103 RN, false); 104 }}); 105 } 106 } 107 0x1: decode OPCODE { 108 0x9: ArmBx::armBx(); 109 0xb: PredOp::clz({{ 110 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 111 }}); 112 } 113 0x2: decode OPCODE { 114 0x9: WarnUnimpl::bxj(); 115 } 116 0x3: decode OPCODE { 117 0x9: ArmBlxReg::armBlxReg(); 118 } 119 0x5: decode OPCODE { 120 0x8: WarnUnimpl::qadd(); 121 0x9: WarnUnimpl::qsub(); 122 0xa: WarnUnimpl::qdadd(); 123 0xb: WarnUnimpl::qdsub(); 124 } 125 } 126 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc(); 127 } 128 } 129 } 130 0x1: decode IS_MISC { 131 0: ArmDataProcImm::armDataProcImm(); 132 1: decode OPCODE { 133 // The following two instructions aren't supposed to be defined 134 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 135 0x9: decode RN { 136 0: decode IMM { 137 0: PredImmOp::nop({{ ; }}); 138 1: WarnUnimpl::yield(); 139 2: WarnUnimpl::wfe(); 140 3: WarnUnimpl::wfi(); 141 4: WarnUnimpl::sev(); 142 } 143 default: PredImmOp::msr_i_cpsr({{ 144 uint32_t newCpsr = 145 cpsrWriteByInstr(Cpsr | CondCodes, 146 rotated_imm, RN, false); 147 Cpsr = ~CondCodesMask & newCpsr; 148 CondCodes = CondCodesMask & newCpsr; 149 }}); 150 } 151 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 152 0xb: PredImmOp::msr_i_spsr({{ 153 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 154 }}); 155 } 156 } 157 0x2: AddrMode2::addrMode2(True); 158 0x3: decode OPCODE_4 { 159 0: AddrMode2::addrMode2(False); 160 1: decode OPCODE_24_23 { 161 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); 162 0x1: decode MEDIA_OPCODE { 163 0x8: decode MISC_OPCODE { 164 0x1, 0x9: WarnUnimpl::pkhbt(); 165 0x7: WarnUnimpl::sxtab16(); 166 0xb: WarnUnimpl::sel(); 167 0x5, 0xd: WarnUnimpl::pkhtb(); 168 0x3: WarnUnimpl::sign_zero_extend_add(); 169 } 170 0xa, 0xb: decode SHIFT { 171 0x0, 0x2: WarnUnimpl::ssat(); 172 0x1: WarnUnimpl::ssat16(); 173 } 174 0xe, 0xf: decode SHIFT { 175 0x0, 0x2: WarnUnimpl::usat(); 176 0x1: WarnUnimpl::usat16(); 177 } 178 } 179 0x2: ArmSignedMultiplies::armSignedMultiplies(); 180 0x3: decode MEDIA_OPCODE { 181 0x18: decode RN { 182 0xf: WarnUnimpl::usada8(); 183 default: WarnUnimpl::usad8(); 184 } 185 } 186 } 187 } 188 0x4: ArmMacroMem::armMacroMem(); 189 0x5: decode OPCODE_24 { 190 0: ArmBBlxImm::armBBlxImm(); 191 1: ArmBlBlxImm::armBlBlxImm(); 192 } 193 0x6: decode CPNUM { 194 0xb: ExtensionRegLoadStore::extensionRegLoadStore(); 195 } 196 0x7: decode OPCODE_24 { 197 0: decode OPCODE_4 { 198 0: decode CPNUM { 199 0xa, 0xb: decode OPCODE_23_20 { 200##include "vfp.isa" 201 } 202 } // CPNUM 203 1: decode CPNUM { // 27-24=1110,4 ==1 204 1: decode OPCODE_15_12 { 205 format FloatOp { 206 0xf: decode OPCODE_23_21 { 207 format FloatCmp { 208 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 209 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 210 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 211 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 212 } 213 } 214 default: decode OPCODE_23_20 { 215 0x0: decode OPCODE_7 { 216 0: flts({{ Fn.sf = (float) Rd.sw; }}); 217 1: fltd({{ Fn.df = (double) Rd.sw; }}); 218 } 219 0x1: decode OPCODE_7 { 220 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 221 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 222 } 223 0x2: wfs({{ Fpsr = Rd; }}); 224 0x3: rfs({{ Rd = Fpsr; }}); 225 0x4: FailUnimpl::wfc(); 226 0x5: FailUnimpl::rfc(); 227 } 228 } // format FloatOp 229 } 230 0xa: decode MISC_OPCODE { 231 0x1: decode MEDIA_OPCODE { 232 0xf: decode RN { 233 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 234 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 235 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 236 } 237 0xe: decode RN { 238 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 239 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 240 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 241 } 242 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 243 } // MISC_OPCODE (CPNUM 0xA) 244 0xf: decode RN { 245 // Barrriers, Cache Maintence, NOPS 246 7: decode OPCODE_23_21 { 247 0: decode RM { 248 0: decode OPC2 { 249 4: decode OPCODE_20 { 250 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 251 } 252 } 253 1: WarnUnimpl::cp15_cache_maint(); 254 4: WarnUnimpl::cp15_par(); 255 5: decode OPC2 { 256 0,1: WarnUnimpl::cp15_cache_maint2(); 257 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 258 6,7: WarnUnimpl::cp15_bp_maint(); 259 } 260 6: WarnUnimpl::cp15_cache_maint3(); 261 8: WarnUnimpl::cp15_va_to_pa(); 262 10: decode OPC2 { 263 1,2: WarnUnimpl::cp15_cache_maint3(); 264 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 265 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 266 } 267 11: WarnUnimpl::cp15_cache_maint4(); 268 13: decode OPC2 { 269 1: decode OPCODE_20 { 270 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 271 } 272 } 273 14: WarnUnimpl::cp15_cache_maint5(); 274 } // RM 275 } // OPCODE_23_21 CR 276 277 // Thread ID and context ID registers 278 // Thread ID register needs cheaper access than miscreg 279 13: WarnUnimpl::mcr_mrc_cp15_c7(); 280 281 // All the rest 282 default: decode OPCODE_20 { 283 0: PredOp::mcr_cp15({{ 284 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 285 }}); 286 1: PredOp::mrc_cp15({{ 287 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 288 }}); 289 } 290 } // RN 291 } // CPNUM (OP4 == 1) 292 } //OPCODE_4 293 294#if FULL_SYSTEM 295 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 296#else 297 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 298 { 299 if (IMMED_23_0) 300 xc->syscall(IMMED_23_0); 301 else 302 xc->syscall(R7); 303 } 304 }}); 305#endif // FULL_SYSTEM 306 } // OPCODE_24 307 308} 309} 310} 311 312