bitfields.isa revision 6251:1d794d81a4e6
12810SN/A// -*- mode:c++ -*- 22810SN/A 32810SN/A// Copyright (c) 2007-2008 The Florida State University 42810SN/A// All rights reserved. 52810SN/A// 62810SN/A// Redistribution and use in source and binary forms, with or without 72810SN/A// modification, are permitted provided that the following conditions are 82810SN/A// met: redistributions of source code must retain the above copyright 92810SN/A// notice, this list of conditions and the following disclaimer; 102810SN/A// redistributions in binary form must reproduce the above copyright 112810SN/A// notice, this list of conditions and the following disclaimer in the 122810SN/A// documentation and/or other materials provided with the distribution; 132810SN/A// neither the name of the copyright holders nor the names of its 142810SN/A// contributors may be used to endorse or promote products derived from 152810SN/A// this software without specific prior written permission. 162810SN/A// 172810SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A// 292810SN/A// Authors: Stephen Hines 302810SN/A 312810SN/A//////////////////////////////////////////////////////////////////// 322810SN/A// 333861SN/A// Bitfield definitions. 342810SN/A// 352810SN/A 362810SN/A// Opcode fields 372810SN/Adef bitfield OPCODE opcode; 382810SN/Adef bitfield OPCODE_27_25 opcode27_25; 398229Snate@binkert.orgdef bitfield OPCODE_24_21 opcode24_21; 408229Snate@binkert.orgdef bitfield OPCODE_24_23 opcode24_23; 415338Sstever@gmail.comdef bitfield OPCODE_24 opcode24; 422810SN/Adef bitfield OPCODE_23_20 opcode23_20; 433861SN/Adef bitfield OPCODE_23_21 opcode23_21; 442810SN/Adef bitfield OPCODE_23 opcode23; 452810SN/Adef bitfield OPCODE_22_8 opcode22_8; 462810SN/Adef bitfield OPCODE_22_21 opcode22_21; 475875Ssteve.reinhardt@amd.comdef bitfield OPCODE_22 opcode22; 485875Ssteve.reinhardt@amd.comdef bitfield OPCODE_21_20 opcode21_20; 495875Ssteve.reinhardt@amd.comdef bitfield OPCODE_20 opcode20; 505875Ssteve.reinhardt@amd.comdef bitfield OPCODE_19_18 opcode19_18; 515875Ssteve.reinhardt@amd.comdef bitfield OPCODE_19 opcode19; 525875Ssteve.reinhardt@amd.comdef bitfield OPCODE_15_12 opcode15_12; 535875Ssteve.reinhardt@amd.comdef bitfield OPCODE_15 opcode15; 545875Ssteve.reinhardt@amd.comdef bitfield OPCODE_9 opcode9; 552810SN/Adef bitfield OPCODE_7_4 opcode7_4; 562810SN/Adef bitfield OPCODE_7_5 opcode7_5; 575875Ssteve.reinhardt@amd.comdef bitfield OPCODE_7_6 opcode7_6; 585875Ssteve.reinhardt@amd.comdef bitfield OPCODE_7 opcode7; 592810SN/Adef bitfield OPCODE_6_5 opcode6_5; 605875Ssteve.reinhardt@amd.comdef bitfield OPCODE_6 opcode6; 615875Ssteve.reinhardt@amd.comdef bitfield OPCODE_5 opcode5; 622810SN/Adef bitfield OPCODE_4 opcode4; 635875Ssteve.reinhardt@amd.com 642810SN/A// Other 655875Ssteve.reinhardt@amd.comdef bitfield COND_CODE condCode; 662810SN/Adef bitfield S_FIELD sField; 672810SN/Adef bitfield RN rn; 685714Shsul@eecs.umich.edudef bitfield RD rd; 692810SN/Adef bitfield SHIFT_SIZE shiftSize; 702810SN/Adef bitfield SHIFT shift; 712810SN/Adef bitfield RM rm; 725034SN/A 735034SN/Adef bitfield RS rs; 745714Shsul@eecs.umich.edu 752810SN/Adef bitfield RDUP rdup; 762810SN/Adef bitfield RNDN rddn; 772810SN/A 782810SN/Adef bitfield RDHI rdhi; 792810SN/Adef bitfield RDLO rdlo; 803349SN/A 813861SN/Adef bitfield U_FIELD uField; 822810SN/A 832810SN/Adef bitfield PUSWL puswl; 842810SN/Adef bitfield PREPOST puswl.prepost; 85def bitfield UP puswl.up; 86def bitfield PSRUSER puswl.psruser; 87def bitfield WRITEBACK puswl.writeback; 88def bitfield LOADOP puswl.loadOp; 89 90def bitfield PUBWL pubwl; 91def bitfield PUIWL puiwl; 92def bitfield BYTEACCESS byteAccess; 93 94def bitfield LUAS luas; 95 96def bitfield IMM imm; 97def bitfield IMMED_7_4 immed7_4; 98def bitfield IMMED_3_0 immed3_0; 99 100def bitfield F_MSR msr.f; 101def bitfield S_MSR msr.s; 102def bitfield X_MSR msr.x; 103def bitfield C_MSR msr.c; 104 105def bitfield Y_6 y; 106def bitfield X_5 x; 107 108def bitfield IMMED_15_4 immed15_4; 109 110def bitfield W_FIELD wField; 111 112def bitfield ROTATE rotate; 113def bitfield IMMED_7_0 immed7_0; 114 115def bitfield T_FIELD tField; 116def bitfield IMMED_11_0 immed11_0; 117 118def bitfield IMMED_20_16 immed20_16; 119def bitfield IMMED_19_16 immed19_16; 120 121def bitfield IMMED_HI_11_8 immedHi11_8; 122def bitfield IMMED_LO_3_0 immedLo3_0; 123 124def bitfield ROT rot; 125 126def bitfield R_FIELD rField; 127 128def bitfield CARET caret; 129def bitfield REGLIST regList; 130 131def bitfield OFFSET offset; 132def bitfield COPRO copro; 133def bitfield OP1_7_4 op1_7_4; 134def bitfield CM cm; 135 136def bitfield L_FIELD lField; 137def bitfield CD cd; 138def bitfield OPTION option; 139 140def bitfield OP1_23_20 op1_23_20; 141def bitfield CN cn; 142def bitfield OP2_7_5 op2_7_5; 143 144def bitfield OP1_23_21 op1_23_21; 145 146def bitfield IMMED_23_0 immed23_0; 147def bitfield M_FIELD mField; 148def bitfield A_FIELD aField; 149def bitfield I_FIELD iField; 150def bitfield F_FIELD fField; 151def bitfield MODE mode; 152 153def bitfield A_BLX aBlx; 154 155def bitfield CPNUM cpNum; 156// Note that FP Regs are only 3 bits 157def bitfield FN fn; 158def bitfield FD fd; 159def bitfield FPREGIMM fpRegImm; 160// We can just use 3:0 for FM since the hard-wired FP regs are handled in 161// float_regfile.hh 162def bitfield FM fm; 163def bitfield FPIMM fpImm; 164def bitfield PUNWL punwl; 165 166// M5 instructions 167def bitfield M5FUNC m5Func; 168 169