xref: /gem5/src/arch/arm/isa/bitfields.isa

// -*- mode:c++ -*-

// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//

// Opcode fields
def bitfield OPCODE        <27:25>;
def bitfield OPCODE_27_25  <27:25>;
def bitfield OPCODE_24_21  <24:21>;
def bitfield OPCODE_24_23  <24:23>;
def bitfield OPCODE_24	   <24:24>;
def bitfield OPCODE_23_20  <23:20>;
def bitfield OPCODE_23_21  <23:21>;
def bitfield OPCODE_23     <23:23>;
def bitfield OPCODE_22_8   <22: 8>;
def bitfield OPCODE_22_21  <22:21>;
def bitfield OPCODE_22     <22:22>;
def bitfield OPCODE_21_20  <21:20>;
def bitfield OPCODE_20     <20:20>;
def bitfield OPCODE_19_18  <19:18>;
def bitfield OPCODE_19	   <19:19>;
def bitfield OPCODE_15_12  <15:12>;
def bitfield OPCODE_15	   <15:15>;
def bitfield OPCODE_9      < 9: 9>;
def bitfield OPCODE_7_4    < 7: 4>;
def bitfield OPCODE_7_5	   < 7: 5>;
def bitfield OPCODE_7_6    < 7: 6>;
def bitfield OPCODE_7      < 7: 7>;
def bitfield OPCODE_6_5	   < 6: 5>;
def bitfield OPCODE_6	   < 6: 6>;
def bitfield OPCODE_5	   < 5: 5>;
def bitfield OPCODE_4      < 4: 4>;

// Other
def bitfield COND_CODE     <31:28>;
def bitfield S_FIELD       <20:20>;
def bitfield RN            <19:16>;
def bitfield RD            <15:12>;
def bitfield SHIFT_SIZE    <11: 7>;
def bitfield SHIFT         < 6: 5>;
def bitfield RM            < 3: 0>;

def bitfield RE            <20:16>;

def bitfield RS            <11: 8>;

def bitfield RDUP          <19:16>;
def bitfield RNDN          <15:12>;

def bitfield RDHI          <15:12>;
def bitfield RDLO          <11: 8>;

def bitfield U_FIELD       <23:23>;

def bitfield PUSWL	   <24:20>;
def bitfield PREPOST	   <24:24>;
def bitfield UP		   <23:23>;
def bitfield PSRUSER	   <22:22>;
def bitfield WRITEBACK	   <21:21>;
def bitfield LOADOP        <20:20>;

def bitfield PUBWL	   <24:20>;
def bitfield PUIWL	   <24:20>;
def bitfield BYTEACCESS	   <22:22>;

def bitfield LUAS	   <23:20>;

def bitfield IMM	   < 7: 0>;
def bitfield IMMED_7_4     < 7: 4>;
def bitfield IMMED_3_0     < 3: 0>;

def bitfield F_MSR         <19:19>;
def bitfield S_MSR         <18:18>;
def bitfield X_MSR         <17:17>;
def bitfield C_MSR         <16:16>;

def bitfield Y_6           < 6: 6>;
def bitfield X_5           < 5: 5>;

def bitfield IMMED_15_4    <15: 4>;

def bitfield W_FIELD       <21:21>;

def bitfield ROTATE        <11: 8>;
def bitfield IMMED_7_0     < 7: 0>;

def bitfield T_FIELD       <21:21>;
def bitfield IMMED_11_0    <11: 0>;

def bitfield IMMED_20_16   <20:16>;
def bitfield IMMED_19_16   <19:16>;

def bitfield IMMED_HI_11_8 <11: 8>;
def bitfield IMMED_LO_3_0  < 3: 0>;

def bitfield ROT           <11:10>;

def bitfield R_FIELD       < 5: 5>;

def bitfield CARET         <22:22>;
def bitfield REGLIST       <15: 0>;

def bitfield OFFSET        <23: 0>;
def bitfield COPRO         <11: 8>;
def bitfield OP1_7_4       < 7: 4>;
def bitfield CM            < 3: 0>;

def bitfield L_FIELD       <22:22>;
def bitfield CD            <15:12>;
def bitfield OPTION        < 7: 0>;

def bitfield OP1_23_20     <23:20>;
def bitfield CN            <19:16>;
def bitfield OP2_7_5       < 7: 5>;

def bitfield OP1_23_21     <23:21>;

def bitfield IMMED_23_0    <23: 0>;
def bitfield M_FIELD       <17:17>;
def bitfield A_FIELD       < 8: 8>;
def bitfield I_FIELD       < 7: 7>;
def bitfield F_FIELD       < 6: 6>;
def bitfield MODE          < 4: 0>;

def bitfield A_BLX         <24:24>;

def bitfield CPNUM	   <11: 8>;
// Note that FP Regs are only 3 bits
def bitfield FN		   <18:16>;
def bitfield FD		   <14:12>;
def bitfield FPREGIMM	   < 3: 3>;
// We can just use 3:0 for FM since the hard-wired FP regs are handled in
// float_regfile.hh
def bitfield FM		   < 3: 0>;
def bitfield FPIMM	   < 2: 0>;
def bitfield PUNWL	   <24:20>;

// M5 instructions
def bitfield M5FUNC <7:0>;