isa.hh revision 8232 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49#include "debug/Checkpoint.hh"
50
51class ThreadContext;
52class Checkpoint;
53class EventManager;
54
55namespace ArmISA
56{
57    class ISA
58    {
59      protected:
60        MiscReg miscRegs[NumMiscRegs];
61        const IntRegIndex *intRegMap;
62
63        void
64        updateRegMap(CPSR cpsr)
65        {
66            switch (cpsr.mode) {
67              case MODE_USER:
68              case MODE_SYSTEM:
69                intRegMap = IntRegUsrMap;
70                break;
71              case MODE_FIQ:
72                intRegMap = IntRegFiqMap;
73                break;
74              case MODE_IRQ:
75                intRegMap = IntRegIrqMap;
76                break;
77              case MODE_SVC:
78                intRegMap = IntRegSvcMap;
79                break;
80              case MODE_MON:
81                intRegMap = IntRegMonMap;
82                break;
83              case MODE_ABORT:
84                intRegMap = IntRegAbtMap;
85                break;
86              case MODE_UNDEFINED:
87                intRegMap = IntRegUndMap;
88                break;
89              default:
90                panic("Unrecognized mode setting in CPSR.\n");
91            }
92        }
93
94      public:
95        void clear();
96
97        MiscReg readMiscRegNoEffect(int misc_reg);
98        MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
99        void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
100        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
101
102        int
103        flattenIntIndex(int reg)
104        {
105            assert(reg >= 0);
106            if (reg < NUM_ARCH_INTREGS) {
107                return intRegMap[reg];
108            } else if (reg < NUM_INTREGS) {
109                return reg;
110            } else {
111                int mode = reg / intRegsPerMode;
112                reg = reg % intRegsPerMode;
113                switch (mode) {
114                  case MODE_USER:
115                  case MODE_SYSTEM:
116                    return INTREG_USR(reg);
117                  case MODE_FIQ:
118                    return INTREG_FIQ(reg);
119                  case MODE_IRQ:
120                    return INTREG_IRQ(reg);
121                  case MODE_SVC:
122                    return INTREG_SVC(reg);
123                  case MODE_MON:
124                    return INTREG_MON(reg);
125                  case MODE_ABORT:
126                    return INTREG_ABT(reg);
127                  case MODE_UNDEFINED:
128                    return INTREG_UND(reg);
129                  default:
130                    panic("Flattening into an unknown mode.\n");
131                }
132            }
133        }
134
135        int
136        flattenFloatIndex(int reg)
137        {
138            return reg;
139        }
140
141        int
142        flattenMiscIndex(int reg)
143        {
144            if (reg == MISCREG_SPSR) {
145                int spsr_idx = NUM_MISCREGS;
146                CPSR cpsr = miscRegs[MISCREG_CPSR];
147                switch (cpsr.mode) {
148                  case MODE_USER:
149                    warn("User mode does not have SPSR\n");
150                    spsr_idx = MISCREG_SPSR;
151                    break;
152                  case MODE_FIQ:
153                    spsr_idx = MISCREG_SPSR_FIQ;
154                    break;
155                  case MODE_IRQ:
156                    spsr_idx = MISCREG_SPSR_IRQ;
157                    break;
158                  case MODE_SVC:
159                    spsr_idx = MISCREG_SPSR_SVC;
160                    break;
161                  case MODE_MON:
162                    spsr_idx = MISCREG_SPSR_MON;
163                    break;
164                  case MODE_ABORT:
165                    spsr_idx = MISCREG_SPSR_ABT;
166                    break;
167                  case MODE_UNDEFINED:
168                    spsr_idx = MISCREG_SPSR_UND;
169                    break;
170                  default:
171                    warn("Trying to access SPSR in an invalid mode: %d\n",
172                         cpsr.mode);
173                    spsr_idx = MISCREG_SPSR;
174                    break;
175                }
176                return spsr_idx;
177            }
178            return reg;
179        }
180
181        void serialize(EventManager *em, std::ostream &os)
182        {
183            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
184            SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
185        }
186        void unserialize(EventManager *em, Checkpoint *cp,
187                const std::string &section)
188        {
189            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
190            UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
191            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
192            updateRegMap(tmp_cpsr);
193        }
194
195        ISA()
196        {
197            SCTLR sctlr;
198            sctlr = 0;
199            miscRegs[MISCREG_SCTLR_RST] = sctlr;
200
201            clear();
202        }
203    };
204}
205
206#endif
207