isa.hh revision 8229
15389Sgblack@eecs.umich.edu/*
25446Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited
35389Sgblack@eecs.umich.edu * All rights reserved
45389Sgblack@eecs.umich.edu *
55389Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall
65389Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual
75389Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating
85389Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software
95389Sgblack@eecs.umich.edu * licensed hereunder.  You may use the software subject to the license
105389Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated
115389Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software,
125389Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form.
135389Sgblack@eecs.umich.edu *
145389Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan
155389Sgblack@eecs.umich.edu * All rights reserved.
165389Sgblack@eecs.umich.edu *
175389Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
185389Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
195389Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
205389Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
215389Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
225389Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
235389Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
245389Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
255389Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
265389Sgblack@eecs.umich.edu * this software without specific prior written permission.
275389Sgblack@eecs.umich.edu *
285389Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
295389Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
305389Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
315389Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
325389Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
335389Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
345389Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
355389Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
365389Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
375389Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
385389Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
395389Sgblack@eecs.umich.edu *
405389Sgblack@eecs.umich.edu * Authors: Gabe Black
415478Snate@binkert.org */
425643Sgblack@eecs.umich.edu
435636Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__
445389Sgblack@eecs.umich.edu#define __ARCH_ARM_ISA_HH__
455637Sgblack@eecs.umich.edu
465389Sgblack@eecs.umich.edu#include "arch/arm/registers.hh"
475389Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh"
485389Sgblack@eecs.umich.edu#include "arch/arm/types.hh"
495389Sgblack@eecs.umich.edu
505389Sgblack@eecs.umich.educlass ThreadContext;
515638Sgblack@eecs.umich.educlass Checkpoint;
525389Sgblack@eecs.umich.educlass EventManager;
535389Sgblack@eecs.umich.edu
545446Sgblack@eecs.umich.edunamespace ArmISA
555389Sgblack@eecs.umich.edu{
565389Sgblack@eecs.umich.edu    class ISA
575389Sgblack@eecs.umich.edu    {
585389Sgblack@eecs.umich.edu      protected:
595446Sgblack@eecs.umich.edu        MiscReg miscRegs[NumMiscRegs];
605638Sgblack@eecs.umich.edu        const IntRegIndex *intRegMap;
615446Sgblack@eecs.umich.edu
625446Sgblack@eecs.umich.edu        void
635643Sgblack@eecs.umich.edu        updateRegMap(CPSR cpsr)
645643Sgblack@eecs.umich.edu        {
655643Sgblack@eecs.umich.edu            switch (cpsr.mode) {
665643Sgblack@eecs.umich.edu              case MODE_USER:
675636Sgblack@eecs.umich.edu              case MODE_SYSTEM:
685446Sgblack@eecs.umich.edu                intRegMap = IntRegUsrMap;
695446Sgblack@eecs.umich.edu                break;
705446Sgblack@eecs.umich.edu              case MODE_FIQ:
715446Sgblack@eecs.umich.edu                intRegMap = IntRegFiqMap;
725446Sgblack@eecs.umich.edu                break;
735635Sgblack@eecs.umich.edu              case MODE_IRQ:
745635Sgblack@eecs.umich.edu                intRegMap = IntRegIrqMap;
755643Sgblack@eecs.umich.edu                break;
765643Sgblack@eecs.umich.edu              case MODE_SVC:
775643Sgblack@eecs.umich.edu                intRegMap = IntRegSvcMap;
785643Sgblack@eecs.umich.edu                break;
795643Sgblack@eecs.umich.edu              case MODE_MON:
805643Sgblack@eecs.umich.edu                intRegMap = IntRegMonMap;
815643Sgblack@eecs.umich.edu                break;
825643Sgblack@eecs.umich.edu              case MODE_ABORT:
835643Sgblack@eecs.umich.edu                intRegMap = IntRegAbtMap;
845643Sgblack@eecs.umich.edu                break;
855446Sgblack@eecs.umich.edu              case MODE_UNDEFINED:
865446Sgblack@eecs.umich.edu                intRegMap = IntRegUndMap;
875389Sgblack@eecs.umich.edu                break;
885638Sgblack@eecs.umich.edu              default:
895389Sgblack@eecs.umich.edu                panic("Unrecognized mode setting in CPSR.\n");
905389Sgblack@eecs.umich.edu            }
915389Sgblack@eecs.umich.edu        }
925389Sgblack@eecs.umich.edu
935389Sgblack@eecs.umich.edu      public:
945389Sgblack@eecs.umich.edu        void clear();
955638Sgblack@eecs.umich.edu
965389Sgblack@eecs.umich.edu        MiscReg readMiscRegNoEffect(int misc_reg);
975389Sgblack@eecs.umich.edu        MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
985389Sgblack@eecs.umich.edu        void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
995389Sgblack@eecs.umich.edu        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
1005389Sgblack@eecs.umich.edu
1015389Sgblack@eecs.umich.edu        int
1025638Sgblack@eecs.umich.edu        flattenIntIndex(int reg)
1035389Sgblack@eecs.umich.edu        {
1045389Sgblack@eecs.umich.edu            assert(reg >= 0);
1055389Sgblack@eecs.umich.edu            if (reg < NUM_ARCH_INTREGS) {
1065389Sgblack@eecs.umich.edu                return intRegMap[reg];
1075389Sgblack@eecs.umich.edu            } else if (reg < NUM_INTREGS) {
1085389Sgblack@eecs.umich.edu                return reg;
1095638Sgblack@eecs.umich.edu            } else {
1105389Sgblack@eecs.umich.edu                int mode = reg / intRegsPerMode;
1115389Sgblack@eecs.umich.edu                reg = reg % intRegsPerMode;
1125389Sgblack@eecs.umich.edu                switch (mode) {
1135389Sgblack@eecs.umich.edu                  case MODE_USER:
1145389Sgblack@eecs.umich.edu                  case MODE_SYSTEM:
1155638Sgblack@eecs.umich.edu                    return INTREG_USR(reg);
1165389Sgblack@eecs.umich.edu                  case MODE_FIQ:
1175389Sgblack@eecs.umich.edu                    return INTREG_FIQ(reg);
1185389Sgblack@eecs.umich.edu                  case MODE_IRQ:
1195389Sgblack@eecs.umich.edu                    return INTREG_IRQ(reg);
1205389Sgblack@eecs.umich.edu                  case MODE_SVC:
1215638Sgblack@eecs.umich.edu                    return INTREG_SVC(reg);
1225389Sgblack@eecs.umich.edu                  case MODE_MON:
1235389Sgblack@eecs.umich.edu                    return INTREG_MON(reg);
1245389Sgblack@eecs.umich.edu                  case MODE_ABORT:
1255389Sgblack@eecs.umich.edu                    return INTREG_ABT(reg);
1265389Sgblack@eecs.umich.edu                  case MODE_UNDEFINED:
1275389Sgblack@eecs.umich.edu                    return INTREG_UND(reg);
1285389Sgblack@eecs.umich.edu                  default:
1295638Sgblack@eecs.umich.edu                    panic("Flattening into an unknown mode.\n");
1305389Sgblack@eecs.umich.edu                }
1315389Sgblack@eecs.umich.edu            }
1325389Sgblack@eecs.umich.edu        }
1335389Sgblack@eecs.umich.edu
1345389Sgblack@eecs.umich.edu        int
1355389Sgblack@eecs.umich.edu        flattenFloatIndex(int reg)
1365389Sgblack@eecs.umich.edu        {
1375638Sgblack@eecs.umich.edu            return reg;
1385638Sgblack@eecs.umich.edu        }
1395389Sgblack@eecs.umich.edu
1405638Sgblack@eecs.umich.edu        int
1415389Sgblack@eecs.umich.edu        flattenMiscIndex(int reg)
142        {
143            if (reg == MISCREG_SPSR) {
144                int spsr_idx = NUM_MISCREGS;
145                CPSR cpsr = miscRegs[MISCREG_CPSR];
146                switch (cpsr.mode) {
147                  case MODE_USER:
148                    warn("User mode does not have SPSR\n");
149                    spsr_idx = MISCREG_SPSR;
150                    break;
151                  case MODE_FIQ:
152                    spsr_idx = MISCREG_SPSR_FIQ;
153                    break;
154                  case MODE_IRQ:
155                    spsr_idx = MISCREG_SPSR_IRQ;
156                    break;
157                  case MODE_SVC:
158                    spsr_idx = MISCREG_SPSR_SVC;
159                    break;
160                  case MODE_MON:
161                    spsr_idx = MISCREG_SPSR_MON;
162                    break;
163                  case MODE_ABORT:
164                    spsr_idx = MISCREG_SPSR_ABT;
165                    break;
166                  case MODE_UNDEFINED:
167                    spsr_idx = MISCREG_SPSR_UND;
168                    break;
169                  default:
170                    warn("Trying to access SPSR in an invalid mode: %d\n",
171                         cpsr.mode);
172                    spsr_idx = MISCREG_SPSR;
173                    break;
174                }
175                return spsr_idx;
176            }
177            return reg;
178        }
179
180        void serialize(EventManager *em, std::ostream &os)
181        {
182            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
183            SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
184        }
185        void unserialize(EventManager *em, Checkpoint *cp,
186                const std::string &section)
187        {
188            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
189            UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
190            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
191            updateRegMap(tmp_cpsr);
192        }
193
194        ISA()
195        {
196            SCTLR sctlr;
197            sctlr = 0;
198            miscRegs[MISCREG_SCTLR_RST] = sctlr;
199
200            clear();
201        }
202    };
203}
204
205#endif
206