isa.hh revision 8181 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49
50class ThreadContext;
51class Checkpoint;
52class EventManager;
53
54namespace ArmISA
55{
56    class ISA
57    {
58      protected:
59        MiscReg miscRegs[NumMiscRegs];
60        const IntRegIndex *intRegMap;
61
62        void
63        updateRegMap(CPSR cpsr)
64        {
65            switch (cpsr.mode) {
66              case MODE_USER:
67              case MODE_SYSTEM:
68                intRegMap = IntRegUsrMap;
69                break;
70              case MODE_FIQ:
71                intRegMap = IntRegFiqMap;
72                break;
73              case MODE_IRQ:
74                intRegMap = IntRegIrqMap;
75                break;
76              case MODE_SVC:
77                intRegMap = IntRegSvcMap;
78                break;
79              case MODE_MON:
80                intRegMap = IntRegMonMap;
81                break;
82              case MODE_ABORT:
83                intRegMap = IntRegAbtMap;
84                break;
85              case MODE_UNDEFINED:
86                intRegMap = IntRegUndMap;
87                break;
88              default:
89                panic("Unrecognized mode setting in CPSR.\n");
90            }
91        }
92
93      public:
94        void clear();
95
96        MiscReg readMiscRegNoEffect(int misc_reg);
97        MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
98        void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
99        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
100
101        int
102        flattenIntIndex(int reg)
103        {
104            assert(reg >= 0);
105            if (reg < NUM_ARCH_INTREGS) {
106                return intRegMap[reg];
107            } else if (reg < NUM_INTREGS) {
108                return reg;
109            } else {
110                int mode = reg / intRegsPerMode;
111                reg = reg % intRegsPerMode;
112                switch (mode) {
113                  case MODE_USER:
114                  case MODE_SYSTEM:
115                    return INTREG_USR(reg);
116                  case MODE_FIQ:
117                    return INTREG_FIQ(reg);
118                  case MODE_IRQ:
119                    return INTREG_IRQ(reg);
120                  case MODE_SVC:
121                    return INTREG_SVC(reg);
122                  case MODE_MON:
123                    return INTREG_MON(reg);
124                  case MODE_ABORT:
125                    return INTREG_ABT(reg);
126                  case MODE_UNDEFINED:
127                    return INTREG_UND(reg);
128                  default:
129                    panic("Flattening into an unknown mode.\n");
130                }
131            }
132        }
133
134        int
135        flattenFloatIndex(int reg)
136        {
137            return reg;
138        }
139
140        int
141        flattenMiscIndex(int reg)
142        {
143            if (reg == MISCREG_SPSR) {
144                int spsr_idx = NUM_MISCREGS;
145                CPSR cpsr = miscRegs[MISCREG_CPSR];
146                switch (cpsr.mode) {
147                  case MODE_USER:
148                    warn("User mode does not have SPSR\n");
149                    spsr_idx = MISCREG_SPSR;
150                    break;
151                  case MODE_FIQ:
152                    spsr_idx = MISCREG_SPSR_FIQ;
153                    break;
154                  case MODE_IRQ:
155                    spsr_idx = MISCREG_SPSR_IRQ;
156                    break;
157                  case MODE_SVC:
158                    spsr_idx = MISCREG_SPSR_SVC;
159                    break;
160                  case MODE_MON:
161                    spsr_idx = MISCREG_SPSR_MON;
162                    break;
163                  case MODE_ABORT:
164                    spsr_idx = MISCREG_SPSR_ABT;
165                    break;
166                  case MODE_UNDEFINED:
167                    spsr_idx = MISCREG_SPSR_UND;
168                    break;
169                  default:
170                    warn("Trying to access SPSR in an invalid mode: %d\n",
171                         cpsr.mode);
172                    spsr_idx = MISCREG_SPSR;
173                    break;
174                }
175                return spsr_idx;
176            }
177            return reg;
178        }
179
180        void serialize(EventManager *em, std::ostream &os)
181        {
182            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
183            SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
184        }
185        void unserialize(EventManager *em, Checkpoint *cp,
186                const std::string &section)
187        {
188            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
189            UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
190            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
191            updateRegMap(tmp_cpsr);
192        }
193
194        ISA()
195        {
196            SCTLR sctlr;
197            sctlr = 0;
198            miscRegs[MISCREG_SCTLR_RST] = sctlr;
199
200            clear();
201        }
202    };
203}
204
205#endif
206