isa.hh revision 7405 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/types.hh"
49
50class ThreadContext;
51class Checkpoint;
52class EventManager;
53
54namespace ArmISA
55{
56    class ISA
57    {
58      protected:
59        MiscReg miscRegs[NumMiscRegs];
60        const IntRegIndex *intRegMap;
61
62        void
63        updateRegMap(CPSR cpsr)
64        {
65            switch (cpsr.mode) {
66              case MODE_USER:
67              case MODE_SYSTEM:
68                intRegMap = IntRegUsrMap;
69                break;
70              case MODE_FIQ:
71                intRegMap = IntRegFiqMap;
72                break;
73              case MODE_IRQ:
74                intRegMap = IntRegIrqMap;
75                break;
76              case MODE_SVC:
77                intRegMap = IntRegSvcMap;
78                break;
79              case MODE_MON:
80                intRegMap = IntRegMonMap;
81                break;
82              case MODE_ABORT:
83                intRegMap = IntRegAbtMap;
84                break;
85              case MODE_UNDEFINED:
86                intRegMap = IntRegUndMap;
87                break;
88              default:
89                panic("Unrecognized mode setting in CPSR.\n");
90            }
91        }
92
93      public:
94        void clear()
95        {
96            SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
97
98            memset(miscRegs, 0, sizeof(miscRegs));
99            CPSR cpsr = 0;
100            cpsr.mode = MODE_USER;
101            miscRegs[MISCREG_CPSR] = cpsr;
102            updateRegMap(cpsr);
103
104            SCTLR sctlr = 0;
105            sctlr.nmfi = (bool)sctlr_rst.nmfi;
106            sctlr.v = (bool)sctlr_rst.v;
107            sctlr.u    = 1;
108            sctlr.rao1 = 1;
109            sctlr.rao2 = 1;
110            sctlr.rao3 = 1;
111            sctlr.rao4 = 1;
112            miscRegs[MISCREG_SCTLR] = sctlr;
113            miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
114
115
116            /*
117             * Technically this should be 0, but we don't support those
118             * settings.
119             */
120            CPACR cpacr = 0;
121            // Enable CP 10, 11
122            cpacr.cp10 = 0x3;
123            cpacr.cp11 = 0x3;
124            miscRegs[MISCREG_CPACR] = cpacr;
125
126            /* Start with an event in the mailbox */
127            miscRegs[MISCREG_SEV_MAILBOX] = 1;
128
129            /*
130             * Implemented = '5' from "M5",
131             * Variant = 0,
132             */
133            miscRegs[MISCREG_MIDR] =
134                (0x35 << 24) | //Implementor is '5' from "M5"
135                (0 << 20)    | //Variant
136                (0xf << 16)  | //Architecture from CPUID scheme
137                (0 << 4)     | //Primary part number
138                (0 << 0)     | //Revision
139                0;
140
141            // Separate Instruction and Data TLBs.
142            miscRegs[MISCREG_TLBTR] = 1;
143
144            MVFR0 mvfr0 = 0;
145            mvfr0.advSimdRegisters = 2;
146            mvfr0.singlePrecision = 2;
147            mvfr0.doublePrecision = 2;
148            mvfr0.vfpExceptionTrapping = 0;
149            mvfr0.divide = 1;
150            mvfr0.squareRoot = 1;
151            mvfr0.shortVectors = 1;
152            mvfr0.roundingModes = 1;
153            miscRegs[MISCREG_MVFR0] = mvfr0;
154
155            MVFR1 mvfr1 = 0;
156            mvfr1.flushToZero = 1;
157            mvfr1.defaultNaN = 1;
158            mvfr1.advSimdLoadStore = 1;
159            mvfr1.advSimdInteger = 1;
160            mvfr1.advSimdSinglePrecision = 1;
161            mvfr1.advSimdHalfPrecision = 1;
162            mvfr1.vfpHalfPrecision = 1;
163            miscRegs[MISCREG_MVFR1] = mvfr1;
164
165            miscRegs[MISCREG_MPIDR] = 0;
166
167            //XXX We need to initialize the rest of the state.
168        }
169
170        MiscReg readMiscRegNoEffect(int misc_reg);
171
172        MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
173
174        void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
175
176        void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
177
178        int
179        flattenIntIndex(int reg)
180        {
181            assert(reg >= 0);
182            if (reg < NUM_ARCH_INTREGS) {
183                return intRegMap[reg];
184            } else if (reg < NUM_INTREGS) {
185                return reg;
186            } else {
187                int mode = reg / intRegsPerMode;
188                reg = reg % intRegsPerMode;
189                switch (mode) {
190                  case MODE_USER:
191                  case MODE_SYSTEM:
192                    return INTREG_USR(reg);
193                  case MODE_FIQ:
194                    return INTREG_FIQ(reg);
195                  case MODE_IRQ:
196                    return INTREG_IRQ(reg);
197                  case MODE_SVC:
198                    return INTREG_SVC(reg);
199                  case MODE_MON:
200                    return INTREG_MON(reg);
201                  case MODE_ABORT:
202                    return INTREG_ABT(reg);
203                  case MODE_UNDEFINED:
204                    return INTREG_UND(reg);
205                  default:
206                    panic("Flattening into an unknown mode.\n");
207                }
208            }
209        }
210
211        int
212        flattenFloatIndex(int reg)
213        {
214            return reg;
215        }
216
217        void serialize(EventManager *em, std::ostream &os)
218        {}
219        void unserialize(EventManager *em, Checkpoint *cp,
220                const std::string &section)
221        {}
222
223        ISA()
224        {
225            SCTLR sctlr;
226            sctlr = 0;
227            miscRegs[MISCREG_SCTLR_RST] = sctlr;
228
229            clear();
230        }
231    };
232}
233
234#endif
235